Deposition ring for a semiconductor processing chamber

FIG. 1 is an enlarged top isometric view of a deposition ring for a semiconductor processing chamber, according to the first embodiment of the novel design.

FIG. 2 is a front elevation view thereof.

FIG. 3 is a back elevation view thereof.

FIG. 4 is a right elevation view thereof.

FIG. 5 is a left elevation view thereof.

FIG. 6 is a top plan view thereof.

FIG. 7 is a bottom plan view thereof.

FIG. 8 is an enlarged cross-sectional view thereof, taken along line 6 - 6 of FIG. 6 .

FIG. 9 is an enlarged top isometric view of a deposition ring for a semiconductor processing chamber, according to the second embodiment of the novel design.

FIG. 10 is a front elevation view thereof.

FIG. 11 is a back elevation view thereof.

FIG. 12 is a right elevation view thereof.

FIG. 13 is a left elevation view thereof.

FIG. 14 is a top plan view thereof.

FIG. 15 is a bottom plan view thereof.

FIG. 16 is an enlarged cross-sectional view thereof, taken along line 16 - 16 of FIG. 14 ; and,

FIG. 17 is an enlarged cross-sectional view thereof, taken along line 17 - 17 of FIG. 14 .

The dashed lines in FIGS. 1-9 represent unclaimed environment forming no part of the claimed design.