Bulk FinFET ESD device

The disclosure relates generally to semiconductor devices, and more particularly, to a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same.

In manufacturing multi-gate field effect transistors (FETs) that include a plurality of fin structures (i.e., a FinFET), electrostatic discharge (ESD) protection devices are often required. However, passive devices that are used for ESD protection are difficult to build on FinFET structures. Passive devices have a preference towards planar silicon regions, which are not usually available in FinFET structures.

Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.

A first aspect of the disclosure provides a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology, comprising: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.

A second aspect of the disclosure provides a method of manufacturing a dual ESD protection device in fin field effect transistor (FinFET) process technology, the method comprising: providing a bulk silicon wafer substrate; forming a plurality of fins on a top portion of the bulk silicon wafer substrate; forming an oxide isolation region between each of the fins, the oxide isolation region including a shallow trench isolation (STI); performing a selective epitaxial growth process to merge a portion of the plurality of fins; and patterning, etching, and implanting the portion of the plurality of fins to form the dual ESD protection device including: a first ESD device positioned above the oxide isolation region; and a second ESD device positioned below the oxide isolation region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the oxide isolation region.

The above and other aspects, features and advantages of the disclosure will be better understood by reading the following more particular description of the disclosure in conjunction with the accompanying drawings.

FIG. 1 shows a cross-sectional view of a conventional fin field effect transistor.

FIG. 2 shows a cross-sectional view of a fin field effect transistor according to embodiments of the invention.

FIG. 3A shows a cross-sectional view of a fin field effect transistor including at least one ESD device according to embodiments of the invention.

FIG. 3B shows a schematic diagram of a fin field effect transistor including at least one ESD device according to embodiments of the invention.

FIG. 4A shows a cross-sectional view of a fin field effect transistor including at least one ESD device according to embodiments of the invention.

FIG. 4B shows a schematic diagram of a fin field effect transistor including at least one ESD device according to embodiments of the invention.

FIG. 5A shows a cross-sectional view of a fin field effect transistor including at least one ESD device according to embodiments of the invention.

FIG. 5B shows a schematic diagram of a fin field effect transistor including at least one ESD device according to embodiments of the invention.

The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict only typical embodiments of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements.

As mentioned above, the disclosure relates generally to semiconductor devices, and more particularly, to a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin structure and methods of forming the same.

In manufacturing multi-gate field effect transistors (FETs) that include a plurality of fin structures (i.e., a FinFET), electrostatic discharge (ESD) protection devices are often required. However, passive devices that are used for ESD protection are difficult to build on FinFET structures. Passive devices have a preference towards planar silicon regions, which are not usually available in FinFET structures. Therefore, it is desired to be able to manufacture a FinFET structure including at least one ESD protection device.

Turning now to FIG. 1 , a cross-sectional view of a conventional FinFET transistor 100 is shown. It is understood that, using standard FinFET manufacturing technology, a plurality of fins 10 are formed above a bulk silicon substrate 12 . Between each fin 10 is a shallow trench isolation (STI) region 14 . As mentioned above, a passive ESD device cannot be built on top of the plurality of fins 10 .

Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.

Turning now to FIG. 2 , a cross-sectional view of a FinFET transistor 200 according to embodiments of the invention is shown. Between the plurality of fins 10 , a silicon portion 16 is formed. Silicon portion 16 may be formed using, for example, a selective epitaxial growth process, as known in the art. The silicon portion 16 merges the plurality of fins 10 to create a planar surface 18 in an area where it is desired to have a passive ESD device. Although not shown, if more silicon is desired on the planar surface 18 (i.e., in order to dissipate heat), a further selective epitaxial growth process may be performed. Once the planar surface 18 has been created, patterning, etching, and implanting, as known in the art, may be performed in order to form at least one ESD device on the planar surface 18 . Standard patterning, etching, and implanting may also be performed to form FinFET devices in the non-planar region.

Turning now to FIG. 3A , a cross-sectional view of a FinFET 200 including at least one ESD device according to embodiments of the invention is shown. It is understood that only the planar surface 18 ( FIG. 2 ) portion of FinFET 200 is shown for clarity purposes. That is, fins 10 may be implanted to be an NW region, or a p+ region. Further, a portion of the bulk silicon substrate 12 may be implanted as an Nwell region. In this embodiment, FinFET 200 includes a dual ESD protection device. A first ESD protection device 20 is positioned above the STI region 14 . For example, in FIG. 3A , the first ESD device 20 is a lateral device and is a pn junction diode (from the p+ region to the NW region). A second ESD device 25 is provided below the STI region 14 and is also a pn junction diode (from p+ region to Nwell region). As seen in the schematic diagram of FinFET 200 shown in FIG. 3B , a dual ESD protection device 250 is formed by the first ESD device 20 and the second ESD device 25 .

Turning now to FIG. 4A , a cross-sectional view of a FinFET 300 including at least one ESD device according to embodiments of the invention is shown. It is understood that only the planar surface 18 ( FIG. 2 ) portion of FinFET 300 is shown for clarity purposes. That is, fins 10 may be implanted as an n+ and a p+ region, while the silicon portion 16 that merges fins 10 together may be partially implanted as a PW region and partially implanted as an NW region. Further, a portion of the bulk silicon substrate 12 may be appropriately implanted. In this embodiment, FinFET 300 also includes a dual ESD protection device. A first ESD protection device 30 is positioned above the STI region 14 . For example, in FIG. 4A , the first ESD device 30 is a lateral device and is a thyristor formed by a pnpn junction (from the p+ region to the NW region to the PW region to the n+ region). A second ESD device 35 is provided below the STI region 14 and is also a thyristor formed by a pnpn junction (from p+ region to Nwell region to P region to n+ region). As seen in the schematic diagram of FinFET 300 shown in FIG. 4B , a dual ESD protection device 350 is formed by the first ESD device 30 and the second ESD device 35 .

Turning now to FIG. 5A , a cross-sectional view of a FinFET 400 including at least one ESD device according to embodiments of the invention is shown. It is understood that only the planar surface 18 ( FIG. 2 ) portion of FinFET 400 is shown for clarity purposes. That is, fins 10 are implanted to be an n+ region, and silicon portion 16 that merges fins 10 together is implanted as a PW region. In this embodiment, FinFET 400 also includes a dual ESD protection device. A first ESD protection device 40 is positioned above the STI region 14 . For example, in FIG. 4A , the first ESD device 40 is a lateral device and is a lateral npn transistor formed by a npn junction (from the n+ region to the PW region to the n+ region). A second ESD device 45 is provided below the STI region 14 and is also a lateral npn transistor formed by a npn junction (from the n+ region to the PWell region to the n+ region). As seen in the schematic diagram of FinFET 400 shown in FIG. 4B , a dual ESD protection device 350 is formed by the first ESD device 40 and the second ESD device 45 .

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.