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Inventor

Junjun Li

Inventor
Williston, VT, US

Overview

135→
Patents
2006–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 135 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices37%
H01LSemiconductor devices21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
G06FElectric digital data processing7%
H02HEmergency protective circuit arrangements7%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H03KPulse technique1%
Y10TTechnical subjects covered by former us classification1%
G01RMeasuring electric variables1%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
PatentTitleYear
10,857,389Proton therapy system based on compact superconducting cyclotron202010,861,055Method and system for identifying users across mobile and desktop devices202010,773,312Preparation method for silver nanowires with uniform aspect ratio and nodes202010,755,949Structures, methods and applications for electrical pulse anneal processes202010,756,078Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers202010,748,893Electrostatic discharge devices and methods of manufacture202010,423,985Method and system for identifying users across mobile and desktop devices201910,375,815Method for adjusting particle orbit alignment by using first harmonic in cyclotron201910,283,374Structures, methods and applications for electrical pulse anneal processes201910,229,905Electrostatic discharge devices and methods of manufacture201910,224,710Electrostatic discharge power clamp with fail-safe design201910,186,860Electrostatic discharge device with fail-safe design201910,181,463Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers201910,163,892Silicon controlled rectifiers (SCR), methods of manufacture and design structures201810,157,908Electrostatic discharge devices and methods of manufacture201810,079,487Clamp circuit for electrical overstress and electrostatic discharge201810,037,895Structures, methods and applications for electrical pulse anneal processes20189,954,002Multi-gate field effect transistor (FET) including isolated FIN body20189,882,376'Electrostatic discharge power clamp with fail-safe design'20189,881,810'Structures, methods and applications for electrical pulse anneal processes'20189,704,848'Electrostatic discharge devices and methods of manufacture'20179,673,116'On chip electrostatic discharge (ESD) event monitoring'20179,653,448'Electrostatic discharge (ESD) diode in FinFET technology'20179,620,497'Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers'20179,601,480'Single junction bi-directional electrostatic discharge (ESD) protection circuit'20179,575,115'Methodology of grading reliability and performance of chips across wafer'20179,536,870'SCR with fin body regions for ESD protection'20179,461,149'Nanowire structure with selected stack removed for reduced gate resistance and method of fabricating same'20169,453,878'Characterization of interface resistance in a multi-layer conductive structure'20169,425,185'Self-healing electrostatic discharge power clamp'20169,425,184'Electrostatic discharge devices and methods of manufacture'20169,413,169'Electrostatic discharge protection circuit with a fail-safe mechanism'20169,397,086'Passive devices for FinFET integrated circuit technologies'20169,361,322'Unidirectional lookalike campaigns in a messaging platform'20169,349,838'Semiconductor structure with deep trench thermal conduction'20169,349,732'High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region'20169,331,177'Semiconductor structure with deep trench thermal conduction'20169,318,479'Electrostatic discharge (ESD) silicon controlled rectifier (SCR) with lateral gated section'20169,287,178'Multi-gate field effect transistor (FET) including isolated fin body'20169,281,303'Electrostatic discharge devices and methods of manufacture'20169,263,402'Self-protected metal-oxide-semiconductor field-effect transistor'20169,252,242'Semiconductor structure with deep trench thermal conduction'20169,240,471'SCR with fin body regions for ESD protection'20169,236,398'Passive devices for FinFET integrated circuit technologies'20169,219,056'Passive devices for FinFET integrated circuit technologies'20159,093,453'High performance e-fuse fabricated with sub-lithographic dimension'20159,087,808'Fabricating polysilicon MOS devices and passive ESD devices'20159,070,629'Through silicon via repair'20159,064,786'Dual three-dimensional (3D) resistor and methods of forming'20159,058,995'Self-protected drain-extended metal-oxide-semiconductor transistor'20159,059,198'Bi-directional silicon controlled rectifier structure'20159,059,278'High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region'20159,041,127'FinFET device technology with LDMOS structures for high voltage operations'20159,029,206'Electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure'20159,024,411'Conductor with sub-lithographic self-aligned 3D confinement'20159,006,783'Silicon controlled rectifier with integral deep trench capacitor'20158,987,073'Self-protected metal-oxide-semiconductor field-effect transistor'20158,956,925'Silicon controlled rectifier structure with improved junction breakdown and leakage control'20158,954,306'Component behavior modeling using separate behavior model'20158,951,893'Fabricating polysilicon MOS devices and passive ESD devices'20158,946,766'Bi-directional silicon controlled rectifier structure'20158,940,588'Bulk FinFET ESD devices'20158,929,040'ESD protection device for SST transmitter'20158,916,426'Passive devices for FinFET integrated circuit technologies'20148,912,625'Semiconductor-on-insulator device with asymmetric structure'20148,906,751'Silicon controlled rectifiers (SCR), methods of manufacture and design structures'20148,890,249'Bulk FinFET ESD device'20148,891,212'RC-triggered semiconductor controlled rectifier for ESD protection of signal pads'20148,847,354'Metal-insulator-metal capacitors with high capacitance density'20148,841,174'Silicon controlled rectifier with integral deep trench capacitor'20148,815,654'Vertical current controlled silicon on insulator (SOI) device such as a silicon controlled rectifier and method of forming vertical SOI current controlled devices'20148,809,967'Device structures compatible with fin-type field-effect transistor technologies'20148,809,129'Diode-triggered silicon controlled rectifier with an integrated diode'20148,796,731'Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure'20148,760,827'Robust ESD protection circuit, method and design structure for tolerant and failsafe designs'20148,760,831'Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures'20148,759,194'Device structures compatible with fin-type field-effect transistor technologies'20148,748,985'Semiconductor structures with thinned junctions and methods of manufacture'20148,737,028'RC-triggered ESD clamp device with feedback for time constant adjustment'20148,730,624'Electrostatic discharge power clamp with a JFET based RC trigger circuit'20148,692,291'Passive devices for FinFET integrated circuit technologies'20148,692,290'Silicon controlled rectifier structure with improved junction breakdown and leakage control'20148,686,508'Structures, methods and applications for electrical pulse anneal processes'20148,680,573'Diode-triggered silicon controlled rectifier with an integrated diode'20148,674,400'Stress enhanced junction engineering for latchup SCR'20148,669,146'Semiconductor structures with thinned junctions and methods of manufacture'20148,642,452'Semiconductor-on-insulator device with asymmetric structure'20148,637,900'Electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure'20148,637,353'Through silicon via repair'20148,637,388'Semiconductor device heat dissipation structure'20148,634,174'Gate dielectric breakdown protection during ESD events'20148,614,121'Method of manufacturing back gate triggered silicon controlled rectifiers'20138,614,489'Vertical NPNP structure in a triple well CMOS process'20138,610,249'Non-planar capacitor and method of forming the non-planar capacitor'20138,610,217'Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit'20138,585,848'Method of creating wrinkle structures for reversible and irreversible applications'20138,575,718'Programmable electrical fuse'20138,513,738'ESD field-effect transistor and integrated diffusion resistor'20138,514,535'Electrostatic discharge device control and structure'20138,503,140'Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures'20138,489,378'Silicon controlled rectifier modeling'20138,445,355'Metal-insulator-metal capacitors with high capacitance density'20138,421,128'Semiconductor device heat dissipation structure'20138,390,068'Electrostatic discharge protection device and method of fabricating same'20138,384,125'Structure and method for a silicon controlled rectifier (SCR) structure for SOI technology'20138,377,754'Stress enhanced junction engineering for latchup SCR'20138,373,267'Electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure'20138,363,367'Electrical overstress protection circuit'20138,354,722'SCR/MOS clamp for ESD protection of integrated circuits'20138,350,329'Low trigger voltage electrostatic discharge NFET in triple well CMOS technology'20138,299,533'Vertical NPNP structure in a triple well CMOS process'20128,230,382'Model based simulation of electronic discharge and optimization methodology for design checking'20128,217,455'Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures'20128,138,546'Electrostatic discharge protection device and method of fabricating same'20128,101,505'Programmable electrical fuse'20128,039,868'Structure and method for an electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure'20118,010,927'Structure for a stacked power clamp having a BigFET gate pull-up circuit'20117,968,908'Bidirectional electrostatic discharge protection structure for high voltage applications'20117,956,671'Circuit structure and method for programming and re-programming a low power, multiple states, electronic fuse (e-fuse)'20117,943,438'Structure and method for a silicon controlled rectifier (SCR) structure for SOI technology'20117,881,028'E-fuse used to disable a triggering network'20117,826,185'Structure and circuit technique for uniform triggering of multifinger semiconductor devices with tunable trigger voltage'20107,826,188'Methods, design structures, and systems for current mode logic (CML) differential driver ESD protection circuitry'20107,786,535'Design structures for high-voltage integrated circuits'20107,782,580'Stacked power clamp having a BigFET gate pull-up circuit'20107,772,651'Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits'20107,746,607'Substrate triggering for ESD protection in SOI'20107,714,356'Design structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage'20107,646,573'Method for improved triggering and oscillation suppression of ESD clamping devices'20107,518,845'RC-triggered power clamp suppressing negative mode electrostatic discharge stress'20097,399,665'Electrostatic discharge protection device and method of fabricating same'20087,397,641'Apparatus and method for improved triggering and oscillation suppression of ESD clamping devices'20087,298,008'Electrostatic discharge protection device and method of fabricating same'20077,274,546'Apparatus and method for improved triggering and leakage current control of ESD clamping devices'20077,085,113'ESD protection power clamp for suppressing ESD events occurring on power supply terminals'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2020Patents assigned to IBM (115)· patent assignee history
2007–2020Based in Williston, VT, US· patent location history
2012–2015Patents assigned to LI JUNJUN (45)· patent assignee history
2012–2015Patents assigned to GAUTHIER JR ROBERT J (42)· patent assignee history
2012–2014Patents assigned to MITRA SOUVICK (19)· patent assignee history
2012–2014Patents assigned to ABOU-KHALIL MICHEL J (13)· patent assignee history
2016–2020Based in Cupertino, CA, US· patent location history
2016–2017Based in San Jose, CA, US· patent location history
2019–2020Based in Anhui, CN· patent location history
2019–2020Based in Redwood City, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM1152006–2020
LI JUNJUNself452012–2015
GAUTHIER JR ROBERT J422012–2015
MITRA SOUVICK192012–2014
ABOU-KHALIL MICHEL J132012–2014
Locations
LocationPatentsSpan
Williston, VT, US1102007–2020
Cupertino, California, US92016–2020
San Jose, California, US32016–2017
Anhui, CN22019–2020
Redwood City, California, US22019–2020