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Inventor

Tom C. Lee

Inventor
Essex Junction, VT, US

Overview

75→
Patents
2006–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 75 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices26%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H01LSemiconductor devices17%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
G01RMeasuring electric variables4%
H02HEmergency protective circuit arrangements3%
G06FElectric digital data processing2%
G11CStatic stores2%
H10NElectric solid-state devices not otherwise provided for2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
10,755,949Structures, methods and applications for electrical pulse anneal processes202010,297,589Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode201910,283,374Structures, methods and applications for electrical pulse anneal processes201910,109,599Integrated circuit structure with continuous metal crack stop201810,037,895Structures, methods and applications for electrical pulse anneal processes20189,881,810'Structures, methods and applications for electrical pulse anneal processes'20189,831,194Edge compression layers20179,704,852'Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode'20179,685,370'Titanium tungsten liner used with copper interconnects'20179,575,115'Methodology of grading reliability and performance of chips across wafer'20179,536,870'SCR with fin body regions for ESD protection'20179,425,185'Self-healing electrostatic discharge power clamp'20169,413,169'Electrostatic discharge protection circuit with a fail-safe mechanism'20169,391,065'Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode'20169,287,345'Semiconductor structure with thin film resistor and terminal bond pad'20169,240,471'SCR with fin body regions for ESD protection'20169,070,629'Through silicon via repair'20159,064,786'Dual three-dimensional (3D) resistor and methods of forming'20159,006,783'Silicon controlled rectifier with integral deep trench capacitor'20158,945,955'Method of changing reflectance or resistance of a region in an optoelectronic memory device'20158,940,588'Bulk FinFET ESD devices'20158,912,625'Semiconductor-on-insulator device with asymmetric structure'20148,890,249'Bulk FinFET ESD device'20148,891,212'RC-triggered semiconductor controlled rectifier for ESD protection of signal pads'20148,847,354'Metal-insulator-metal capacitors with high capacitance density'20148,841,174'Silicon controlled rectifier with integral deep trench capacitor'20148,822,993'Integrated circuit including sensor structure, related method and design structure'20148,815,733'Isolated wire structures with reduced stress, methods of manufacturing and design structures'20148,803,284'Thick on-chip high-performance wiring structures'20148,765,595'Thick on-chip high-performance wiring structures'20148,760,831'Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures'20148,748,985'Semiconductor structures with thinned junctions and methods of manufacture'20148,737,028'RC-triggered ESD clamp device with feedback for time constant adjustment'20148,686,508'Structures, methods and applications for electrical pulse anneal processes'20148,669,146'Semiconductor structures with thinned junctions and methods of manufacture'20148,659,173'Isolated wire structures with reduced stress, methods of manufacturing and design structures'20148,642,452'Semiconductor-on-insulator device with asymmetric structure'20148,637,388'Semiconductor device heat dissipation structure'20148,637,353'Through silicon via repair'20148,610,249'Non-planar capacitor and method of forming the non-planar capacitor'20138,592,941'Fuse structure having crack stop void, method for forming and programming same, and design structure'20138,586,466'Electrical fuse with a current shunt'20138,575,718'Programmable electrical fuse'20138,562,210'Thermal sensor for semiconductor circuits'20138,563,336'Method for forming thin film resistor and terminal bond pad simultaneously'20138,503,140'Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures'20138,445,355'Metal-insulator-metal capacitors with high capacitance density'20138,421,128'Semiconductor device heat dissipation structure'20138,288,747'Optoelectronic memory devices'20128,236,655'Fuse link structures using film stress for programming and methods of manufacture'20128,217,455'Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures'20128,101,505'Programmable electrical fuse'20128,089,105'Fuse link structures using film stress for programming and methods of manufacture'20128,084,864'Electromigration resistant aluminum-based metal interconnect structure'20118,021,950'Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation'20118,018,017'Thermo-mechanical cleavable structure'20118,003,536'Electromigration resistant aluminum-based metal interconnect structure'20117,981,732'Programming of laser fuse'20117,956,671'Circuit structure and method for programming and re-programming a low power, multiple states, electronic fuse (e-fuse)'20117,892,926'Fuse link structures using film stress for programming and methods of manufacture'20117,890,893'Design structure for semiconductor on-chip repair scheme for negative bias temperature instability'20117,881,028'E-fuse used to disable a triggering network'20117,838,958'Semiconductor on-chip repair scheme for negative bias temperature instability'20107,786,535'Design structures for high-voltage integrated circuits'20107,772,651'Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits'20107,768,815'Optoelectronic memory devices'20107,692,439'Structure for modeling stress-induced degradation of conductive interconnects'20107,639,032'Structure for monitoring stress-induced degradation of conductive interconnects'20097,512,506'IC chip stress testing'20097,397,260'Structure and method for monitoring stress-induced degradation of conductive interconnects'20087,384,824'Structure and programming of laser fuse'20087,378,866'Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices'20087,345,503'Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices'20087,166,913'Heat dissipation for heat generating element of semiconductor device and related method'20077,064,409'Structure and programming of laser fuse'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2020Patents assigned to IBM (67)· patent assignee history
2006–2020Based in Essex Junction, VT, US· patent location history
2011–2014Patents assigned to LEE TOM C (23)· patent assignee history
2012–2014Patents assigned to GAUTHIER JR ROBERT J (13)· patent assignee history
2012–2014Patents assigned to LI JUNJUN (13)· patent assignee history
2012–2014Patents assigned to MITRA SOUVICK (13)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM672006–2020
LEE TOM Cself232011–2014
GAUTHIER JR ROBERT J132012–2014
LI JUNJUN132012–2014
MITRA SOUVICK132012–2014
Locations
LocationPatentsSpan
Essex Junction, VT, US752006–2020