Active noise-canceling scheme for dynamic circuits

High fan-in domino gates tend to be leaky and prone to noise. Examples of such gates are high fan-in dynamic NOR gates used in schedulers and register files. The inputs to these dynamic gates may traverse long distances running parallel to each other. A capacitive charge may develop between neighboring read-select lines, which may increase with the length of the wires, their height, and inversely to the distance between them.

The inter-wire coupling capacitance between the read-select lines may be a significant source of noise, and may affect the performance of the high fan-in domino gates. One technique for dealing with capacitive coupled noise in the circuit is to replace the leaky high fan-in domino gates with gates that include transistors with high threshold voltages (V t ). However, the use of high V t devices may entail certain performance trade-offs.

FIG. 1 is a schematic diagram of a dynamic circuit including a noise canceling circuit according to an embodiment.

FIG. 2 is a timing diagram for signals in the circuit illustrated in FIG. 1 .

FIG. 1 illustrates a register file circuit 100 including a noise-canceling circuit 102 according to an embodiment. The noise canceling circuit 102 may decouple noise at the input of a high fan-in domino gate 104 that is induced by charge coupling affects caused by transitions on adjacent read-select lines.

The domino gate 104 illustrated is a high fan-in dynamic NOR gate. The NOR gate includes a PMOS transistor 110 with a source coupled to Vcc, a local bitline 112 , and a parallel stack of NMOS transistors. Each stack includes an NMOS transistor 116 with a drain coupled with the local bit line 112 and a source coupled to the drain of another NMOS transistor 114 . The source of NMOS transistor 114 is coupled to ground. The gate of transistor 116 is controlled by the readselect — 1 signal 120 . The gate of transistor 114 is controlled by a data 0 signal.

Transistors 117 and 115 form another similar stack with the gate of 117 controlled by another readselect signal, e.g., readselect_N, and the gate of 115 controlled by another data signal, e.g., data N .

The readselect signals reaadselect — 0 . . . readselect_N may be mutually exclusive. Thus, only one of them can transition high at any point, causing the local bitline to discharge depending on the value of the data signal that it is stacked with. Thus, a NOR operation is performed.

The gate of the PMOS transistor 110 is controlled by a clock signal Clk 2 . The Clk 2 signal causes the dynamic NOR gate 104 to transition between a pre-charge mode and an evaluate mode each system clock cycle. The read-select line 120 is controlled by a dynamic driver 130 , which in turn is controlled to transition between the pre-charge and evaluate modes by a Φ1 clock signal. Exemplary timing signals for the Φ1 and Clk 2 clock signals are shown in FIG. 2 .

The dynamic NOR gate 104 enters the pre-charge mode when Clk 2 transitions LOW and the PMOS transistor 110 turns on, opening the path to Vcc. The signals are timed such that when the PMOS transistor turns on, the signal on the read-select line 120 is LOW, and the input NMOS transistors 116 and 117 are off. This closes the path from the local bitline 112 through the NMOS transistors 114 , 115 and ground. Accordingly, during pre-charge, the bitline 112 is pulled HIGH.

The dynamic NOR gate 104 enters the evaluate mode when Clk 2 transitions HIGH, turning off the PMOS transistor 110 and closing the path to Vcc. During evaluation, if the read-select line 120 transitions HIGH, the input transistor 116 will turn on, opening a path between the HIGH signal on the bitline 112 and the NMOS transistors 114 . If data signal data 0 at the gate of the NMOS transistor 114 is HIGH, transistor 114 will turn on. This will open a discharge path to ground, and the bitline 112 will be pulled LOW. If the data signal data 0 is LOW, the NMOS transistor 114 will be OFF, and the signal on the bitline 112 will remain HIGH. These conditions give the dynamic circuit 104 its NOR gate functionality.

The input transistors of high fan-in domino gates tend to be leaky. Even when the signal on the read-select line 120 at the gates of the input transistors 116 , 117 is LOW, the input transistors 116 , 117 may not be completely turned off. This may create a discharge path from Vcc to ground during evaluation mode, which may impair the performance of the device and potentially compromise the logic level of the bitline 112 .

In order to avoid such leakage, the input transistors 116 may be replaced with transistors with higher threshold voltages (V t ) to reduce the leakage and the improve gate's robustness to noise. However, the use of higher V t devices may entail certain performance trade-offs.

Alternatively, a low V t enabler circuit 140 may be coupled to a static inverter 150 at the output of the dynamic driver 130 . The low V t enabler circuit 140 includes an NMOS transistor 142 coupled between an NMOS transistor 152 in the static inverter 150 , and a capacitor 144 coupled between the drain of the NMOS transistor 142 and its gate. The node 160 at the drain of the NMOS transistor may be considered a virtual ground node 160 (V g ). The NMOS transistor is controlled by a clock signal {overscore (Clk)} 2 , which is the approximate complement of the Clk 2 signal, as shown in FIG. 2 . During evaluation, {overscore (Clk)} 2 transitions LOW, and the NMOS transistor 142 turns off, closing the path to ground. The capacitor 144 pulls the virtual ground node 160 a voltage −ΔV, which is slightly below ground, in response to the falling transition at the gate. This ΔV may be between about 10 mV and 100 mV, depending on the size and type of the transistors, and the size of the capacitor 144 .

When the NMOS transistor 152 in the inverter is ON, which is the case when the read-select line 120 is not selected, the path to the virtual ground node 160 is opened, and the read-select line 120 is pulled to the voltage on the virtual ground node 160 . During evaluation, when V g is at −ΔV, the negative voltage under-drives the gate terminals of the low V t input NMOS transistors 116 in the high fan-in domino gate. Under-driving the gates of the transistors 116 causes them to turn strongly OFF, thereby reducing the amount of leakage in the circuit. During pre-charge, Clk 2 goes HIGH, which restores the virtual ground node 160 and the gates of input transistors 116 to 0 V. Hence, the evaluation delay in one cycle is unaffected by the under-driving operation in the previous cycle.

The negative voltage −ΔV on the virtual ground node 160 may be susceptible to noise, which may negate the benefits provided by the low V t enabler circuit 140 . Noise may be induced by signal transitions on adjacent readselect lines 170 . A capacitive charge may develop between neighboring wires in an integrated circuit, which may increase with the length of the wires, their height, and inversely to the distance between them. This inherent capacitance is represented in FIG. 1 by a parasitic capacitor 175 . Noise may be injected on a victim wire, e.g., the read-select line 120 , by the parasitic capacitor 175 in response to a neighboring wire 170 transitioning between Vcc and ground.

In an embodiment, noise-canceling circuits 102 may be connected between neighboring read-select lines 170 and the virtual ground node 160 of the static inverter 150 to decouple noise injected onto read-select line 120 in response to those neighboring lines 170 transitioning between Vcc and ground.

The noise canceling circuit 102 includes a PMOS transistor 180 with a gate controlled by the Clk 2 signal, and an NMOS transistor 182 with a gate coupled to the neighboring read-select line 170 . An output node 184 between the PMOS transistor 180 and the NMOS transistor 182 is coupled to one side (the “near side”) of a capacitor 186 . The other side (the “far side”) of the capacitor 186 is coupled to the virtual ground node 160 . The capacitor 186 may have a capacitance that is approximately equal (to a first-order) to that of parasitic capacitor 175 .

During the NOR gate's 104 pre-charge, both Clk 2 and the neighboring read-select line 170 are LOW. With PMOS transistor 180 ON and NMOS transistor 182 OFF, the output node 184 is pulled HIGH, charging the near side of the capacitor 186 to Vcc.

During evaluation, Clk 2 is HIGH and the PMOS transistor 180 is OFF, closing the path to Vcc. During that time, if read-select line 120 is not selected, e.g., the signal on read-select line 120 is LOW, the gates of the input transistors 116 , 117 are under-driven by −ΔV supplied by the virtual ground node 160 . If neighboring read-select line 170 transitions HIGH, the rising edge of the transition on read-select line 170 will cause the parasitic capacitor 175 to inject noise onto the victim read-select line 120 , and hence to the gates of the input transistors 116 . This noise will also be injected onto the virtual ground node 160 through the (ON) NMOS transistor 152 of the static inverter 150 .

The rising signal on the neighboring read-select line 170 will also start to turn on NMOS transistor 182 in the noise canceling circuit 102 . As the discharge path to ground opens, the HIGH signal on the output node 184 begins to transition LOW. This falling transition from Vcc to ground on the near side of the capacitor 186 causes the capacitor 186 to inject a signal onto the virtual ground node that is approximately equal in magnitude but opposite in polarity to the noise injected by the parasitic capacitor 175 . Thus, the two signals tend to cancel out, and the noise injected by the transition of the neighboring read-select line 170 is effectively decoupled from the virtual ground node. This active decoupling may improve the performance of the circuit.

If the read-select line 170 does not transition HIGH during evaluation, the near side of capacitor 186 remains floating at Vcc, and the parasitic capacitor 175 will not interfere with the virtual ground node 160 of the read-select line 120 .

The devices in the noise-canceling circuit 102 may be relatively small to the read-select lines and hence will not significantly impact the performance of the circuit. Although there may be a dynamic power overhead associated with the low V t enabler circuit, it has been found that overall performance may be improved compared to circuits that incorporate high V t devices and compared to low V t devices that do not utilize the low V t enabler circuit.

The noise-canceling scheme described above may be utilized for dynamic circuits in noisy environment other than the register file circuit 100 , for example, schedulers and dynamic buses. The noise-canceling scheme may also be used to reduce leakage in high fan-in domino gates other than the dynamic NOR gate 104 illustrated.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.