Inventor
Ram K. Krishnamurthy
Inventor
Portland, OR, US
Overview
Patents· 156 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique24%
G06FElectric digital data processing20%
G11CStatic stores18%
H04LTransmission of digital information, e.g. telegraphic communication11%
G06NComputing arrangements based on specific computational models5%
G01RMeasuring electric variables4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
H04NPictorial communication, e.g. television3%
H03MCoding2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
PatentTitleYear
11,100,385Scalable free-running neuromorphic computer202111,061,646Compute in memory circuits with multi-Vdd arrays and/or analog multipliers202111,062,203Neuromorphic computer with reconfigurable memory mapping for various neural network topologies202111,054,470Double edge triggered Mux-D scan flip-flop202111,048,434Compute in memory circuits with time-to-digital computation202111,016,701Oscillator circuitry to facilitate in-memory computation202111,017,288Spike timing dependent plasticity in neuromorphic hardware202110,877,752Techniques for current-sensing circuit design for compute-in-memory202010,860,682Binary, ternary and bit serial compute-in-memory circuits202010,831,446Digital bit-serial multi-multiply-and-accumulate compute in memory202010,825,509Full-rail digital read compute-in-memory circuit202010,756,736Fused voltage level shifting latch202010,748,603In-memory multiply and accumulate with global charge-sharing202010,713,558Neural network with reconfigurable sparse connectivity and online learning202010,705,967Programmable interface to in-memory cache processor202010,642,922Binary, ternary and bit serial compute-in-memory circuits202010,565,138Memory device with multiple memory arrays to facilitate in-memory computation202010,491,217Low-power clock gate circuit201910,473,718Multibit vectored sequential with scan201910,440,377Motion estimation for video processing201910,418,975Low clock supply voltage interruptible sequential201910,397,157Message management in a social networking environment201910,382,019Time borrowing flip-flop with clock gating scan multiplexer201910,284,368Secure key storage201910,248,906Neuromorphic circuits for storing and generating connectivity information201910,193,536Shared keeper and footer flip-flop201910,176,248Performing a dynamic search of electronically stored records based on a search term format201910,177,765Integrated clock gate circuit with embedded NOR201910,148,426Method and apparatus for efficiently implementing the advanced encryption standard201810,079,911Content analysis based selection of user communities or groups of users201810,050,778Method and apparatus for efficiently implementing the advanced encryption standard20189,985,612Time borrowing flip-flop with clock gating scan multiplexer20189,979,668Combined guaranteed throughput and best effort network-on-chip20189,965,248Threshold filtering of compressed domain data using steering vector20189,961,019Adaptively switched network-on-chip20189,960,753Apparatus and method for low power fully-interruptible latches and master-slave flip-flops20189,859,876'Shared keeper and footer flip-flop'20189,852,540Graphics lighting engine including log and anti-log units20179,843,441'Compact, low power advanced encryption standard circuit'20179,787,571'Link delay based routing apparatus for a network-on-chip'20179,699,096'Priority-based routing'20179,652,425'Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC)'20179,641,160'Common N-well state retention flip-flop'20179,634,866'Architecture and method for hybrid circuit-switched and packet-switched router'20179,544,141'Secure key storage using physically unclonable functions'20179,544,133'On-the-fly key generation for encryption and decryption'20179,503,747'Threshold filtering of compressed domain data using steering vector'20169,397,641'Apparatus and method for low power fully-interruptible latches and master-slave flip-flops'20169,391,617'Hardware-embedded key based on random variations of a stress-hardened inegrated circuit'20169,306,596'Hybrid CAM assisted deflate decompression accelerator'20169,307,409'Apparatus, system and method of protecting domains of a multimode wireless radio transceiver'20169,262,256'Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location'20169,225,521'Apparatus and method for skein hashing'20159,104,474'Variable precision floating point multiply-add circuit'20159,059,715'Voltage level shift with interim-voltage-controlled contention interrupt'20159,035,686'Apparatus and method for low power fully-interruptible latches and master-slave flip-flops'20158,923,510'Method and apparatus for efficiently implementing the advanced encryption standard'20148,855,302'Apparatus and method for Skein hashing'20148,677,275'Illustrating a menu of insights associated with visualizations'20148,577,948'Split path multiply accumulate unit'20138,407,075'Merging calendar entries'20138,284,766'Multi-core processor and method of communicating across a die'20128,265,135'Method and apparatus for video processing'20128,214,414'Combined set bit count and detector logic'20128,078,662'Multiplier product generation based on encoded data from addressable location'20117,913,101'Method and apparatus for treating a signal'20117,900,160'System and method for illustrating a menu of insights associated with visualizations'20117,860,240'Native composite-field AES encryption/decryption accelerator circuit'20107,855,575'Wide voltage range level shifter with symmetrical switching'20107,840,885'Distributed ring control circuits for Viterbi traceback'20107,800,407'Multiple voltage mode pre-charging and selective level shifting'20107,693,926'Modular multiplication acceleration circuit and method for data encryption/decryption'20107,693,925'Multiplicand shifting in a linear systolic array modular multiplier'20107,606,062'Ultra low voltage and minimum operating voltage tolerant register file'20097,603,398'Data converter and a delay threshold comparator'20097,592,835'Co-processor having configurable logic blocks'20097,519,646'Reconfigurable SIMD vector processing system'20097,477,171'Binary-to-BCD conversion'20097,426,127'Full-rail, dual-supply global bitline accelerator CAM circuit'20087,380,099'Apparatus and method for an address generation circuit'20087,379,491'Flop repeater circuit'20087,372,763'Memory with spatially encoded data storage'20087,362,621'Register file with a selectable keeper circuit'20087,352,209'Voltage-level converter'20087,332,937'Dynamic logic with adaptive keeper'20087,325,024'Adder circuit with sense-amplifier multiplexer front-end'20087,275,204'Distributed ring control circuits for Viterbi traceback'20077,272,029'Transition-encoder sense amplifier'20077,250,783'Current mirror multi-channel leakage current monitor circuit and method'20077,209,395'Low leakage and leakage tolerant stack free multi-ported register file'20077,196,546'Low-swing bus driver and receiver'20077,196,548'Single ended current-sensed bus with novel static power free receiver circuit'20077,190,286'Single-stage and multi-stage low power interconnect architectures'20077,188,134'High-performance adder'20077,161,992'Transition encoded dynamic bus circuit'20077,161,826'Low-noise leakage-tolerant register file technique'20077,154,300'Encoder and decoder circuits for dynamic bus'20067,132,849'Method and apparatus for configuring the operation of an integrated circuit'20067,132,856'Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessors'20067,131,055'Fast bit-parallel Viterbi decoder add-compare-select circuit'20067,099,219'Multi read port bit line'20067,057,913'Low-power search line circuit encoding technique for content addressable memories'20067,053,663'Dynamic gate with conditional keeper for soft error rate reduction'20067,016,239'Leakage tolerant register file'20067,002,375'Robust variable keeper strength process-compensated dynamic circuit and method'20067,002,389'Fast static receiver with input transition dependent inversion threshold'20066,992,603'Single-stage and multi-stage low power interconnect architectures'20066,940,313'Dynamic bus repeater with improved noise tolerance'20056,919,737'Voltage-level converter'20056,847,569'Differential current sense amplifier'20056,844,750'Current mirror based multi-channel leakage current monitor circuit and method'20056,838,910'Fast dual-rail dynamic logic style'20056,828,841'Clock receiver circuit for on-die salphasic clocking'20046,791,364'Conditional burn-in keeper for dynamic circuits'20046,781,892'Active leakage control in single-ended full-swing caches'20046,765,414'Low frequency testing, leakage control, and burn-in control for high-performance digital circuits'20046,762,957'Low clock swing latch for dual-supply voltage design'20046,751,141'Differential charge transfer sense amplifier'20046,717,441'Flash II-Domino: a fast dual-rail dynamic logic style'20046,707,708'Static random access memory with symmetric leakage-compensated bit line'20046,693,461'Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation'20046,690,604'Register files and caches with digital sub-threshold leakage current calibration'20046,633,190'Multi-phase clock generation and synchronization'20036,628,557'Leakage-tolerant memory arrangements'20036,628,143'Full-swing source-follower leakage tolerant dynamic logic'20036,617,892'Single ended interconnect systems'20036,618,316'Pseudo-static single-ended cache cell'20036,614,279'Clock receiver circuit for on-die salphasic clocking'20036,614,680'Current leakage reduction for loaded bit-lines in on-chip memory structures'20036,600,340'Noise tolerant wide-fanin domino circuits'20036,597,623'Low power architecture for register files'20036,590,801'Current leakage reduction for loaded bit-lines in on-chip memory structures'20036,573,756'Active noise-canceling scheme for dynamic circuits'20036,571,269'Noise-tolerant digital adder circuit and method'20036,563,357'Level converting latch'20036,549,040'Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates'20036,519,178'Current leakage reduction for loaded bit-lines in on-chip memory structures'20036,510,077'Current leakage reduction for loaded bit-lines in on-chip memory structures'20036,510,092'Robust shadow bitline circuit technique for high-performance register files'20036,493,254'Current leakage reduction for loaded bit-lines in on-chip memory structures'20026,441,648'Double data rate dynamic logic'20026,404,234'Variable virtual ground domino logic with leakage control'20026,404,237'Boosted multiplexer transmission gate'20026,366,122'Tristate driver for integrated circuit in interconnects'20026,366,061'Multiple power supply circuit architecture'20026,366,132'Soft error resistant circuits'20026,353,342'Integrated circuit bus architecture including a full-swing, clocked, common-gate receiver for fast on-chip signal transmission'20026,351,150'Low switching activity dynamic driver for high performance interconnects'20026,346,831'Noise tolerant wide-fanin domino circuits'20026,320,795'Pseudo-static leakage-tolerant register file bit-cell circuit'20016,271,713'Dynamic threshold source follower voltage driver circuit'20016,225,826'Single ended domino compatible dual function generator circuits'20016,204,696'Domino circuits with high performance and high noise immunity'20016,181,166'Tristate driver for integrated circuit interconnects'20016,137,319'Reference-free single ended clocked sense amplifier circuit'20005,986,473'Differential, mixed swing, tristate driver circuit for high performance and low power on-chip interconnects'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2021Patents assigned to INTEL CORP (146)· patent assignee history
1999–2015Based in Hillsboro, OR, US· patent location history
2000–2005Based in Beaverton, OR, US· patent location history
2001–2021Based in Portland, OR, US· patent location history
2006Based in Austin, TX, US· patent location history
2011–2020Patents assigned to KRISHNAMURTHY RAM (11)· patent assignee history
2011–2019Patents assigned to IBM (6)· patent assignee history
2011–2019Based in Westford, MA, US· patent location history
2012–2017Patents assigned to KRISHNAMURTHY RAM K (8)· patent assignee history
2012–2017Patents assigned to MATHEW SANU K (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 146 | 1999–2021 |
| KRISHNAMURTHY RAMself | 11 | 2011–2020 |
| KRISHNAMURTHY RAM Kself | 8 | 2012–2017 |
| MATHEW SANU K | 8 | 2012–2017 |
| IBM | 6 | 2011–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 126 | 2001–2021 |
| Beaverton, OR, US | 21 | 2000–2005 |
| Westford, Massachusetts, US | 6 | 2011–2019 |
| Hillsboro, OR, US | 2 | 1999–2015 |
| Austin, Texas, US | 1 | 2006 |