Inventor

Mark A. Anders

Inventor

Hillsboro, OR, US

Overview

51→

Patents

2001–2021

Patent span

Physics

Primary field (CPC G)

Patents· 51 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing31%

H04LTransmission of digital information, e.g. telegraphic communication18%

H03KPulse technique14%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%

G06NComputing arrangements based on specific computational models6%

G06TImage data processing or generation, in general3%

G09GArrangements or circuits for control of indicating devices using static means to present variable information3%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%

G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy2%

G11CStatic stores2%

PatentTitleYear

11,080,046Instructions and logic to perform floating point and integer operations for machine learning2021 10,944,402Reconfigurable interconnect structure in integrated circuits2021 10,642,614Reconfigurable multi-precision integer dot-product hardware accelerator for machine-learning applications2020 10,599,429Variable format, variable sparsity matrix multiplication instruction2020 10,474,458Instructions and logic to perform floating-point and integer operations for machine learning2019 10,440,377Motion estimation for video processing2019 10,374,793Simon-based hashing for fuse validation2019 10,353,706Instructions and logic to perform floating-point and integer operations for machine learning2019 10,303,735Systems, apparatuses, and methods for K nearest neighbor search2019 9,992,042Pipelined hybrid packet/circuit-switched network-on-chip2018 9,979,668Combined guaranteed throughput and best effort network-on-chip2018 9,961,019Adaptively switched network-on-chip2018 9,940,236Pointer chasing across distributed memory2018 9,923,730'System for multicast and reduction communications on a network-on-chip'2018 9,866,476'Parallel direction decode circuits for network-on-chip'2018 9,843,441'Compact, low power advanced encryption standard circuit'2017 9,787,571'Link delay based routing apparatus for a network-on-chip'2017 9,699,096'Priority-based routing'2017 9,680,459'Edge-aware synchronization of a data signal'2017 9,680,765'Spatially divided circuit-switched channels for a network-on-chip'2017 9,652,425'Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC)'2017 9,634,866'Architecture and method for hybrid circuit-switched and packet-switched router'2017 9,626,334'Systems, apparatuses, and methods for K nearest neighbor search'2017 9,577,634'Scalable crossbar apparatus and method for arranging crossbar circuits'2017 9,473,296'Instruction and logic for a simon block cipher'2016 9,104,474'Variable precision floating point multiply-add circuit'2015 8,284,766'Multi-core processor and method of communicating across a die'2012 8,265,135'Method and apparatus for video processing'2012 7,840,885'Distributed ring control circuits for Viterbi traceback'2010 7,603,398'Data converter and a delay threshold comparator'2009 7,519,646'Reconfigurable SIMD vector processing system'2009 7,509,368'Sparse tree adder circuit'2009 7,380,099'Apparatus and method for an address generation circuit'2008 7,352,209'Voltage-level converter'2008 7,352,059'Low loss interconnect structure for use in microelectronic circuits'2008 7,325,024'Adder circuit with sense-amplifier multiplexer front-end'2008 7,275,204'Distributed ring control circuits for Viterbi traceback'2007 7,272,029'Transition-encoder sense amplifier'2007 7,196,546'Low-swing bus driver and receiver'2007 7,196,548'Single ended current-sensed bus with novel static power free receiver circuit'2007 7,161,992'Transition encoded dynamic bus circuit'2007 7,154,300'Encoder and decoder circuits for dynamic bus'2006 6,940,313'Dynamic bus repeater with improved noise tolerance'2005 6,909,127'Low loss interconnect structure for use in microelectronic circuits'2005 6,828,841'Clock receiver circuit for on-die salphasic clocking'2004 6,628,143'Full-swing source-follower leakage tolerant dynamic logic'2003 6,614,279'Clock receiver circuit for on-die salphasic clocking'2003 6,573,756'Active noise-canceling scheme for dynamic circuits'2003 6,522,186'Hierarchical clock grid for on-die salphasic clocking'2003 6,351,150'Low switching activity dynamic driver for high performance interconnects'2002 6,225,826'Single ended domino compatible dual function generator circuits'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Patents assigned to INTEL CORP (49)· patent assignee history

2001Based in Champaign, IL, US· patent location history

2002–2021Based in Hillsboro, OR, US· patent location history

2012–2017Patents assigned to KAUL HIMANSHU (5)· patent assignee history

2012–2017Patents assigned to ANDERS MARK (3)· patent assignee history

2012–2017Patents assigned to KRISHNAMURTHY RAM (3)· patent assignee history

2016–2017Patents assigned to ANDERS MARK A (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	49	2001–2021
KAUL HIMANSHU	5	2012–2017
ANDERS MARKself	3	2012–2017
KRISHNAMURTHY RAM	3	2012–2017
ANDERS MARK Aself	2	2016–2017

Locations

Location	Patents	Span
Hillsboro, OR, US	50	2002–2021
Champaign, Illinois, US	1	2001