Semiconductor integrated circuit device capable of ensuring reliability of transistor driving high voltage

1. Field of the Invention

The present invention relates to a configuration of a semiconductor integrated circuit device and, more particularly, to a circuit configuration operating at a voltage higher than in other circuit portions in a semiconductor integrated circuit device.

2. Description of the Background Art

In a semiconductor integrated circuit device, for example, in a dynamic random access memory (DRAM) as a semiconductor memory device, generally an internal power supply circuit is mounted, for supplying an internal boosted potential by boosting an externally applied power supply voltage.

More specifically, in a word line potential driving circuit of a DRAM, the above described internally boosted potential is used to make gate potential of an access transistor in a memory cell sufficiently high to prevent voltage drop in the access transistor.

When a sense amplifier band is shared by two memory cell blocks adjacent thereto, a gate circuit for selectively coupling a sense amplifier to a bit line pair in either one of the memory cell blocks is generally formed by an N channel MOS transistor. It is necessary that a signal level controlling such a gate circuit is at a level higher than the “H” level potential which can be generated in the bit line pair, that is, the internally boosted potential described above, in order to prevent the voltage drop in the gate circuit.

At this time, the high voltage is applied to the transistor constituting the gate circuit and the access transistor of the memory cell which is the transistor on the side of receiving the high voltage, only when these are selected.

By contrast, the transistor included in the internal power supply circuit for generating the internally boosted potential is subjected to such a high voltage for a longer period, and such a transistor operates under the severest condition considering the necessity of securing reliability.

One of the causes decreasing reliability of such a transistor operating with high voltage applied thereto is a deterioration mode caused by “hot carriers” generated in a high electric field region near the drain of the transistor.

More specifically, when a transistor is miniaturized while keeping constant the power supply voltage, electric field strength increases near the drain. Therefore, electrons flowing from the source to the drain through the channel obtains high energy from the high electric field near the drain junction, and turn to a so called “hot electrons.” The hot electrons collide and are ionized near a drain end, generating electrons.holes. Though the electrons flow into the drain, part of the electrons are introduced and captured as a gate current in a gate oxide film and causes increase in threshold voltage or decrease in conductance as time passes.

Degradation of transistor characteristics caused by “hot carriers resulting from impact ionization” is said to be more likely in an N channel MOS transistor than a P channel MOS transistor. The reason for this may be the fact that electrons have higher ratio of impact ionization than holes, and that impurity profile of the drain is more steep, and hence electric field near the drain is high.

Accordingly, in a circuit for driving a high voltage such as described above, conventionally, a transistor having an electric field relaxing drain structure, for example, in order to maintain reliability of the N channel MOS transistor, a transistor having an electric field relaxing drain structure, for example, an N channel MOS transistor having an LDD (Lightly Doped Drain) structure has been sometimes used. Alternatively, a circuit configuration has been adopted in which an N channel MOS transistor having a prescribed gate potential applied thereto is interposed between a boosting node and a discharging N channel MOS transistor, so as to relax drain.source voltage.

Recently, in an LSI for image processing, for example, sometimes such a device is manufactured in that a DRAM and a logic circuit are mounted mixed on one chip.

In such a case, generally an MOS insulating film is made thin, for example, insulating film of an MOSFET is made thin (for example, insulating film thickness Tox=2 to 3 nm), in order to improve transistor performance of the logic circuit. Here, the MOS insulating film of the MOSFET in an area where the DRAM is formed is set thicker than in the logic circuit, and the insulating film thickness is Tox=6 to 7.5 nm, for example. Such a structure is referred to as a “Dual-Tox” method, as MOS insulating films of two different thicknesses are used in one LSI.

Here, up to the generation of the DRAM and the logic circuit having the minimum design dimension of 0.20 micron, an n + -polysilicon gate doped with n type impurity to a high concentration has been used as a gate electrode material both in P channel and N channel MOS transistors. Such a structure of the gate electrode material is referred to as “single gate method”.

In the single gate method, the N channel MOS transistor is a so called surface channel type MOS transistor, while the P channel MOS transistor is a buried channel type MOS transistor.

More specifically, in the single gate method, generally, an n type polycrystalline silicon (polysilicon) doped with a large amount of phosphorus (P) is used as the gate electrode material. Even in a polycide gate structure consisting of a stacked structure of a high melting point metal silicide and polycrystalline silicon, what is indirect contact with a gate oxide film is n type polysilicon.

When such gate electrode materials are used as the gate electrode of the N channel MOS transistor, the threshold voltage becomes lower, as there is a large difference in work function between a p type substrate and an n type polysilicon. Therefore, generally, in an N channel MOS transistor, impurities of the same conductivity as the substrate are ion-implanted to the channel region, so as to increase the threshold voltage.

When the n type polysilicon is used as the gate electrode of a P channel MOS transistor, the difference of work function between the n type substrate and the n type polysilicon is small, and therefore the threshold voltage increases in a negative direction. Therefore, when the absolute value of the threshold voltage is to be set at approximately the same value as that of the N channel MOS transistor, it becomes necessary that an impurity of an opposite conductivity to the substrate is ion-implanted to the channel region, so as to make smaller the absolute value of the threshold voltage.

As a result, in the P channel MOS transistor having the n type polysilicon as the gate electrode, a very shallow p-n junction is formed in the channel region, resulting in a buried channel type device. By contrast, the N channel MOS transistor having the n type polysilicon gate becomes a surface channel type device.

In the single gate method, the n type polysilicon is used as the gate electrode both in the N channel and P channel MOS transistors, and the threshold voltages of the N channel and P channel MOS transistors are adjusted to be approximately the same, by ion-implantation of boron to the channel region.

When such a structure is adopted, the position where the potential is the minimum is not at the Si—SiO 2 interface but in the substrate (well) in the P channel MOS transistor, and therefore, a buried channel is formed.

By contrast, from the generation where the circuit design rule attains 0.18 micron or smaller, a so called “dual gate method” comes to be adopted, in which the gate of the P channel MOS transistor is formed by p + -polysilicon gate and the gate of N channel MOS transistor is formed by n + -polysilicon.

In this case, both P and N channel MOS transistors are the surface channel type MOS transistors.

The reason why such an approach is taken is that the buried channel type device such as the conventional P channel MOS transistor is, though advantageous in that mobility increases as the carriers in the buried channel are less susceptible to the influence of surface scattering particular to the interface, disadvantageous in that short channel effect is likely. Therefore, as the gate dimension reduces, there arises the problems of decreased threshold voltage, degradation in subthreshold characteristic and decrease of punch through breakdown voltage. Possible causes of these problems include that the influence of the gate voltage becomes smaller as the channel position becomes further from the Si—SiO 2 interface, and that near the Si—SiO 2 interface, the structure along the direction of the channel is p + -p-p + and there is not the p-n junction, so that the influence of the drain voltage on the channel is increased. Accordingly, it becomes necessary to have the P channel MOS transistor of surface channel type.

In this situation, that is, when a memory circuit such as the DRAM and a logic circuit are formed on one chip and the Dual-Tox method and the dual gate method are employed for the CMOS circuits constituting these circuits, the conventional transistor structure as described above may be insufficient to ensure reliability of the transistor.

An example of a transistor to which the above described high electric field is applied in a DRAM will be described in greater detail.

FIG. 38 is a schematic block diagram illustrating, where a sense amplifier SA has a so called shared amplifier configuration shared by two bit line pairs BL 11 , /BL 11 and BL 21 , /BL 21 in a DRAM, for example, the configurations of a gate circuit for opening/closing the connection between the bit line pairs and the sense amplifier SA and driving circuits DRBI 1 and DRBI 2 generating a signal BLI for controlling the gate potential of the transistor constituting the gate circuit.

Referring to FIG. 38, sense amplifier SA is connected to bit line pair BL 11 , /BL 11 through gate transistors TG 11 and TG 12 , respectively. Sense amplifier SA is connected to bit line pair BL 21 , /BL 21 through gate transistors TG 21 and TG 22 , respectively.

Gate potentials of transistors TG 11 and TG 12 are controlled by the signal BLI (i, 0 ) output from driving circuit DRBI 1 .

Gate potentials of transistors TG 21 and TG 22 are controlled by the signal BLI (i, 1 ) output from driving circuit DRBI 2 .

Driving circuit DRBI 1 includes an inverter INV 11 receiving a block selecting signal BSi, P channel MOS transistors TP 11 and TN 11 connected in series between a boosted potential Vpp and the ground potential GND, and P channel MOS transistors TP 12 and TN 12 connected in series between the boosted potential Vpp and the ground potential GND.

Transistor TP 12 has its gate connected to a connection node of transistors TP 11 and TN 11 , while transistor TP 11 has its gate connected to a connection node of transistors TP 12 and TN 12 .

Transistor TN 11 receives at its gate a signal BSi, and transistor TN 12 receives at its gate an output of inverter INV 11 .

Driving circuit DRBI 1 further includes a P channel MOS transistor TP 13 and an N channel MOS transistor TN 13 connected in series between the boosted potential Vpp and the ground potential GND.

Transistor TP 13 has its gate connected to a connection node of transistors TP 12 and TN 12 , and the potential level at the connection node of transistors TP 13 and TN 13 is provided as the signal BLI (i, 0 ).

Driving circuit DRBI 2 basically has the same configuration as driving circuit DRBI 1 . Now, when a logic and a DRAM are mounted together on one chip, the gate length of MOSFET providing the logic circuit is formed with the minimum design dimension, for example, while a transistor having the gate length longer than the minimum design dimension is used as a transistor to which a particularly high voltage is applied, in the DRAM portion 100 , such as the transistor TP 13 .

FIG. 39 is a timing chart illustrating the operation of the circuit shown in FIG. 38 .

Referring to FIG. 39, assume that the ith block is selected and the block selecting signal BSi is at an active state (“L” level) at time point t 0 . At time T 1 , in response to the signal BSI attaining to an inactive state (“H” level), transistors TN 11 and TN 13 in the driving circuit DRBI 1 are rendered conductive.

In response, the output of inverter INV 1 attains to the “L” level, and transistor TN 12 is turned off. Therefore, transistor TP 12 is rendered conductive, and the gate potential of transistor TP 13 increases to the boosted potential Vpp. Thus, transistor TP 13 attains to the off state, and the signal BLI (i, 0 ) attains to the ground potential GND.

At time T 2 , when the signal BSi attains to the active state (“L” level), transistors TN 11 and TN 13 in driving circuit DRBI 1 are set to the off state in response. As the output level of inverter INV 11 attains to the “H” level, transistor TN 12 is rendered conductive. In response, transistor TP 11 is rendered conductive, and the gate potential of transistor TP 12 attains to the boosted potential Vpp. Thus, transistor TP 12 is turned off. In response, gate potential of transistor TP 13 attains to the ground potential GND, and therefore, transistor TP 13 is rendered conductive and the signal BLI (i, 0 ) attains to the boosted potential Vpp.

The output level of driving circuit DRBI 2 which is not in the selected state, is kept at the “L” level.

In such a configuration, P channel MOS transistors TP 13 and the like make transition between a state where a potential corresponding to the potential difference between the ground potential GND and the boosted potential Vpp is applied between the source and drain (off state) and a state where the potential difference between the source and the drain is almost eliminated (conductive state).

Here, the transistor TP 13 in driving circuit DRBI 1 is required to drive, at one time, a plurality of gate transistors (in FIG. 38, only two gate transistors are shown as representatives) existing in the memory cell block, and therefore, it must have a relatively large driving force. Therefore, the time period from the state where the transistor TP 13 is in the off state with the ground potential GND and the boosted potential Vpp applied between the source and the drain thereof until the potential difference between the source and the drain of transistor TP 13 becomes small is longer than in transistors TP 11 and TP 12 . Therefore, transistors TP 13 and the like are kept in such a state in that channel current flows while a larger source.drain voltage Vds is applied.

In the LSI having the DRAM and the logic circuit mounted together, when the CMOS transistor has the dual gate structure and the Dual-Tox method is employed, there is a possibility that sufficient reliability of the P channel MOS transistor such as the transistor TP 13 that has been considered less susceptible to degradation in reliability caused by hot carriers, cannot be ensured if such a voltage stress is applied.

An object of the present invention is to provide a semiconductor integrated circuit device capable of ensuring, in a circuit that must drive a relatively high voltage, reliability of a transistor pulling up the voltage.

Briefly stated, the present invention provides a semiconductor integrated circuit device including a logic circuit portion, a voltage down converting circuit, a boosting circuit and a memory portion.

The logic circuit portion operates at the ground potential and a first power supply potential.

The voltage down converting circuit generates, from an external power supply potential, a second power supply potential by down-converting the external power supply potential. The boosting circuit generates a boosted potential, from the external power supply potential, by boosting the external power supply potential.

The memory portion operates at least at the ground potential and the internal power supply potential and the boosted potential, and transmits/receives data to and from the logic circuit portion.

The memory portion includes a plurality of memory cells and a driving circuit. The plurality of memory cells are arranged in a matrix of rows and columns. The plurality of memory cells are each capable of storing any of at least two levels corresponding to the ground potential and the second internal power supply potential.

The driving circuit operates upon reception of the boosted potential and, at least in a data reading operation from the memory cell, generates an internal control signal having a level corresponding to the boosted potential, for controlling the reading operation.

The driving circuit has an output node for outputting an internal control signal, and a surface channel type N channel MOS transistor provided between the output node and the boosted potential, for pulling up the potential level of the output node.

According to another aspect, the present invention provides a semiconductor integrated circuit device including a logic circuit portion, a voltage down converting circuit, a boosting circuit and a memory portion.

The logic circuit portion operates at the ground potential and the first power supply potential.

The voltage down converting circuit generates a second power supply potential from an external power supply potential, by down-converting the external power supply potential. The boosted circuit generates a boosted potential from the external power supply potential, by boosting the external power supply potential.

The memory portion operates at least at the ground potential and the second internal power supply potential and the boosted potential, and transmits/receives data to and from the logic circuit portion.

The memory portion includes a plurality of memory cells and a driving circuit.

The plurality of memory cells are arranged in a matrix of rows and columns. The plurality of memory cells are each capable of storing any of at least two levels corresponding to the ground potential and the second internal power supply potential.

The driving circuit operates receiving the boosted potential, and generates, at least in the data reading operation from the memory cell, an internal control signal having a level corresponding to the boosted potential, for controlling the reading operation.

The driving circuit has an output node for outputting the internal control signal, and a buried channel type P channel MOS transistor for pulling up the potential level of the output node.

According to a still further aspect, the present invention provides a semiconductor integrated circuit device including a logic circuit portion, a voltage down converting circuit, a boosting circuit and a memory portion.

The logic circuit portion operates at the ground potential and a first power supply potential.

The voltage down converting circuit generates a second power supply potential from an external power supply potential, by down-converting the external power supply potential. The boosting circuit generates a boosting potential from the external power supply potential, by boosting the external power supply potential.

The memory portion operates at least at the ground potential and the second internal power supply potential and the boosted potential, and transmits/receives data to and from the logic circuit portion.

The memory portion includes a plurality of memory cells and a driving circuit.

The plurality of memory cells are arranged in a matrix of rows and columns. The plurality of memory cells are each capable of storing any of at least two levels corresponding to the ground potential and the second internal power supply potential.

The driving circuit operates upon reception of the boosted potential, and at least in the data reading operation from the memory cell, generates an internal control signal having a level corresponding to the boosted potential, for controlling the reading operation.

The driving circuit has an output node for outputting the internal control signal, and an LDD type P channel MOS transistor provided between the output node and the boosted potential, for pulling up the potential level of the output node.

According to a still further aspect, the present invention provides a semiconductor integrated circuit device including a logic circuit portion, a voltage down converting circuit, a boosting circuit and a memory portion.

The logic circuit portion operates at the ground potential and a first power supply potential.

The voltage down converting circuit generates a second power supply potential from the external power supply potential, by down-converting the external power supply potential. The boosting circuit generates a boosted potential from the external power supply potential, by boosting the external power supply potential.

The memory portion operates at least at the ground potential and the second internal power supply potential and the boosted potential, and transmits/receives data to and from the logic circuit portion.

The memory portion includes a plurality of memory cells, a driving circuit, a sense amplifier band, a word line driving circuit band, a signal line, a plurality of P channel pull up transistors, and a gate circuit.

The plurality of memory cells are each capable of storing any of at least two levels corresponding to the ground potential and the second internal power supply potential, respectively, and arranged in a matrix of rows and columns. The plurality of memory cells are arranged divided into a plurality of memory cell blocks along the column direction.

The driving circuit operates upon reception of the boosted potential, and generates, at least in the data reading operation from the memory cell, an internal control signal having a level corresponding to the boosted potential, for controlling the reading operation.

The sense amplifier band is provided commonly corresponding to every adjacent pair of memory cell blocks among the plurality of memory cell blocks, and arranged along the row direction for amplifying data read out from the memory cells within the selected memory cell block. The word line driving circuit band is provided along the column direction for every prescribed number of memory cell columns.

The signal line transmits the internal control signal. The plurality of P channel pull up transistors are provided at every intersecting area between the word line driving circuit band and the sense amplifier band, and drive the first signal line level to the boosted potential, in response to activation of the internal control signal.

The gate circuit selectively couples the sense amplifier band with a corresponding memory cell block. The gate circuit includes a plurality of N channel MOS transistors controlled by the potential level of the signal line, for opening/closing coupling between the memory cell block and the sense amplifier portion.

Therefore, a main advantage of the present invention is that at least in the period when a high voltage is applied between the source.drain of the pull up transistor, in driving the internal control signal of the boosted potential level, the potential is pulled up by the N channel MOS transistor. Therefore, degradation of reliability caused by “channel hot carriers” can be suppressed.

Another advantage of the present invention is that, in driving the internal control signal of the boosted potential level, the potential is pulled up by a P channel MOS transistor having such a structure that has immunity to “channel hot carriers”, and therefore degradation of reliability caused by “channel hot carriers” can be suppressed.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a schematic block diagram representing a configuration of a semiconductor integrated circuit device 1000 in accordance with a first embodiment of the present invention.

FIG. 2 is a schematic block diagram representing a configuration of a DRAM portion 100 .

FIG. 3 shows a configuration of an inverter INV 1 operating at a boosted potential Vpp.

FIG. 4 shows an input/output waveform of the inverter shown in FIG. 3 .

FIG. 5 shows a fan out dependency of the input/output waveform of the inverter shown in FIG. 3 .

FIG. 6A is a schematic diagram representing the conventionally known degradation of reliability caused by hot carriers, and FIG. 6B schematically represents the degradation of reliability caused by “channel hot carriers.”

FIG. 7 is a schematic diagram representing a configuration of a memory cell array 102 .

FIG. 8 is a circuit diagram representing extracted configurations of memory cell block MCB 2 and sense amplifier bands SAB 1 and SAB 2 .

FIG. 9 is a schematic block diagram representing the configurations of driving circuits DR 1 and DR 2 .

FIG. 10 is a timing chart representing the operation of the circuits shown in FIG. 9 .

FIG. 11 is a schematic block diagram representing configurations of driving circuits DR 21 and DR 22 .

FIG. 12 is a timing chart representing the operation of the circuits shown in FIG. 11 .

FIG. 13 is a schematic block diagram representing configurations of driving circuits DR 31 and DR 32 .

FIG. 14 is a timing chart representing the operation of circuit DR 31 .

FIG. 15 is a schematic block diagram representing configurations of driving circuits DR 41 and DR 42 .

FIG. 16 is a timing chart representing the operations of the circuit shown in FIG. 15 .

FIG. 17 shows a cross sectional structure of a LDD P channel MOS transistor corresponding to transistor TP 15 of a first modification of a fourth embodiment.

FIGS. 18 to 22 are cross sectional views showing the first to fifth steps of manufacturing a P channel MOS transistor and an N channel MOS transistor.

FIGS. 23 to 28 are cross sectional views showing the first to sixth steps of manufacturing a P channel MOS transistor and an N channel MOS transistor.

FIG. 29 is a schematic block diagram representing a configuration for selecting a subword line and a configuration for equalizing bit line potentials.

FIG. 30 is a circuit diagram representing a configuration of a bit line equalize circuit BECK.

FIG. 31 is a circuit diagram representing a configuration of a sense amplifier SA 11 shown in FIG. 29 .

FIG. 32 is a schematic block diagram representing a configuration of an SD signal generating circuit 140 shown in FIG. 29 .

FIG. 33 is a circuit diagram representing a configuration of a driving circuit DR 51 in signal converting circuits 1420 . 1 to 142 . 4 in accordance with a first modification of a fifth embodiment.

FIG. 34 is a circuit diagram representing a configuration of a subword driver SWD′ of a second modification of the fifth embodiment.

FIG. 35 is a circuit diagram representing a configuration of a data output buffer BOB in a data I/O circuit portion 300 shown in FIG. 1 .

FIG. 36 is a schematic diagram representing another exemplary configuration of memory cell array 102 shown in FIG. 1 .

FIG. 37 is a circuit diagram showing extracted configurations of memory cell block MCB 2 and sense amplifier bands SAB 1 and SAB 2 shown in FIG. 36 .

FIG. 38 is a schematic block diagram illustrating the configurations of driving circuits DRBI 1 and DRBI 2 for generating a signal BLI.

FIG. 39 is a timing chart illustrating the operation of the circuit shown in FIG. 38 .

[First Embodiment]

FIG. 1 is a schematic block diagram representing the configuration of the semiconductor integrated circuit device 1000 in accordance with the first embodiment of the present invention.

Referring to FIG. 1, semiconductor integrated circuit device 1000 includes a power supply terminal 10 for receiving an external power supply potential Ext.Vcc 1 of a relatively low voltage (for example, 1.5V), and a second power supply terminal 112 for receiving an external power supply potential Ext.Vcc 2 higher than the external power supply potential Ext.Vcc 1 . Here, it is assumed that external power supply potential Ext.Vcc 2 is, for example, 3.3V.

Semiconductor integrated circuit device 1000 further includes a DRAM portion 100 operating upon reception of the ground potential GND, external power supply potential Ext.Vcc 1 and external power supply potential Ext.Vcc 2 , a logic circuit portion 200 operating upon reception of the ground potential GND and external power supply potential Ext.Vcc 1 , and a data I/O circuit portion 300 operating upon reception of the ground potential GND and external power supply potential Ext.Vcc 2 , for transmitting/receiving data to and from the logic circuit portion 200 and data input/output terminal 14 .

DRAM portion 100 includes: a memory array portion 102 including memory cells for holding data arranged in a matrix of rows and columns; a peripheral circuit portion 104 operating upon reception of external power supply potential Ext.Vcc 1 , for controlling data input/output operation to and from the memory cell array portion 102 ; an internal voltage down converting circuit 106 receiving and down-converting the external power supply potential Ext.Vcc 2 to generate a down-converted potential (for example, 1.8V); and a Vpp generating circuit 108 receiving an output of internal voltage down converting circuit 106 and generating a boosted potential (for example, 3.5V).

It is assumed that the minimum design rule of the DRAM portion 100 , logic circuit portion 200 and the like shown in FIG. 1 is at most 180 nm (0.18 micron). Further, it is assumed that the transistors constituting semiconductor integrated circuit device 1000 are in accordance with “dual gate method” and “Dual-Tox method”, except for the transistors for driving the boosted potential, as will be described later.

FIG. 2 is a schematic block diagram representing the configuration of DRAM portion 100 shown in FIG. 1 .

The DRAM portion 100 includes: a control signal input buffer 100 receiving control signals from logic portion 200 , for example, a row address strobe signals /RAS, a column address strobe signal /CAS and a write enable signal /WE; an address buffer 112 for receiving an address signal applied for designating a memory cell to be accessed from logic portion 200 ; and a data buffer 114 for transmitting/receiving data to and from the logic portion 200 . Here, data buffer 114 receives and operates with the output of internal voltage down converting circuit 106 .

The DRAM portion 100 further includes: a control circuit 120 receiving a control signal from control signal input buffer 110 for controlling an operation of the DRAM portion 100 ; a row predecoder 122 controlled by control circuit 120 , receiving a row address signal from address buffer 112 for generating a predecode signal; a row decoder (XD) 124 receiving an output from row predecoder 122 for selecting any of the rows; a column predecoder 130 controlled by control signal 120 , receiving a column address signal from address buffer 112 for generating a predecode signal; a column decoder 132 for selecting a corresponding column (bit line pair) of the memory cell block based on the column predecode signal from column predecoder 130 ; a sense amplifier SA provided corresponding to each bit line pair, for amplifying data stored in the selected memory cell; and an I/O circuit for selectively transmitting data from the bit line pair selected by the column decoder 100 to data buffer 114 . In FIG. 2, column decoder (YD) 132 and sense amplifier and I/O circuit 134 are represented collectively by one block for convenience. The memory cell in the memory cell array 102 designated by row decoder 124 and column decoder 134 communicates data with logic circuit portion 200 through sense amplifier+I/O circuit 132 and input/output buffer 114 .

As shown in FIG. 2, memory array 102 is divided into N memory cell blocks MCB 1 to MCBN.

Internal voltage down converting circuit 106 generates an internal power supply potential (for example, 1.8V) from external power supply potential Ext.Vcc 2 (for example, 3.3V), and supplies the generated potential to sense amplifier SA and data buffer 114 . Vpp generating circuit 108 generates the boosted potential Vpp from internal power supply potential and, as will be discussed later, supplies the generated potential to the word line driving circuitry and BLI driving circuitry.

The configuration of the DRAM portion 100 shown in FIG. 2 is only a representative example, and the present invention is generally applicable even when other configuration of the dynamic semiconductor memory device is used for the DRAM portion. For example, the manner of division of the memory cell array is not limited to the example of FIG. 2 .

FIG. 3 shows a configuration of inverter INV 1 operating at the boosted potential Vpp used, for example, in row decoder 124 shown in FIG. 2, and FIG. 4 shows an input/output waveform of such an inverter.

Inverter INV 1 includes a P channel MOS transistor TIP 1 and an N channel MOS transistor TIN 1 connected in series between the boosted potential Vpp and the ground potential GND.

Referring to FIGS. 3 and 4, when the input signal IN starts to change from “H” level to “L” level at time t 1 , the level of the output signal OUT also starts to change from the “L” level to “H” level in response. At this time, for the inverter portion operating at the amplitude of boosted potential Vpp, a thick oxide film (Tox=6 to 7.5 nm) in accordance with the Dual-Tox method is typically used. The circuit including such a transistor that has the thick oxide film suffers from the problem of “channel hot carrier” reliability, as will be discussed below.

The channel hot carrier reliability refers to the variation in the threshold value or the variation in source/drain current Ids caused by the hot carriers generated in the channel of a MOS transistor.

Degradation in reliability caused by the channel hot carriers is strongly dependent on the drain-gate voltage (the phenomenon is more noticeable when the voltage increases). Therefore, in the graph shown in FIG. 4, degradation in reliability is most significant under the bias condition when, at the start of turning on the P channel MOS transistor TIP 1 , the gate potential begins to change while the drain voltage is still maintained at a large value. More specifically, degradation is most significant in the period of time point t 1 to time t 1 +Δt in FIG. 4 .

Such a phenomenon is the most significant at a circuit portion where the signal amplitude is large (for example, Vpp amplitude) and it is necessary to drive a large load capacitance, that is, the most significant where the fan out is large.

Further, the phenomenon is more noticeable in a P channel MOS transistor than in an N channel MOS transistor and further, more noticeable in a surface channel type transistor than the buried channel type transistor.

FIG. 5 shows a fan out dependency of the input/output waveform of the inverter shown in FIG. 3 .

More specifically, degradation by the channel hot carriers is more significant in a circuit in which transistor fan out is large and the timing necessary for the transition of the output potential level from “L” to “H” is longer.

More specifically, when the fan out is small, the time change of the output signal with respect to the change of an input signal IN is relatively steep as represented by the curve Con.S in FIG. 5, and therefore, the time period in which the gate potential of P channel MOS transistor has changed while the drain voltage is maintained at a large value is, for example, from time point t 1 to t 1 +Δt 1 . By contrast, when the fan out is large, the time change of the output signal with respect to the change in the input signal IN is relatively moderate as represented by the curve Con.L in FIG. 5 . Therefore, the time period in which the gate potential of P channel MOS transistor has changed while the drain voltage is maintained at a large value is, for example, from t 1 to 1+Δt 2 . Therefore, it is the case that when the fan out is large, the P channel MOS transistor is exposed longer to the degradation caused by “channel hot carriers”.

FIGS. 6A and 6B are illustrations schematically representing the relation between degradation in reliability caused by hot carriers as conventionally known, and the degradation of reliability caused by “channel hot carriers.”

As can be seen from FIG. 6A, degradation in reliability of the transistor caused by the general hot carriers occurs due to the generation of electron.hole pairs by impact ionization, near the drain end having high electric field intensity.

By contrast, degradation in reliability caused by “channel hot carriers” occurs significantly when the transistor starts to change from the off to on state, that is, in a state where the source/drain voltage is large and the channel current starts to flow as shown in FIG. 6 B and described above.

FIG. 7 is a schematic diagram representing a configuration of memory cell array 102 shown in FIG. 1 . Referring to FIG. 7, the memory cell array is divided into N memory cell blocks MCB 1 to MCBN, and sense amplifier bands SAB 0 to SABN are shared by adjacent memory cell blocks. At this time, as will be described later, a plurality of bit line pairs in memory cell block MCB 2 are so arranged as to be coupled to sense amplifiers in sense amplifier band SAB 1 or sense amplifier band SAB 2 , alternately.

FIG. 8 is a circuit diagram extracting the configurations of memory cell block MCB 2 and sense amplifier bands SAB and SAB 2 shown in FIG. 7 .

FIG. 8 extracts and shows bit line pairs BL 21 , /BL 21 , BL 22 , /BL 22 and BL 23 , /BL 23 , of memory cell block MCB 2 .

The pair of bit lines BL 21 and /BL 21 can be electrically coupled to sense amplifier SA in sense amplifier band SAB 1 through N channel MOS transistors TG 211 and TG 212 , respectively. The pair of bit lines BL 22 and /BL 22 next to the pair of bit lines BL 21 and /BL 21 can be electrically coupled to sense amplifier SA 21 in sense amplifier band SAB 2 through N channel MOS transistors TG 221 and TG 222 , respectively. Further, the pair of bit lines BL 23 and /BL 23 next to the pair of bit lines BL 22 and /BL 22 can be electrically coupled to sense amplifier SA 12 in sense amplifier band SAB 1 through N channel MOS transistors TG 231 and TG 232 , respectively.

Gate potentials of transistors TG 211 and TG 212 , TG 221 and TG 222 as well as TG 231 and TG 232 are driven by the signal BLI ( 2 , 0 ).

FIG. 9 is a schematic block diagram representing the configurations of driving circuits DR 1 and DR 2 for generating the signals BLI (i, 0 ) and BLI (i, 1 ) (i: natural number) shown in FIG. 8 .

Referring to FIG. 9, driving circuit DR 1 includes an inverter INV 11 receiving a block selecting signal BSi, P channel MOS transistors TP 11 and TN 11 connected in series between boosted potential Vpp and the ground potential GND, and P channel MOS transistors TP 12 and TN 12 connected in series between the boosted potential Vpp and the ground potential GND.

Transistor TP 12 has its gate connected to a connection node n 11 of transistors TP 11 and TN 11 , and transistor TP 11 has its gate connected to a connection node n 12 of transistors TP 12 and TN 12 . Transistor TN 11 receives at its gate the signal BSi, and transistor TN 12 receives at its gate an output of inverter INV 11 .

Driving circuit DR 1 further includes N channel MOS transistors TN 14 and TN 13 connected in series between the boosted potential Vpp and the ground potential GND.

Transistor TN 14 has its gate connected to the connection node n 11 of transistors TP 11 and TN 11 , and a potential level at the connection node of transistors TN 14 and TN 13 is output as the signal BLI (i, 0 ).

Driving circuit DR 2 basically has the same structure as driving circuit DR 1 .

FIG. 10 is a timing chart representing the operation of the circuit shown in FIG. 9 . In the following, it is assumed that the transistor TN 14 has a threshold voltage of Vtn.

Referring to FIG. 10, it is assumed that at time T 0 , ith block is selected and the block selecting signal BSi is at the active state (“L” level).

At time T 1 , in response to the signal BSi attaining to the inactive state (“H” level), transistors TN 11 and TN 13 in driving circuit DR 1 are rendered conductive. In response, potential levels of nodes n 11 and n 12 decrease toward the ground potential.

The output of inverter INV 11 attains to the “L” level, and transistor TN 12 is turned off. Transistor TP 12 is rendered conductive as the potential level at node n 11 lowers, and the potential at node n 12 increases to the boosted potential Vpp. Conversely, the potential level of node n 11 decreases, and therefore transistor TN 14 is turned off. Thus, signal BLI (i, 0 ) attains to the ground potential GND.

At time T 2 , when the signal BSi again attains to the active state (“L” level), transistors TN 11 and TN 13 in driving circuit DR 1 are turned off in response. As the output level of inverter INV 11 attains to “H”, transistor TN 12 is rendered conductive. In response, the potential level at node n 12 decreases toward the ground potential GND. Transistor TP 11 is rendered conductive and the gate potential of transistor TP 12 attains to the boosted potential Vpp, and therefore transistor TP 12 is turned off. On the other hand, in response to the potential level at node n 11 attaining to the boosted potential Vpp, the gate potential of transistor TN 14 also attains to the boosted potential Vpp, and therefore, transistor TN 14 is rendered conductive and the signal BLI (i, 0 ) attains to the boosted potential (Vpp−Vtn).

The output level of driving circuit DR 2 which is not in the selected state is kept at the “L” level.

In such a structure, what drives the potential of node n 13 providing the signal BLI (i, 0 ) to the high potential (Vpp−Vtn) is the N channel MOS transistor TN 14 . Therefore, degradation in characteristic by “channel hot carriers” in this transistor can be suppressed.

Here, transistor TN 14 in driving circuit DR 1 must drive, at one time, a plurality of gate transistors in the memory cell block (in FIG. 8, only the transistors TG 211 to TG 233 are shown as representatives), and therefore, the transistor must have a relatively large driving force.

The time period from a state where transistor TN 14 is off and the ground potential and the booster potential Vpp are applied between the source and the drain thereof until a state where the potential difference between the source and the drain of transistor TN 14 decreases is longer than in transistor TP 11 or TP 12 . By the fact that transistor TN 14 is an N channel MOS transistor, however, degradation in reliability caused by “channel hot carriers” can be suppressed.

[Second Embodiment]

FIG. 11 is a schematic block diagram representing configurations of driving circuits DR 21 and DR 22 for generating the signals BLI (i, 0 ) and BLI (i, 1 ) (i; natural number) in accordance with the second embodiment of the present invention.

The configuration of driving circuit DR 21 differs from the driving circuit DR 1 of the first embodiment shown in FIG. 9 in that a P channel MOS transistor TP 13 is provided between the boosted potential Vpp and the node n 13 providing the signal BLI (i, 0 ). Transistor TP 13 has its gate connected to node n 12 .

Therefore, in driving circuit DR 21 , the signal BLI (i, 0 ) is driven from the ground potential GND to the boosted potential Vpp by transistor TP 13 .

Driving circuit DR 22 basically has the same configuration as driving circuit DR 21 .

FIG. 12 is a timing chart representing the operation of the circuit shown in FIG. 11 .

The operation is the same as that of the driving circuit DR 1 in accordance with the first embodiment shown in FIG. 9 except that when the signal BSi is at the active state (“L” level), transistors TP 13 and TN 14 are both rendered conductive, so that the signal BLI (i, 0 ) increases to the boosted potential Vpp. Therefore, description thereof is not repeated.

By adopting the structure shown in FIG. 11, it becomes possible to render conductive the gate transistors TG 211 and TG 212 sufficiently to eliminate the influence of voltage drop, without the necessity of boosting the boosted level Vpp to such a high level as in the first embodiment.

Further, when the potential of node n 13 is to be increased, both N channel MOS transistor TN 14 and P channel MOS transistor TP 13 are used for driving. Therefore, degradation in driveability of P channel MOS transistor TP 13 caused by “channel hot carriers” can be suppressed.

[Third Embodiment]

FIG. 13 is a schematic block diagram representing the configurations of driving circuits DR 31 and DR 32 for generating the signals BLI (i, 0 ) and BLI (i, 1 ) (i: natural number) in accordance with the third embodiment of the present invention.

The configuration of driving circuit DR 31 differs from that of the driving circuit DR 21 in accordance with the second embodiment shown in FIG. 1 in the following points.

Driving circuit DR 31 includes a delay circuit DL 1 receiving as an input the potential level of node n 11 and including an even-numbered stages (in FIG. 13, 4 stages) of inverters connected in series with each other, and an NAND gate NAG 1 having input nodes connected to an output node of delay circuit DL 1 and node n 11 . In driving circuit DR 31 , the gate of P channel MOS transistor TP 13 is connected not to the node n 12 but to an output node of NAND circuit NAG 1 . Here, the inverters constituting the delay circuit DL 1 and NAND circuit NAG 1 all operate receiving the ground potential GND and the boosted potential Vpp. Here, the signal delay time in delay circuit DL 1 is represented as TD.

Therefore, in the driving circuit DR 31 , in response to the potential level at node n 11 reaching the boosted potential Vpp, first, N channel MOS transistor TN 14 is rendered conductive to start raising the potential level of node n 13 and, after the lapse of the delay time ΔTD, P channel MOS transistor TP 13 is rendered conductive and further increases, together with transistor TN 14 , the potential level of node n 13 .

Driving circuit DR 32 basically has the same configuration as driving circuit DR 31 .

FIG. 14 is a timing chart representing the operation of the circuit DR 31 shown in FIG. 13 .

Referring to FIG. 14, it is assumed that at time T 0 , the ith block is selected and the block selecting signal BSI is at the active state (“L” level). Therefore, at time T 0 , the potential levels at the input nodes of NAND circuit NAG 1 are both at the “H” level, and therefore the output of NAND circuit NAG 1 is at the “L” level and transistor TP 13 is conductive.

At time T 1 , in response to the signal BSi attaining to the inactive state (“H” level), transistors TN 11 and TN 13 in driving circuit DR 31 are rendered conductive. In response, potential levels at nodes n 11 and n 12 decrease to the ground potential.

On the other hand, the output of inverter INV 11 attains to the “L” level, and transistor TN 12 is turned off. Transistor TP 12 is rendered conductive as the potential level of node n 11 decreases, and the potential of node n 12 increases to the boosted potential Vpp. Conversely, as the potential level of node n 11 decreases, the potential level of one input node of NAND circuit NAG 1 attains to “L”, the output level of NAND circuit NAG 1 attains to “H” in response, and transistor TP 13 is turned off. Further, as the potential level of node n 11 decreases, transistor TN 14 is turned off and the signal BSi attains to the “H”, whereby transistor TN 13 is rendered conductive. Thus, the signal BLI (i, 0 ) attains to the ground potential GND.

At time T 2 , when the signal BSi again attains to the active state (“L” level), transistors TN 11 and TN 13 in driving circuit DR 31 are turned off in response. As the output level of inverter INV 11 attains to the “H” level, transistor TN 12 is rendered conductive. In response, the potential level of node n 12 decreases toward the ground potential GND. Transistor TP 11 is rendered conductive and the gate potential of transistor TP 12 attains to the boosted potential Vpp. Therefore, transistor TP 12 is turned off. On the other hand, as the potential level of node n 11 attains to the boosted potential Vpp, the gate potential of transistor TN 14 also attains to the boosted potential Vpp, so that transistor TN 14 is rendered conductive and the signal BLI (i, 0 ) increases to a boosted potential (Vpp−Vtn). At this time, the potential level of one input node of NAND circuit NAG 1 also attains to the boosted potential Vpp in response to the increase of the potential level of node n 11 . The other input node of NAND circuit NAG 1 , that is, the input node connected to the output node of delay circuit DL, is kept at the potential level of “L”. Therefore, the output level of NAND circuit NAG 1 is at the “H” level (potential Vpp), and transistor TP 13 is kept off.

At time T 3 after the delay time TD from the time point T 2 , the output level of NAND circuit NAG 1 attains to the “L” level (potential GND), and transistor TP 13 is rendered conductive. In response, the signal BLI (i, 0 ) increases, and attains to the boosted potential Vpp at time T 4 .

The output level of driving circuit DR 32 that is not in the selected state is kept at the “L” level.

In this configuration, what drives the potential of node n 13 providing the signal BLI (i, 0 ) to the potential (Vpp−Vtn) is the N channel MOS transistor TN 14 , and further, P channel MOS transistor drives the potential of node n 13 providing the signal BLI (i, 0 ) from the potential (Vpp−Vtn) to the boosted potential Vpp. Therefore, degradation in characteristic caused by “channel hot carriers” in this transistor can be suppressed.

[Fourth Embodiment]

FIG. 15 is a schematic block diagram representing the configurations of driving circuits DR 41 and DR 42 for generating the signals BLI (i, 0 ) and BLI (i, 1 ) (i: natural number) in accordance with the fourth embodiment of the present invention.

The configuration of driving circuit DR 41 differs from that of driving circuit DR 1 in accordance with the first embodiment shown in FIG. 9 in that a buried channel type P channel MOS transistor TP 15 is provided between the boosted potential Vpp and the node n 13 providing the signal BLI (i, 0 ). The transistor TP 15 has its gate connected to node n 12 .

Therefore, in driving circuit DR 41 , the signal BLI (i, 0 ) is driven from the ground potential GND to the boosted potential Vpp by transistor TP 13 .

In driving circuit DR 41 , transistors TP 11 and TP 12 are surface channel type P channel MOS transistors, and, in order to provide the transistor TP 15 which is a buried channel type P channel MOS transistor, an impurity is ion-implanted to attain a desired threshold voltage to the channel regions of respective transistors, the gate electrodes of transistors TP 11 and TP 12 are formed by p + -polysilicon, and the gate electrode of transistor TP 15 is formed by n + -polysilicon.

Driving circuit DR 22 basically has the same configuration as driving circuit DR 21 .

FIG. 16 is a timing chart representing the operation of the circuit shown in FIG. 15 .

The operation is the same as that of driving circuit DR 1 in accordance with the first embodiment shown in FIGS. 9 and 10 except that transistor TP 15 is rendered conductive when the signal BSi is at the active state (“L” level), so that the signal BLI (i, 0 ) increases to the boosted potential Vpp, and therefore, description thereof is not repeated.

By the configuration shown in FIG. 15, it becomes possible to render gate transistors TG 211 , TG 212 and the like sufficiently conductive to eliminate the influence of the voltage drop, without the necessity to boost the boosted level Vpp to such a high level as in the first embodiment.

Further, in order to increase the potential of node n 13 , buried P channel MOS transistor TP 15 is used for driving, and therefore, degradation in reliability of P channel MOS transistor TP 15 caused by the “channel hot carriers” can be suppressed.

[First Modification of the Fourth Embodiment]

In the fourth embodiment, transistor TP 15 for driving the potential level of boosted node n 13 in driving circuit DR 41 and the like is a buried channel type MOS transistor.

In order to suppress degradation in reliability of transistor TP 15 caused by the “channel hot carrier”, it is possible to form transistor TP 15 as a P channel MOS transistor having the so called LDD structure.

FIG. 17 is a cross section showing the P channel MOS transistor having the LDD structure, corresponding to the transistor TP 15 in accordance with the first modification of the fourth embodiment.

On an N well 502 formed at a main surface of p type Si substrate 500 , a gate oxide film 504 is formed, and a gate electrode 510 is further formed, and processed to a prescribed shape.

Here, as described above, a thick oxide film (Tox=6 to 7.5 nm) is used as the gate oxide film 504 of transistor TP 15 in accordance with the Dual-Tox method. It is assumed that gate electrode 510 is of p + -polysilicon. Therefore, transistor TP is a surface channel type MOS transistor.

On the surface side of N well 502 adjacent to gate electrode 510 , p − regions 520 , which are low concentration p type regions formed by ion implantation using gate electrode 510 itself as a mask, are provided. Further, on the surface side of N well 502 , p + regions 520 , which are high concentration p type regions formed by ion implantation using sidewalls 512 of SiO 2 film as a mask, are provided.

As the ion implantation to form p − region 520 , boron (B) or BF 2 is introduced, with the amount of implantation being up to about 10 14 /cm 2 .

FIGS. 18 to 22 are cross sections showing the first to fifth steps of manufacturing P channel and N channel MOS transistors including such a transistor TP 15 .

Referring to FIG. 18, on a main surface of the p type Si substrate 500 , a P well 402 and N wells 502 and 602 are formed. Here, N well 502 is the well in which transistor TP 15 is formed, for example, as described above. Further, it is assumed that transistor TP 12 is formed in N well 602 and transistor TN 12 is formed in P well 402 , for example. The transistors are separated from each other by element isolating regions 540 .

On N wells 502 and 602 , gate electrodes 510 and 610 are formed by p + -polysilicon, respectively. On P well 402 , a gate 410 is formed by n + -polysilicon.

First, using a photoresist 700 and gate 410 as masks, n − regions 420 are formed by phosphorus ion implantation.

Thereafter, referring to FIG. 19, using a photoresist 702 and gate electrodes 510 and 610 as masks, BF 2 ions are implanted to form p − regions 520 and 620 .

Referring to FIG. 20, by depositing an SiO 2 film by the CVD method, sidewalls 412 , 512 and 612 are formed for gates 410 , 510 and 610 , respectively, by anisotropic etching.

Referring to FIG. 21, using a photoresist mask 710 , gate electrodes 510 and 610 as well as sidewalls 512 and 612 as masks, BF 2 ions are implanted to form p + regions 522 and 622 .

Referring to FIG. 22, using a photoresist mask 712 , gate electrode 410 and sidewall 412 as mask, arsenic (As) ion is implanted to form n + region 422 .

In this manner, N channel and P channel MOS transistors are all formed with LDD structure, and therefore, it becomes possible to suppress degradation in reliability of transistor TP 15 that boost node n 13 , caused by the “channel hot carriers.”

[Second Modification of the Fourth Embodiment]

In the first modification of the fourth embodiment, P channel MOS transistors are all adapted to have the LDD structure.

It is noted, however, in the transistor TP 15 or the like directly driving the boosted node n 13 , it is preferable to have relatively low impurity concentration of p − region 520 of the LDD structure in order to sufficiently suppress degradation in reliability caused by “channel hot carriers”, whereas in other P channel MOS transistors, preferably, the impurity concentration of p − region 620 should be higher than that of p − region 520 , in view of transistor characteristics.

In the second modification of the fourth embodiment, the impurity concentration of the p − region of transistor TP 15 or the like driving the boosted node n 13 is made lower than the concentration of the p − region of other P channel MOS transistors.

More specifically, in order to form the p − region 520 of transistor TP 15 or the like, boron (B) or BF 2 is ion-implanted with the amount of up to about 10 12 /cm 2 , and to form the p − region 620 of other P channel MOS transistors including TP 12 , ion implantation amount is up to about 10 14 /cm 2 .

FIGS. 23 to 28 are cross sections showing the first to sixth steps of manufacturing the P channel and N channel MOS transistors including transistor TP 15 .

Different from the first modification of the fourth embodiment shown in FIGS. 18 to 22 , referring to FIG. 23, the n − region 420 is formed by phosphorus ion implantation using photoresist 700 and gate 410 , and thereafter, the step of forming p − regions 520 and 620 is divided into two steps, that is, the step of performing BF 2 ion implantation to form p − region 620 using photoresist 702 and gate electrode 610 as mask as shown in FIG. 24, and the step of performing BF 2 ion implantation to form p − region 520 using photoresist 704 and gate electrode 510 as mask, as shown in FIG. 25 .

The following steps shown in FIGS. 26 to 28 are the same as the step shown in FIGS. 20 to 22 . Therefore, corresponding portions are denoted by the same reference characters, and description thereof will not be repeated.

By the above described structure also, it is possible to suppress degradation in reliability of transistor TP 15 boosting node n 13 caused by “channel hot carriers.”

Referring to FIG. 24, it is possible to form transistor TP 15 or the like for boosting node n 13 only to have the LDD structure, by sufficiently increasing concentration of ion implantation using photoresist 702 and gate electrode 610 as masks, to be comparable to the concentration of p + region 522 .

[Fifth Embodiment]

FIG. 29 is a schematic block diagram representing a configuration for selecting a sub word line in the memory cell block MCB 2 and sense amplifier bands SAB 1 and SAB 2 , and a configuration for equalizing the bit line potentials, shown in FIG. 8 .

In FIG. 29 also, the bit line pairs BL 21 , /BL 21 , BL 22 , /BL 22 and BL 23 , /BL 23 of memory cell block MCB 2 are extracted and shown as representatives.

A bit line equalizing circuit BECK is provided for each of the bit line pairs BL 21 and /BL 21 , BL 22 and /BL 22 and BL 23 and /BL 23 . The bit line equalizing circuit BECK is activated by a bit line equalizing signal BLEQ. The bit line equalizing signal BLEQ is generated by a control signal generating circuit 200 outputting an internal control signal under the control of control circuit 120 . Control signal generating circuit 200 also generates driving signals SN and SP for sense amplifiers SA 11 , SA 12 , SA 21 and the like.

Control signal generating circuit 200 includes inverters 202 and 204 outputting the bit line equalizing signals BLEQ, and inverters 212 and 214 generating driving signals SN and SP. The P channel MOS transistors constituting inverters 202 , 204 , 212 and 214 are buried channel type P channel MOS transistors, as in the fourth embodiment.

Further, memory cells MC respectively connected to bit line pairs BL 21 and /BL 21 , BL 22 and /BL 22 are selected by a subword line SWL. The subword line SWL is set to an active potential (potential Vpp) by a subword driver SWD that operates in response to the potential of a main word line MWL selected by a main row decoder 124 and the potentials of subdecoder lines SD 1 , /SD 1 to SD 4 , /SD 4 driven by a subdecode signal generating circuit (hereinafter referred to as SD signal generating circuit) 140 .

In FIG. 29, among the plurality of subword drivers, the subword driver SWD driven by subdecode lines SD 1 , /SD 1 is extracted as an example.

Subword driver SWD includes a P channel MOS transistor TSP 11 and an N channel MOS transistor TSN 11 connected in series between subdecode line SB 1 the ground potential GND, and an N channel MOS transistor TSN 12 provided between the ground potential GND and a connection node ns 1 between transistors TSP 11 and TSN 11 .

Transistors TSP 11 and TSN 11 have their gates coupled to main word line MWL, and transistor TSN 12 has its gate connected to subdecode line /SD 1 .

FIG. 30 is a schematic diagram representing the configuration of the bit line equalizing circuit BECK shown in FIG. 29 .

Bit line equalizing circuit BECK includes: an N channel MOS transistor TBN 11 provided between bit line equalizing potential VBL and bit line BL 1 ; an N channel MOS transistor TBN 12 provided between bit line equalizing potential VBL and bit line /BL 21 ; and an N channel MOS transistor TBN 21 provided between bit lines BL 21 and /BL 21 . The bit line equalizing potential VBL is, when the “H” level supplied to the memory cell is int.Vcc, int.Vcc/2. The gates of transistors TBN 11 , TBN 21 and TBN 21 receive the bit line equalizing signal BLEQ.

FIG. 31 is a schematic diagram representing the configuration of sense amplifier SA 11 shown in FIG. 29 .

Sense amplifier SA includes an N channel MOS transistor TAN 11 provided between an SN signal line transmitting the driving signal SN and bit line BL 21 ; a P channel MOS transistor TAP 11 provided between an SP signal line transmitting a driving signal SP and bit line BL 21 ; an N channel MOS transistor TAN 12 provided between the SN signal line and the bit line /BL 21 ; and a P channel MOS transistor TAP 12 provided between the SP signal line and the bit line /BL 21 . The gates of transistors TAN 11 and TAP 11 are coupled to bit line /BL 21 , while the gates of transistors TAN 12 and TAB 12 are coupled to bit line BL 21 .

FIG. 32 is a schematic block diagram representing the configuration of the SD signal generating circuit 140 shown in FIG. 29 .

Referring to FIG. 32, SD signal generating circuit 140 includes a decode circuit 1402 receiving row predecode signals RA 0 and RA 1 and generating signals X 1 to X 4 , and signal converting circuits 1420 . 1 to 1420 . 4 for providing signals SD 1 and /SD 1 to SD 4 and /SD 4 , in response to the signals X 1 to X 4 , respectively.

Decode circuit 1402 includes: a logic gate 1404 responsive to activation of an inverted signal of signal RA 0 and activation of an inverted signal of signal RA 1 for setting the signal X 1 to the active state (“H” level); a logic gate 1406 responsive to activation of an inverted signal of the signal RA 0 and activation of the signal RA 1 for setting the signal X 2 to the active state; a logic gate 1408 responsive to activation of the signal RA 0 and activation of an inverted signal of signal RA 1 for setting the signal X 3 to the active state; and a logic gate 1410 responsive to activation of signals RA 0 and RA 1 for setting the signal X 4 to the active state.

Signal converting circuit 1420 . 1 includes an inverter INV 12 inverting the signal X 1 , and a driving circuit DR 51 . Basic configuration of driving circuit DR 51 is the same as the driving circuit DR 41 in accordance with the fourth embodiment described with reference to FIG. 15 . It should be noted, however, that the signal SD 1 is output from node n 13 , and the output of inverter INV 12 is provided as the signal /SD 1 . Except for these points, driving circuit DR 51 has the same structure as driving circuit DR 41 , and therefore, corresponding portions are denoted by the same reference characters and description thereof is not repeated.

Therefore, transistor TP 15 is a buried channel type P channel MOS transistor.

Signal converting circuits 1420 . 2 to 1420 . 4 basically have the same configuration as signal converting circuit 1420 . 1 .

When the signal X 1 is at the “H” level, for example, the output of inverter INV 12 is “L” and the output of inverter INV 11 is “H”. In response, transistor TN 12 is rendered conductive, setting the gate potential of transistor TP 15 to the ground potential GND. Transistor TP 15 is rendered conductive, and sets the level of node n 13 , that is, the level of the signal SD 1 to the potential Vpp.

Again referring to FIG. 29, the potential of a main word line MWL in the selected state is at the ground potential GND, transistor TSP 11 is conductive, and transistor TSN 11 is off. As the level of signal SD 1 attains to the potential Vpp, the potential level of sub word line SWL also attains to the potential Vpp.

In the above described structure, when the potential of node n 13 is to be increased to set the subword line to the selected state, buried channel type P channel MOS transistor TP 15 is used for driving, and therefore, it is possible to suppress degradation in reliability of P channel MOS transistor TP 15 caused by “channel hot carriers.” Further, in generating the bit line equalizing signal BLEQ and sense amplifier driving signals SN and SP, it is also possible to suppress degradation in reliability caused by “channel hot carriers.”

Though transistor TP 15 has been described as a buried channel type P channel MOS transistor above, the transistor TP 15 may be an LDD type P channel MOS transistor as in the first and second modifications of the fourth embodiment.

[First Modification of the Fifth Embodiment]

FIG. 33 is a schematic diagram representing the configuration of a driving circuit DR 51 ′ in the signal converting circuits 1420 . 1 to 1420 . 4 in accordance with the first modification of the fifth embodiment.

The basic configuration of the driving circuit DR 51 ′ is the same as that of the driving circuit DR 21 described with reference to FIG. 11 . It should be noted, however, that the signal SD 1 is output from node n 13 , and the output of inverter INV 12 is provided as the signal /SD 1 . Except for these points, the driving circuit DR 51 ′ has the same structure as driving circuit DR 21 , and therefore, corresponding portions are denoted by the same reference characters and description thereof will not be repeated.

In this configuration also, when the potential of node n 13 is to be increased, both N channel MOS transistor TN 14 and P channel MOS transistor TP 13 are used for driving.

Therefore, it is possible to suppress degradation in reliability of P channel MOS transistor TP 13 caused by “channel hot carriers.”

As the configuration of driving circuit DR 51 , the configuration of driving circuit DR 1 in accordance with the first embodiment or the configuration of DR 31 in accordance with the third embodiment may be used.

[Second Modification of the Fifth Embodiment]

FIG. 34 is a schematic diagram representing the configuration of a subword driver SWD′ in accordance with a second modification of the fifth embodiment.

In subword driver SWD′, the transistor TSP 11 in the configuration of subword driver SWD described with reference to FIG. 29 is a buried channel type P channel MOS transistor. Except for this point, subword driver SWD′ has the same structure as subword driver SWD. Therefore, corresponding portions are denoted by the same reference characters and description thereof will not be repeated.

In this configuration, when the potential of subword line SWL is to be increased, the potential is driven by the buried channel type P channel MOS transistor TSP 11 , and therefore degradation in reliability of transistor TSP 11 caused by the “channel hot carriers” can be suppressed.

Though transistor TSP 11 has been described as a buried channel type P channel MOS transistor in the foregoing, transistor TSP 11 may be an LDD type P channel MOS transistor as in the first and second modifications of the fourth embodiment.

[Sixth Embodiment]

FIG. 35 is a schematic diagram representing a configuration of a data output buffer DOB in the data I/O circuit portion 300 shown in FIG. 1 .

Referring to FIG. 35, data output buffer DOB includes an inverter INV 61 receiving a signal from a logic circuit 200 , and an inverter INV 62 receiving an output from inverter INV 61 and providing an output signal Dout.

Inverter INV 62 includes a buried channel type P channel MOS transistor TDP 11 and an N channel MOS transistor TDN 11 provided in series between an external power supply potential Ext.Vcc 2 and the ground potential GND. The signal Dout is provided from a connection node nd between transistors TDP 11 and TDN 11 .

In this configuration, when the potential of connection node nd is to be increased, the potential is driven by the buried channel type P channel MOS transistor TDP 11 . Therefore, it is possible to suppress degradation in reliability of transistor TDP 11 caused by “channel hot carriers.”

Though transistor TDP 11 has been described as a buried channel type P channel MOS transistor in the foregoing, transistor TDP 11 may be an LDD type P channel MOS transistor as in the first and second modifications of the fourth embodiment.

[Seventh Embodiment]

FIG. 36 is a schematic diagram representing another exemplary configuration of memory cell array 102 shown in FIG. 1 .

Referring to FIG. 36, the memory cell array is divided into N memory cell blocks MCB 1 to MCBN in the column direction, and sense amplifier bands SAB 0 to SABN are shared by adjacent memory cell blocks. For example, a plurality of bit line pairs in memory cell block MCB 2 are arranged to be coupled to sense amplifiers in sense amplifier band SAB 1 or sense amplifiers in sense amplifier band SAB 2 , alternately.

At every prescribed memory cell column, a subword driver band SWDB is provided along the row direction. The subword driver SWD in the subword driver band SWDB is driven by a main word line MWL (not shown) from the main word driver band MWDB.

In the following, regions where subword driver band SWDB intersects sense amplifier bands SAB 0 to SABN will be referred to as “intersecting regions ISR”. In the intersecting region ISR, in principle, neither the sense amplifier nor the subword driver is arranged.

FIG. 37 is a schematic diagram extracting and showing the configurations of memory cell block MCB 2 and sense amplifier bands SAB 1 and SAB 2 shown in FIG. 36 .

Referring to FIG. 37, the pair of bit lines BL 21 and /BL 21 can be electrically coupled to sense amplifier SA 11 in sense amplifier band SAB 1 through N channel MOS transistors TG 211 and TG 212 , respectively. The pair of bit lines BL 22 and /BL 22 next to the pair of bit lines BL 21 and /BL 21 can be electrically coupled to sense amplifier SA 21 in sense amplifier band SAB 2 through N channel MOS transistors TG 221 and TG 222 , respectively. Further, the pair of bit lines BL 23 and /BL 23 next to the pair of bit lines BL 22 and /BL 22 can be electrically coupled to sense amplifier SA 12 in sense amplifier band SAB 1 through N channel MOS transistors TG 232 and TG 232 , respectively.

The gate potentials of transistors TG 211 and TG 212 , TG 221 and TG 222 as well as TG 231 and TH 232 are driven by the signal BLI ( 2 , 0 ).

BLI signal driving circuit DBLI provides not only the signal BLI ( 2 , 0 ) but also an inverted signal thereof, that is, /BLI ( 2 , 0 ). The circuit DR in BLI signal driving circuit DBLI may have a similar configuration as the driving circuit DR 1 described with reference to the first embodiment. Alternatively, the driving circuit DR may have the configuration described with reference to FIGS. 11, 13 or 15 .

Further, the potential level of the line LB transmitting the signal BLI ( 2 , 0 ) is driven not only by the driving circuit DR but also by the P channel MOS transistor TBP provided at every intersecting region ISR. Here, transistor TBP is provided between the boosted potential Vpp and the line LB, and the gate potential thereof is driven by the signal /BLI ( 2 , 0 ).

In this configuration, when the potential of the line LB is to be increased, both the N channel MOS transistor TN 13 (not shown) in the driving circuit DR and surface channel type P channel MOS transistor TBP are used for driving. Therefore, degradation in reliability caused by “channel hot carriers” can be suppressed. Further, the transistor TBP is provided at every intersecting region, the time for driving the potential of the line LB can be made shorter.

Further, the P channel MOS transistor TBP may be a buried channel type P channel MOS transistor. Alternatively, P channel MOS transistor TBP may be an LDD type P channel MOS transistor as in the first and second modifications of the fourth embodiment.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.