Process for improving copper fill integrity

(1) Field of the Invention

The invention generally relates to an interconnection process used in semiconductor manufacturing and, more particularly, to a method for improving the reliability of connections between different layers of metal or conducting material in the fabrication of integrated circuits.

(2) Description of Prior Art

To improve the device speed of logic on sub-quarter micron semiconductor circuits, copper has gained popularity as an interconnect material. This takes advantage of the copper's low electrical resistivity and superior resistance to electro-migration. In circuit employing multi-level interconnection, vias are used to connect the different conducting levels. The vias must provide reliable, low resistance interconnection between the conducting levels.

Referring now to FIG. 1, a typical via process is depicted in cross-section. A substrate layer 10 is provided. The substrate layer 10 may contain underlying layers, devices, junctions, and other features covered by an insulating layer formed prior to deposition and patterning of the first conductive layer 12 . A silicon nitride (SiN) etch stop layer 14 is provided overlying the first conductive layer 12 . An inter-metal dielectric (IMD) layer 16 overlies the entire surface. An anisotropic etch is performed leaving via holes 18 in the IMD layer 16 . Referring now to FIG. 2, a second etch step is performed to remove the etch stop layer 14 not protected by the IMD) layer thereby extending the via holes 18 to the first conductive layer 12 . Because of the etch selectivity of the SiN etch stop layer 14 over the IMD layer 16 , a notch profile 19 results as shown at the bottom of the via hole 18 as shown in FIG. 2 .

Referring now to FIG. 3, a conductive glue layer 20 composed of tantalum nitride (TaN) is applied to the surface of the wafer, lining the via holes 18 . Thereafter a second conductive layer 22 such as copper is deposited on the surface of the wafer, filling the via holes 18 . The notch at the base of the via hole 18 causes discontinuous deposition of the conductive glue layer 20 and may result in an open or poor electrical connection between the first conductive layer 12 and the second conductive layer 22 . As shown in FIG. 4, chemical mechanical polishing (CMP) is used to planarize the surface exposing the top of the IMD layer 16 and completing the via structure.

The prior art shown above illustrates the difficulty in etching vias. Incomplete clearing of etch by-product residue at the bottom of narrow trenches and the formation of the notch profile may result in poor or open connections between the via metal and the first conductive layer. These problems may be exaggerated by the fact that etch rates increase in areas where via density is higher.

Other approaches improving interconnections exist. U.S. Patent No. 6,010,962 to Lui et al. teaches a method where a glue layer is deposited in a via hole followed by a thin seed copper layer. The via hole is filled with photoresist to keep contaminants from entering during CMP planarization. After CMP the photoresist is removed by dry ashing and. electroless plating is incorporated to fill the via hole with copper. U.S. Patent No. 6,054,398 to Pramanick teaches a method for using low-K fluorinated dielectrics in interconnection. Tantalum (Ta) is first conformally deposited in a carbon or silicon ambient to form a carbide or silicide along the sidewalls of the via hole. This suppresses the reaction between the Ta and the low-K fluorinated dielectrics. Thereafter the glue layer of Ta or tantalum nitride (TaN) can be applied to line the via hole which is then filled with copper. U.S. Pat. No. 5,654,232 to Gardner teaches a method using silicon nitride (SiN) as a via hole liner. Copper is sputtered onto the surface filling the via hole. While maintaining the vacuum from sputtering, the copper is reflowed and oxidation of the copper surface is avoided. U.S. Pat. No. 4,519,872 to Anderson, Jr. et al. teaches a method using polymers to create lift-off structures in the formation of multiple level interconnections. U.S. Patent No. 5,512,514 to Lee teaches a method of using pillars in the creation of vias in multilevel metalization. U.S. Patent No. 5,691,238 to Avanzino et al teaches a method using a dual and triple damascene process whereby pillars are created to complete interlevel connection. U.S. Patent No. 5,693,568 to Liu et al. teaches a method using two conductive layers with a conductive etch stop layer between them. First all three layers are selectively etched to form the pattern for the lower conductors. The openings between the conductors are then filled with a dielectric. The upper conductive layer is then patterned and etched to form the interlevel vias. The openings in the upper conductive layer are then filled and the wafer surface covered with dielectric. The surface is planarized exposing the tops of the upper conductive layer. This process is repeated to form multiple levels of interconnection. U.S. Pat. No. 5,846,876 to Bandyapadhyay et al. teaches a method using multiple conductive levels to reduce conductor spacing while avoiding problems of increased capacitance.

A principal object of the present invention is to provide a process that allows the formation of reliable interlevel conductor connection.

Another object of the present invention is to provide a process that allows the formation of reliable interlevel conductor connection by eliminating the problems associated with the discontinuous deposition of the glue layer at the bottom of the via resulting from the notch in the silicon nitride etch stop layer.

These objects are achieved by using a process where a substrate layer is provided containing underlying layers, devices, junctions, and other features covered by an insulating layer. First conductive layer traces are patterned and a silicon nitride (SiN) etch stop layer is provided overlying the first conductive layer. An inter-metal dielectric (IMD) layer overlies the entire surface. An anisotropic etch is performed leaving via holes in the IMD layer followed by a second anisotropic etch step to remove the etch stop layer not protected by the ID layer. This results in the formation of the notch profile described in the prior art. An ammonia (NH 3 ), nitrogen/hydrogen (N 2 /H 2 ) or N 2 plasma treatment is performed to nitridize the dielectric surfaces. A wet polymer process cleaning is performed which removes the nitridized surface of the dielectric layer thereby eliminating the notch. The process then continues as described in the prior art.

In the accompanying drawings forming a material part of this description, there is shown:

FIGS. 1 through 4 schematically illustrating in cross-sectional representation a prior art example of the via process.

FIGS. 5 through 10 schematically illustrating in cross-sectional representation a preferred embodiment of the present invention.

Referring now to FIG. 5, a substrate 30 is provided. The substrate layer 30 may contain underlying layers, devices, junctions, and other features formed in earlier process steps covered by an insulating layer. A first conductive layer 32 composed of a conductor from a group containing aluminum, copper (preferable), gold or alloys of aluminum, copper and/or gold overlies the substrate 30 . The first conductive layer 32 is deposited by copper electrochemical deposition (ECD) followed by planarization using chemical mechanical polishing (CMP) to yield a thickness of between about 2,500 to 4,000 Angstroms. This is followed by a etch stop layer 34 deposition composed of silicon nitride (SiN) or silicon carbide (SiC) by chemical vapor deposition (CVD) to a thickness of between about 300 to 800 Angstroms. An IMD layer 36 composed of undoped silicate glass (USG), fluorinated silicate glass (FSG) or other oxide based materials is deposited by CVD to a thickness of between about 6,000 to 20,000 Angstroms. The IMD layer 36 is then patterned and anisotropically etched to form via hole 38 . This is achieved by dry etching with a chemistry comprised of one or more from a list containing CF 4 , C 2 F 6 , C 4 F 8 , N 2 and O 2 at a pressure of between about 40 to 100mT and a power of between 500 to 1,500 watts.

Referring now to FIG. 6, the etch stop layer 34 is etched in the area not protected by the IMD layer 36 thereby extending via hole 38 . This is accomplished by dry etching with a chemistry comprised of one or more from a list containing CF 4 , C 2 F 6 , CHF 3 , C 4 F 8 , N 2 and O 2 at a pressure of between about 40 to 100mT and a power of between 200 to 1,000 watts. As described in the prior art, this results in the formation of a notch 39 in the etch stop layer 34 .

Referring now to FIG. 7, depicting an important step in the present invention. A plasma treatment using ammonia (NH 3 ), nitrogen/hydrogen (N 2 /H 2 ) or N 2 is performed at a temperature of between about 200 to 450° C., a flow rate of between about 500 to 5,000 sccm, a pressure of between about 0.5 to 5 Torr for 20 to 60 minutes. This step is to nitridize the IMD surface above the notch 39 yielding a SiNO layer 41 . The notch 39 is protected from the plasma treatment and is therefore less treated.

Referring now to FIG. 8, the SiNO layer 41 is subsequently removed by a polymer wet cleaning using a copper compatible solvent at a temperature of between about 25 to 110° C. for 10 to 30 minutes. Since the notch 39 is not nitridized, when the SiNO layer 41 above the notch 39 is removed, the un-nitridized notch 39 will disappear.

The process continues as described in prior art. Referring now to FIG. 9, a glue layer 40 composed of one from a list containing tantalum (Ta), tantalum nitride (TaN), or titanium nitride (TiN) is deposited by physical vapor deposition (PVD) to a thickness of between about 100 to 600 Angstroms. A second conductive layer 42 composed of one from a group containing aluminum, copper (preferable), gold or alloys of aluminum, copper and/or gold is deposited covering the surface and filling via hole 38 . The second conductive layer 42 is deposited by ECD to a thickness of between about 3,000 to 10,000 Angstroms, depending upon the thickness of the IMD layer 36 .

Referring now to FIG. 10, the via structure is completed by planarization using chemical mechanical polishing, for example, to remove the second conductive layer 42 and glue layer 40 not contained by the via hole 38 .

The present invention provides a process that allows the formation of reliable interlevel conductor connection by eliminating the problems associated with the discontinuous deposition of the glue layer at the bottom. This is accomplished by the addition of a plasma treatment and surface cleaning which eliminates the notch created during etching of the silicon nitride etch stop layer. This provides for uniform deposition of the glue layer thereby eliminating problems of agglomeration of the second conductive layer during annealing. The result is a reliable, low resistance via contact.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.