Inventor

Chao-Cheng Chen

Inventor
Hsinchu, TW

Overview

173→
Patents
1998–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 173 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H01LSemiconductor devices20%
H10DInorganic electric semiconductor devices20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
G06FElectric digital data processing6%
H01JElectric discharge tubes or discharge lamps2%
H04LTransmission of digital information, e.g. telegraphic communication1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
G06KGraphical data reading1%
PatentTitleYear
10,868,139Controlling profiles of replacement gates202010,854,729Method to reduce etch variation using ion implantation202010,854,742Metal gate electrode of a semiconductor device202010,831,828Method and system for improving datacenter operations utilizing layered information model202010,790,124Methods for removing particles from etching chamber202010,784,375Source/drain recess in a semiconductor device202010,762,139Method and system for managing a document search index202010,749,007Gate structure with desired profile for semiconductor devices202010,748,768Method for mandrel and spacer patterning202010,713,305Method and system for document search in structured document repositories202010,691,879Smart multimedia processing202010,691,757Method and system for cached document search202010,665,457Method of forming an integrated circuit using a patterned mask layer202010,658,509FinFET device202010,658,491Controlling profiles of replacement gates202010,614,089Managing opinion data202010,606,902Method and system for cached early-binding document search202010,572,544Method and system for document similarity analysis202010,553,699Gate structure of a semiconductor device202010,546,024Method and device for searching character string202010,521,656Method and system for assessing similarity of documents201910,515,955Methods of manufacturing transistor gate structures by local thinning of dummy gate stacks using an etch barrier201910,489,466Method and system for document similarity analysis based on weak transitive relation of similarity201910,490,648Method to reduce etch variation using ion implantation201910,447,799Method and apparatus for providing computing resources201910,418,460Dummy gate structure and methods thereof201910,409,871Apparatus and method for searching information201910,372,383Providing secure access to data in mobile devices201910,372,523Analysis system and method for intelligent customer service based on common sequence pattern201910,360,248Method and system for processing search queries using permission definition tokens201910,355,860Generating a QR code201910,332,991Metal gate electrode of a semiconductor device201910,331,717Method and apparatus for determining similar document set to target document from a plurality of documents201910,312,158Method for forming semiconductor device structure with gate structure201910,269,581Method of fabricating a semiconductor structure201910,269,937Semiconductor strips with undercuts and methods for forming the same201910,248,626Method and system for document similarity analysis based on common denominator similarity201910,241,998Method and system for tokenizing documents201910,170,367Semiconductor device and method201910,157,742Method for mandrel and spacer patterning201810,140,195Method, apparatus, and computer program product for backup and failure recovery in a storage device201810,117,956Radiolabeled active targeting pharmaceutical composition and the use thereof201810,089,389Translation of unstructured text into semantic models201810,083,872Methods for forming Fin field-effect transistors201810,061,864Method and system for improving datacenter operations utilizing layered information model201810,037,993Method of making a FinFET device201810,020,397Bottle-neck recess in a semiconductor device201810,005,990Cleaning method for semiconductor device fabrication20189,991,375Metal gate electrode of a semiconductor device20189,978,853Method of forming gate structure of a semiconductor device20189,947,764Dummy gate structure and methods thereof20189,941,407Method of forming FinFET20189,934,971Method of forming an integrated circuit using a patterned mask layer20189,934,945Methods for removing particles from etching chamber20189,923,079'Composite dummy gate with conformal polysilicon layer for FinFET device'20189,918,296'Method and device for positioning'20189,870,954'Simultaneous formation of source/drain openings with different profiles'20189,865,708'Semiconductor strips with undercuts and methods for forming the same'20189,852,337Method and system for assessing similarity of documents20179,825,173'FinFET device'20179,793,127'Plasma generation and pulsed plasma etching'20179,789,214'Radiolabeled active targeting pharmaceutical composition and the use thereof'20179,779,963'Method of fabricating a semiconductor structure'20179,761,684'Method and structure for metal gates'20179,685,344'Method of fabricating a semiconductor device including a plurality of isolation features'20179,685,332'Iterative self-aligned patterning'20179,640,398'Method of forming an integrated circuit using a patterned mask layer'20179,633,905'Semiconductor fin structures and methods for forming the same'20179,613,819'Process chamber, method of preparing a process chamber, and method of operating a process chamber'20179,601,333'Etching process'20179,595,443'Metal gate structure of a semiconductor device'20179,570,319'Method of manufacturing a semiconductor device'20179,564,488'Strained isolation regions'20179,548,305'Semiconductor devices and methods of manufacture thereof'20179,542,255'Troubleshooting based on log similarity'20179,536,980'Gate spacers and methods of forming same'20179,508,830'Method of forming FinFET'20169,496,372'Method of making a FinFET device'20169,472,414'Self-aligned multiple spacer patterning process'20169,460,968'Fin shape for fin field-effect transistors and method of forming'20169,461,144'Method for semiconductor device fabrication'20169,443,961'Semiconductor strips with undercuts and methods for forming the same'20169,436,930'Method and apparatus for recognizing image content'20169,431,513'Dummy gate structure and methods thereof'20169,431,304'Method and structure for metal gates'20169,412,666'Equal gate height control method for semiconductor device with different pattern densites'20169,384,988'Gate protection caps and method of forming the same'20169,379,220'FinFET device structure and methods of making same'20169,373,552'Method of calibrating or exposing a lithography tool'20169,355,874'Silicon nitride etching in a single wafer apparatus'20169,355,823'Methods for removing particles from etching chamber'20169,349,839'FinFET device structure and methods of making same'20169,337,195'Semiconductor devices and methods of manufacture thereof'20169,287,129'Method of fabricating FinFETs'20169,287,179'Composite dummy gate with conformal polysilicon layer for FinFET device'20169,281,196'Method to reduce etch variation using ion implantation'20169,276,089'FinFETs and methods for forming the same'20169,263,551'Simultaneous formation of source/drain openings with different profiles'20169,245,883'Method of making a FinFET device'20169,214,358'Equal gate height control method for semiconductor device with different pattern densites'20159,190,496'Method of making a FinFET device'20159,147,679'Method of semiconductor integrated circuit fabrication'20159,128,384'Method of forming a pattern'20159,123,743'FinFETs and methods for forming the same'20159,109,066'Method for preparing a flame retardant modified acrylonitrile-based copolymer and a flame retardant fibrous material'20159,111,861'Method of fabricating a semiconductor structure with ion-implanted conductive layer'20159,111,884'Finlike structures and methods of making same'20159,059,085'Method of forming an integrated circuit using a patterned mask layer'20159,054,130'Bottle-neck recess in a semiconductor device'20159,041,125'Fin shape for fin field-effect transistors and method of forming'20159,034,706'FinFETs with regrown source/drain and methods for forming the same'20158,946,014'FinFET device structure and methods of making same'20158,932,962'Chemical dispensing system and method'20158,932,936'Method of forming a FinFET device'20158,900,937'FinFET device structure and methods of making same'20148,889,502'Finlike structures and methods of making same'20148,772,183'Method of forming an integrated circuit'20148,765,556'Method of fabricating strained structure in semiconductor device'20148,748,989'Fin field effect transistors'20148,736,016'Strained isolation regions'20148,735,252'Method of semiconductor integrated circuit fabrication'20148,691,655'Method of semiconductor integrated circuit fabrication'20148,529,783'Method for backside polymer reduction in dry-etch process'20138,507,979'Semiconductor integrated circuit with metal gate'20138,409,964'Shallow trench isolation with improved structure and method of forming'20138,273,632'Patterning methodology for uniformity control'20128,258,588'Sealing layer of a field effect transistor'20128,120,094'Shallow trench isolation with improved structure and method of forming'20128,053,323'Patterning methodology for uniformity control'20117,833,853'Method of defining gate structure height for semiconductor devices'20107,759,239'Method of reducing a critical dimension of a semiconductor device'20107,713,380'Method and apparatus for backside polymer reduction in dry-etch process'20107,538,025'Dual damascene process flow for porous low-k materials'20097,511,349'Contact or via hole structure with enlarged bottom critical dimension'20097,354,524'Method and system for processing multi-layer films'20087,186,662'Method for forming a hard mask for gate electrode patterning and corresponding device'20077,169,701'Dual damascene trench formation to avoid low-K dielectric damage'20077,067,433'Method to reduce the fluorine contamination on the Al/Al-Cu pad by a post high cathod temperature plasma treatment'20067,033,518'Method and system for processing multi-layer films'20067,022,610'Wet cleaning method to eliminate copper corrosion'20066,995,085'Underlayer protection for the dual damascene etching'20066,960,496'Method of damascene process flow'20056,914,007'In-situ discharge to avoid arcing during plasma etch processes'20056,821,880'Process of dual or single damascene utilizing separate etching and DCM apparati'20046,809,028'Chemistry for liner removal in a dual damascene process'20046,790,770'Method for preventing photoresist poisoning'20046,616,855'Process to reduce surface roughness of low K damascene'20036,444,517'High Q inductor with Cu damascene via/trench etching simultaneous module'20026,440,863'Plasma etch method for forming patterned oxygen containing plasma etchable layer'20026,429,119'Dual damascene process to reduce etch barrier thickness'20026,383,943'Process for improving copper fill integrity'20026,323,121'Fully dry post-via-etch cleaning method for a damascene process'20016,319,822'Process for forming an integrated contact or via'20016,309,962'Film stack and etching sequence for dual damascene'20016,297,168'Edge defect inhibited trench etch plasma etch method'20016,277,752'Multiple etch method for forming residue free patterned hard mask layer'20016,211,061'Dual damascene process for carbon-based low-K materials'20016,194,128'Method of dual damascene etching'20016,194,284'Method for forming residue free etched silicon layer'20016,133,145'Method to increase the etch rate selectivity between metal and photoresist via use of a plasma treatment'20006,130,167'Method of preventing corrosion of a metal structure exposed in a non-fully landed via'20006,107,206'Method for etching shallow trenches in a semiconductor body'20006,043,163'HCL in overetch with hard mask to improve metal line etching profile'20006,040,248'Chemistry for etching organic low-k materials'20006,027,861'VLSIC patterning process'20006,025,273'Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask'20006,008,131'Bottom rounding in shallow trench etching using a highly isotropic etching step'19995,994,229'Achievement of top rounding in shallow trench etch'19995,989,784'Etch recipe for embedded DRAM passivation with etch stopping layer scheme'19995,981,398'Hard mask method for forming chlorine containing plasma etched layer'19995,970,376'Post via etch plasma treatment method for forming with attenuated lateral etching a residue free via through a silsesquioxane spin-on-glass (SOG) dielectric layer'19995,942,446'Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer'19995,807,789'Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI)'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (85)· patent assignee history
1998–2006Based in Tainan, TW· patent location history
1999–2004Based in Matou, TW· patent location history
2010–2020Based in Shin-Chu, TW· patent location history
2012–2017Patents assigned to CHEN CHAO-CHENG (20)· patent assignee history
2012–2020Based in Hsinchu, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (58)· patent assignee history
2016–2020Patents assigned to EMC CORP (13)· patent assignee history
2016–2020Based in Shanghai, CN· patent location history
2017–2020Patents assigned to EMC IP HOLDING CO LLC (23)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG851998–2016
TAIWAN SEMICONDUCTOR MFG CO LTD582016–2020
EMC IP HOLDING CO LLC232017–2020
CHEN CHAO-CHENGself202012–2017
EMC CORP132016–2020
Locations
LocationPatentsSpan
Hsinchu, TW652012–2020
Shin-Chu, TW352010–2020
Shanghai, CN272016–2020
Matou, TW161999–2004
Tainan, TW131998–2006