Soft error resistant circuits

1. Technical Field of the Invention

The present invention relates to circuits and, more particularly, to soft error resistant circuits, such as latches and dynamic circuits.

2. Background Art

Integrated circuit technology design has scaled over time. In particular, operating voltage and transistor device dimensions have become smaller and the chips are operating at higher frequencies. Hence the integrated circuits are becoming more susceptible to external interference. Cosmic rays have caused soft errors in memories and storage elements in the chips used at high altitudes by the aerospace community. A soft error is a change in the voltage state of a node in a circuit due to cosmic rays. Cosmic rays are increasingly likely to cause soft errors in integrated chips at ground levels because of the scaling of dimensions and voltage. The storage elements in a datapath such as in static latches and dynamic gates are becoming susceptible to soft errors and there is concern for an associated soft error rate (SER). Additional complexity arises from the lack of error correction in datapath.

Both neutrons and alpha particles can cause soft errors. Neutrons may cause hole-electron pairs in the substrate and also in wells close to the surface of the integrated circuit. An alpha particle may also cause hole-electron pairs to be created in the substrate, but it is believed that the alpha particles typically travel deeper into the integrated circuit so as to pass through wells.

As an example, FIG. 1 illustrates a schematic cross-sectional view of a portion of an integrated circuit 10 having an n-channel metal oxide semiconductor field effect transistor (NMOSFET) 14 and p-channel metal oxide semiconductor field effect transistor (PMOSFET) 16 . In the example, the drain diffusions D of NMOSFET 14 and PMOSFET 16 are connected at a node N 1 and the source diffusions S are respectively connected to a ground voltage (sometimes called Vss) and power supply voltage (sometimes called Vdd or Vcc). Assume the gates G of NMOSFET 14 and PMOSFET 16 are connected. Assume hole-electron pairs + and − are created in the p-substrate and also in the n-well of integrated circuit 10 .

The electrons (−) in the n-well are attracted to Vdd and the holes (+) in the p-substrate are attracted to Vss. If PMOSFET 16 is on and NMOSFET 14 is off, the drains are pulled high (Vcc). In that case, the electrons (−) in the p-substrate are attracted to drain diffusion D of NMOSFET 14 . If there are enough electrons attracted to drain diffusion D, the voltage state of node N 1 might change from high to low. Likewise, if PMOSFET 16 is off and NMOSFET 14 is on, the drains are pulled low (Vss). In that case, the holes (+) in the n-well are attracted to drain diffusion D of PMOSFET 16 . If there are enough holes attracted to drain diffusion D, the voltage state of node N 1 might change from low to high. With a closed loop system, the change in state may be permanent.

There is a need for soft error resistant techniques for datapath and control circuits that have a relatively small effect on performance.

In some embodiments, the invention includes a soft error resistant latch circuit. The latch circuit includes a storage node, a feedback node, and an inverter between the storage node and the feedback node. The latch circuit also includes split connection storage node drivers and split connection feedback node drivers each connected to the storage node and the feedback node.

In some embodiments, the invention includes a soft error resistant domino circuit a domino node, a keeper node, and a soft error resistant keeper. The soft error resistant keeper includes (a) a FET having a gate connected to the keeper node; (b) a FET having a gate connected to the domino node; and (c) an inverter between the domino and keeper nodes.

In some embodiments, the invention includes a soft error resistant domino circuit having a domino node, a keeper node, and an inverter between the domino and keeper nodes. The circuit also includes reverse connection keeper drivers connected between the domino node and the keeper node.

Additional embodiments are described and claimed.

The invention will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the invention which, however, should not be taken to limit the invention to the specific embodiments described, but are for explanation and understanding only.

FIG. 1 is a schematic cross-sectional representation of transistors in an integrated circuit.

FIG. 2 is a schematic representation of a prior art latch.

FIG. 3 is a schematic representation of a latch according to some embodiments of the invention.

FIG. 4 is a schematic representation of an optional modification to the latch of FIG. 4 .

FIG. 5 is a block diagram representation of a die in which one or more of the various circuits of the invention may be included.

FIG. 6 is a schematic representation of a prior art precharge domino circuit with a full keeper.

FIG. 7 is a schematic representation of a prior art precharge domino circuit with a half keeper.

FIG. 8 is a schematic representation of a precharge domino circuit according to some embodiments of the invention.

FIG. 9 is a schematic representation of a predischarge domino circuit according to some embodiments of the invention.

The invention involves circuits which are soft error resistant, yet still maintain high performance. The circuits include an inverter between first and second nodes, which makes state changes much more difficult. Examples of the first and second nodes include storage and feedback nodes in a latch, and domino and keeper nodes in a domino circuit. Soft error resistance is also increased through split connection node drivers and reverse connection keeper drivers, described below.

The present disclosure refers to p-channel field effect transistors (PETs) and n-channel field effect transistors (NFETs). The PFETs may be PMOSFETs or another type of p-channel field effect transistor. The NFETs may be NMOSFETs or another type of n-channel field effect transistor.

Latch Examples

Before describing embodiments of the present invention, FIG. 2 illustrates a prior art latch circuit 20 having a latch loop including a storage node N 4 , a feedback node N 8 , feedback node drivers, and storage node drivers, and a pass gate. The feedback node drivers include PFET T 1 and NFET T 3 . The storage node drivers include PFET T 4 and NFET T 6 . In some implementations, there may be an NFET (not shown) between T 4 and T 6 , the gate of which is driven by a scan (test mode) signal. The pass gate includes PFET T 8 and NFET T 9 . When a clock signal clk is low and clk* is high, pass gate transistors T 8 and T 9 are turned on and a value of input data signal din is written onto storage node N 4 . The value is inverted by an inverter I 1 or other output circuitry to create a output signal q.

Node N 4 has a parasitic capacitance CpN 4 and node N 8 has a parasitic capacitance CpN 8 . If there is a cosmic ray on any node, diffusion areas connected to that node may collect induced charge which may help cause soft errors. On the other hand, the overall capacitance (CpN 4 and CpN 8 ) and the recovery device (storage node and feedback node drivers) that hold the latch state fight against changes in state (soft errors). Cosmic rays may cause a low to high or high to low strike on both nodes N 4 and N 8 , although the capacitance CpN 4 is generally greater than CpN 8 , so node N 4 may be less susceptible to soft errors through strikes associated with diffusions on node N 4 .

When clk is high, the voltage state on node N 4 is maintained through transistors T 1 , T 2 , T 3 , T 4 , and T 6 as follows. Assume node N 4 is initially high. If node N 4 is high, T 4 is off and T 6 is on pulling node N 8 low. With node N 8 low and clock high, T 1 and T 2 are on and T 3 is off. With T 1 on and T 3 off, node N 4 is kept high through T 1 . Assume there is a cosmic ray strike so that node N 8 changes from low to high. In that case, T 1 begins to turn off and T 3 begins to turn on so node N 4 begins to go low. As node N 4 goes low, T 4 starts to turn on and T 6 starts to turn off which further pulls down node N 8 . Holes (positive charge) tend to be removed from node N 8 through T 6 . Further, parasitic capacitance CpN 8 on node N 8 inhibits the change of node N 8 from low to high. However, if the cosmic ray is strong enough, the state change of node N 8 will be complete before the holes can be removed through T 6 . The invention involves a more soft error resistant circuit arrangement.

FIG. 3 illustrates a latch circuit 30 according to some embodiments of the present invention. Referring to FIG. 3, a latch circuit 30 including a storage node N 14 , a feedback node N 18 and, a pass gate (including T 8 and T 9 ). In addition, latch circuit 30 includes split connection feedback node drivers, split connection storage node drivers, and an inverter I 2 between the nodes N 18 and N 14 . The split connection feedback node drivers include PFET T 17 and NFET T 16 . The split connection storage node drivers include PFET T 15 and NFET T 18 .

When a clock signal clk is low, pass gate transistors T 8 and T 9 are turned on and a value of input data signal din is written onto storage node N 14 . The value is inverted by an inverter I 1 or other output circuitry to create a output signal q. (Note that the invention is not limited to particular details of the output circuit. The output signal may be inverted or not inverted.) Node N 14 includes parasitic capacitance CpN 14 and node N 18 includes parasitic capacitance CpN 18 .

When clk is high, the voltage state on node N 14 is maintained through transistors T 15 , T 16 , T 17 , T 18 , and T 19 as follows. Assume that node N 14 is initially high and node N 18 is low. If node N 14 is high, T 15 is off and T 18 is on. With clk high, T 19 is on so that node N 18 is pulled low. With N 18 low, T 16 is off and T 17 is on pulling node N 14 high. Further, with N 18 low, inverter I 2 also causes node N 14 to be high. Assume there is a cosmic ray strike so that holes collecting on a diffusion associated with node N 18 cause node N 18 to change from low to high. In that case, T 17 begins to turn off and T 16 begins to turn on so node N 14 starts to go low. Further, inverter I 2 begins to pulls N 14 low. As node N 14 goes low, T 18 starts to turn off and T 15 starts to turn on which further pulls down node N 18 . However, the holes collecting on node N 18 are removed from node N 18 through T 18 and T 19 and the NFET of I 2 . Further, parasitic capacitance CpN 18 on node N 18 inhibits the change of node N 18 from low to high. Gate capacitance of inverter I 2 contributes to the parasitic capacitance CpN 18 , which is greater than CpN 8 in FIG. 2 . Also, the capacitance CpN 14 resists change to node N 14 . The overall effect is a substantial improvement in soft error resistance. Yet, inverter 12 responds relatively quickly to intended changes in state caused by writing data through the pass gate (T 8 and T 9 ).

Still referring to FIG. 3, assume instead that node N 14 is initially low and N 18 is high with clk high. In that case, T 17 and T 18 are off and T 15 is on pulling N 18 high and T 16 is on pulling N 14 low. Then, assume a cosmic ray strike causes node N 18 to change from high to low (a strike causes electrons to collect in a diffusion associated with node N 18 ). In that case, T 17 begins to turn on and T 16 begins to turn off so that N 14 begins to be pulled high. Also, inverter I 2 begins to pull N 14 high. However, parasitic capacitance CpN 18 resists the change and the electrons (negative charge) collected on N 18 are removed through T 15 and the PFET of 12 . Also, the capacitance CpN 14 resists change to node N 14 . The overall effect is a substantial improvement in soft error resistance.

Assume node N 14 is initially high and there is a cosmic ray strike producing electrons that collect in a diffusion associated with N 14 that would tend to cause node N 14 to change from high to low. The parasitic capacitances CpN 14 and CpN 18 will resist a change in state, while the electrons are removed from N 14 through T 17 and the PFET of I 1 . Now assume node N 14 is initially low and there is a cosmic ray strike producing holes on a diffusion associated with on node N 14 that would tend to cause node N 14 to change from low to high. The parasitic capacitances CpN 14 and CpN 18 will resist a change in state, while the holes are removed through T 16 and the NFET of I 1 . Although soft errors are still possible with sufficient induced charge, they are less likely with the invention.

Inverter I 2 may be designed using minimum sized devices. There are additional diffusions on storage node N 14 from inverter I 2 , however, for a large output driver, charge collection by the added diffusions tends to not cause soft errors. Due to these effects, in simulations, an embodiment of latch 30 of FIG. 3 yielded a 1.6X improvement in soft error resistance compared to prior art latch 20 of FIG. 2 . In other embodiments, the difference in change in soft error resistance may be different. An embodiment of latch 30 had a 40 pico second decrease in the time it took from the clk signal being received to the time output signal q appears at the output (40 pS clk2q performance gain) at the expense of 20 pico second increase in the time it took from the data din being received to the time output signal q appears at the output (20 pS data2q penalty). There is only a small area penalty of latch 30 as compared to latch 20 .

Inverter I 2 could be added to latch 20 of FIG. 2 to produce an embodiment of the invention. Further, an embodiment could be latch 30 without inverter I 2 . However, the full benefit of latch 30 occurs because latch 30 includes inverter I 2 and the two NFETs of the latch loop are swapped with split connection node drivers (contrast T 12 and T 6 of FIG. 2 with T 18 and T 16 of FIG. 3 ).

Note that the invention may encompass a variety of modifications to latch 30 . For example, the order of T 18 and T 19 may change. There may be additional transistors. For example, as shown in FIG. 4, in some embodiments, an NFET T 20 may be positioned between T 16 and ground (Vss), the gate of which is driven by a scan (test mode) signal. The direction of inverter I 2 could be changed so that N 14 is at the input and N 18 is at the output.

The various circuits described herein may be included in a die 50 shown in FIG. 5 .

Domino Circuit Examples

The invention may also be used in domino circuits. Before describing embodiments, prior art domino circuits are described in connection with FIGS. 6 and 7, which are well known examples of precharge domino circuits having transistors (e.g., having NFET transistors in an n-stack). Also well known are predischarge domino circuits in which the domino node is predischarged to ground during a predischarge phase and selectively pulled high during an evaluate phase (e.g., through PFET transistors in a p-stack).

Referring to FIG. 6, a domino circuit 60 includes a domino node N 30 , which is precharged through PFET T 33 to Vdd in a precharge phase during which clock is low. Then, in an evaluate phase, during which clock is high, node N 30 is conditionally brought low depending on the inputs to the evaluate transistors 64 . Node N 30 has a parasitic capacitance CpN 30 , which includes the gate capacitance of inverters 15 and 16 . Keeper transistor T 30 and inverter 16 keep node N 30 high assuming evaluate transistors 64 do not pull it low. An NFET T 31 keeps N 30 low after evaluate transistors 64 pull it low. Node 31 between inverter 16 and T 30 may be called a keeper node.

Referring to FIG. 7, domino circuit 70 is like domino circuit 60 in FIG. 6, except that it does not include T 31 . Domino circuit 60 is referred to as a full keeper domino circuit and domino circuit 70 is referred to as a half keeper domino circuit.

The domino node N 30 is strongly driven by the precharge PFET driven by clk during the precharge phase. During the evaluate phase, when the inputs are such that evaluate transistors 64 provide a path to ground, there is a strong pulldown strength on node N 30 . However, when the inputs are such that N 30 is not pulled to the low state by evaluate transistors 64 , a weak keeper T 30 is holding the domino node at the high state. Hence domino node N 30 is susceptible for soft errors during the evaluate phase when the domino node is held high by the weak keeper. Assume a cosmic ray strike causes electrons to change domino node N 30 from high to low. In that case, inverter I 6 will change node N 31 from low to high turning off T 30 (and turning on T 31 in the case of circuit 60 .) Capacitance CpN 30 will fight the change while the electrons are removed through T 30 or the PFETs of 15 and 16 . Upsizing the keeper is one common solution to avoid soft errors. However, this slows the performance.

The present invention provides increased soft error resistance as compared to that of FIGS. 6 and 7, while providing good performance.

Referring to FIG. 8, domino circuit 80 includes a domino node N 40 and a feedback node N 41 . An inverter I 7 is positioned between nodes N 40 and N 41 . A PFET T 40 is a keeper, such that when N 40 is high, node N 41 is low and T 40 pulls up N 40 . (T 40 and T 41 may tend to be weak to allow greater switching speed.) Also, when N 40 is high, T 41 is on pulling N 41 low, keeping T 40 on. T 40 , T 41 and inverter I 7 form a soft error resistant keeper circuit 86 . Further, reverse connection keeper drivers 88 includes driver T 40 to pull up node N 40 and driver T 41 to pull down node N 41 . Inverter I 7 can pull up or pull down node N 41 .

Parasitic capacitance CpN 40 is the parasitic capacitance of node N 40 and includes gate capacitance of inverters I 5 and I 7 . Although the output stage is shown as an inverter I 5 , it may be another circuit. The invention is not restricted to a particular kind of output stage or having any output stage at all.

When N 40 is high, there is a chance for it to be made low through a high to low strike on N 40 or a low to high strike on N 41 . Assume N 40 is high and a cosmic ray strike causes electrons to collect in a diffusion associated with node N 40 . In that case, N 40 would tend to change from high to low. T 41 would start to turn off and I 7 would start to switch so N 41 would start to go high causing T 40 to start to turn off. However, the capacitance CpN 40 would fight against a change of state (from high to low) in N 40 while electrons would be removed from node N 40 through T 40 and the PFETs of 15 and 17 . The invention provides a timing advantage. When the PFET of I 7 starts to pull up, the NFET of I 7 is still pulling down. Inverter I 7 could be skewed so that the NFET is more powerful. The overall effect of circuit 80 is a significantly improved soft error reduction with a relatively high switch speed performance (i.e., speed in output signal q responding to a change in inputs during the evaluate phase). Although soft errors are still possible, they are less likely.

Assume N 41 is low and a cosmic ray strike causes holes to collect in a diffusion associated with node N 41 . In that case, N 41 would tend to change from low to high. T 40 would start to turn off. However, holes would be removed through T 41 . Further, the parasitic gate capacitance of T 40 would fight the change on node N 41 . Parasitic capacitance CpN 40 would fight the change in node N 40 . The overall effect is that holes tend to be removed through T 41 before T 41 turns off and soft error resistance is improved. In alternative embodiments, the orientation of 17 is changed so the input of 17 is at N 41 and the output is at N 40 Oust the opposite in FIG. 9, discussed below). In that case, N 41 has more capacitance and N 40 has less.

When node N 40 is low, the evaluate transistors pull it low fairly hard so there is relatively little chance of it changing from low to high (likewise, little change of a strike to node N 41 changing node N 40 when N 40 is low.)

In some embodiments, domino circuit 60 includes only one p-n pair compared with the new latch configuration, latch 30 presented above. The reason being, the keeper has to maintain a single state, namely high, only on the domino node. As compared with a prior art full keeper circuit 60 , the keeper circuit of FIG. 8 does not include an n-diffusion on the domino node. In an embodiment, a simulation of this new configuration yielded about a 1.4X soft error resistance improvement compared to full and half keeper versions of prior art domino circuits 60 and 70 . Circuit 80 has about the same area as full keeper circuit 60 . In an embodiment, the performance of a simulation of circuit 80 is essentially identical to the half keeper dynamic gate and better than a full keeper dynamic gate.

FIG. 9 provides an example of the invention with a predischarge domino circuit 90 having a domino node N 50 that is precharged to ground (predischarged) through NFET T 44 when clk is low (clk* is high) during a predischarge phase. Domino node N 50 is selectively pulled high through evaluate transistors 94 during an evaluate stage. Parasitic capacitance CpN 50 is the parasitic capacitance of node 50 includes the gate capacitance of inverters I 5 and I 7 . A feedback node N 5 1 is between PFET T 40 and NFET T 41 .

In FIG. 9, T 40 , T 41 and inverter I 7 form a soft error resistant keeper circuit 96 . Further, reverse connection keeper drivers 98 includes driver T 40 to pull up node N 50 and driver T 41 to pull down node N 4 1 . Inverter I 7 can pull up or pull down node N 50 . Other arrangements for soft error resistant keeper circuit 96 and reverse connection keeper drivers 98 could be used.

Assume N 50 is low and a cosmic strike causes holes to collect in a diffusion(s) associated with N 50 . In that case, N 50 tends to change from low to high. T 40 would start to turn off and I 7 would start to turn on. When node N 50 is high, the evaluate transistors pull it fairly hard.

The invention is not restricted to use with any particular integrated circuit arrangement. For example, although enhancement mode transistors are shown, depletion mode transistors may be used. Although a p-substrate and n-well arrangement is shown in FIG. 1, a different arrangement may be used (e.g., n-substrate; p-well in p-substrate). The transistors may be forward, zero, or reverse biased. Additional transistors (e.g., for testing) may be included in the circuit without departing from the invention). The invention is not restricted to a precise order or timing of signals (e.g., clock signal with respect to other signals.)

In general, the sizes and threshold voltages of the various transistors can be set to achieve desired performance versus soft error resistance tradeoffs.

Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the invention. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.

If the specification states a component, feature, structure, or characteristic “may”, “might”, or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.

Those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present invention. Accordingly, it is the following claims including any amendments thereto that define the scope of the invention.