Semiconductor structure and method manufacturing the same

This application claims the priority benefit of U.S. provisional application Ser. No. 62/864,446, filed on Jun. 20, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

In recent years, the semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area. For example, the area occupied by integrated components is proximate to the surface of a semiconductor wafer; however, there are physical limitations to an achievable density in two-dimensional (2D) integrated circuit formation. For example, one of these limitations comes from the significant gains in the number and length of interconnections between semiconductor devices as the number of semiconductor devices increases. As the existing integrated circuit design rules require a decreasing pitch for laying out conductive wirings in a semiconductor structure, there is continuous effort in developing new mechanisms of forming semiconductor structures.

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 through FIG. 4 are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor die in accordance with some embodiments of the disclosure.

FIG. 5 through FIG. 24 are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure in accordance with some embodiments of the disclosure.

FIG. 25 is a schematic top view illustrating a relative position between a semiconductor die, a carrier die and an insulating encapsulation of a semiconductor structure in accordance with some embodiments of the disclosure.

FIG. 26A is an enlarged and schematic cross-sectional view showing a bonding interface between a semiconductor die and a carrier die underlying thereto in a dashed area A outlined in FIG. 11 in accordance with some embodiments of the disclosure.

FIG. 26B is an enlarged and schematic cross-sectional view showing a bonding interface between a semiconductor die and a carrier die underlying thereto in accordance with some embodiments of the disclosure.

FIG. 27A is an enlarged and schematic cross-sectional view showing a bonding interface between adjacent tiers of a die stack in a dashed area B outlined in FIG. 17 in accordance with some embodiments of the disclosure.

FIG. 27B is an enlarged and schematic cross-sectional view showing a bonding interface between adjacent tiers of a die stack in accordance with some embodiments of the disclosure.

FIG. 28A is an enlarged and schematic cross-sectional view showing a bonding interface between adjacent tiers of a die stack in a dashed area C outlined in FIG. 19 in accordance with some embodiments of the disclosure.

FIG. 28B is an enlarged and schematic cross-sectional view showing a bonding interface between adjacent tiers of a die stack in accordance with some embodiments of the disclosure.

FIG. 28C is an enlarged and schematic cross-sectional view showing a bonding interface between adjacent tiers of a die stack in accordance with some embodiments of the disclosure.

FIG. 29A is an enlarged and schematic cross-sectional view illustrating a configuration of an outermost tier of a die stack in a dashed area D outlined in FIG. 19 in accordance with some embodiments of the disclosure.

FIG. 29B is an enlarged and schematic cross-sectional view illustrating a configuration of an outermost tier of a die stack in accordance with some embodiments of the disclosure.

FIG. 30 through FIG. 44 are schematic cross-sectional views respectively showing a semiconductor structure in accordance with some embodiments of the disclosure.

FIG. 45 is a schematic cross-sectional view showing a semiconductor structure in accordance with some embodiments of the disclosure.

FIGS. 46A and 46B are schematic top views respectively illustrating a relative position between a semiconductor die, a carrier die and an insulating encapsulation of a semiconductor structure in accordance with some embodiments of the disclosure.

FIG. 47 is a schematic cross-sectional view showing a semiconductor structure in accordance with some embodiments of the disclosure.

FIG. 48A and FIG. 48B are schematic top views respectively illustrating a relative position between a semiconductor die, a carrier die and an insulating encapsulation of a semiconductor structure in accordance with some embodiments of the disclosure.

FIG. 49 through FIG. 56 are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure in accordance with some embodiments of the disclosure.

FIG. 57 is a schematic top view illustrating a relative position between a semiconductor die, a carrier die and an insulating encapsulation of a semiconductor structure in accordance with some embodiments of the disclosure.

FIG. 58 is a schematic cross-sectional view showing an application of a semiconductor structure in accordance with some embodiments of the disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In addition, terms, such as “first”, “second”, “third” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIG. 1 through FIG. 4 are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor die in accordance with some embodiments of the disclosure. Referring to FIG. 1 , in some embodiments, a semiconductor wafer W 1 is provided. In some embodiments, the semiconductor wafer W 1 includes a plurality of semiconductor dies 10 A′ connected to one another. For example, each of the semiconductor dies 10 A′ may include an integrated circuit device (e.g., a logic die, a memory die, a radio frequency die, a power management die, a micro-electro-mechanical-system (MEMS) die, the like, or combinations of these). In some embodiments, a thickness T 1 of the semiconductor wafer W 1 is in a range of about 720 μm to about 800 μm.

For example, each of the semiconductor dies 10 A′ includes a semiconductor substrate 110 having semiconductor devices (not shown) formed therein, an interconnect structure 120 formed on the semiconductor substrate 110 , a plurality of conductive vias 130 formed in the semiconductor substrate 110 and extending into the interconnect structure 120 , a dielectric layer 140 formed on the interconnect structure 120 and opposite to the semiconductor substrate 110 , and a plurality of bonding conductors 150 formed over the interconnect structure 120 and laterally covered by the dielectric layer 140 . In some embodiments, as shown in FIG. 1 , each of the semiconductor dies 10 A′ has a front surface S 1 and a bottom surface 110 b ′ opposite to the front surface S 1 . The bonding conductors 150 are distributed at the front surface S 1 and accessibly revealed by the dielectric layer 140 , and the bottom surface 110 b ′ may be considered to the side distal from the interconnect structure 120 and the bonding conductors 150 .

In some embodiments, the semiconductor substrate 110 includes a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, other supporting substrate (e.g., quartz, glass, etc.), combinations thereof, or the like, which may be doped or undoped. In some embodiments, the semiconductor substrate 110 includes an elementary semiconductor (e.g., silicon or germanium in a crystalline, a polycrystalline, or an amorphous structure, etc.), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, etc.), an alloy semiconductor (e.g., silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminium gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure. In some embodiments, the alloy SiGe is formed over a silicon substrate. In other embodiments, a SiGe substrate is strained. The semiconductor substrate 110 may include the semiconductor devices (not shown) formed therein or thereon, and the semiconductor devices may be or may include active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, inductors, etc.), or other suitable electrical components. In some embodiments, the semiconductor devices are formed at the side of the semiconductor substrate 110 proximal to the interconnect structure 120 .

The semiconductor substrate 110 may include circuitry (not shown) formed in a front-end-of-line (FEOL), and the interconnect structure 120 may be formed in a back-end-of-line (BEOL). In some embodiments, the interconnect structure 120 includes an inter-layer dielectric (ILD) layer formed over the semiconductor substrate 110 and covering the semiconductor devices, and an inter-metallization dielectric (IMD) layer formed over the ILD layer. In some embodiments, the ILD layer and the IMD layer are formed of a low-K dielectric material or an extreme low-K (ELK) material, such as an oxide, silicon dioxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), fluorinated silicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like. The ILD layer and the IMD layer may include any suitable number of dielectric material layers which is not limited thereto.

In some embodiments, the interconnect structure 120 including one or more dielectric layer(s) (e.g., dielectric layers DI 1 illustrated in FIG. 26A ) and one or more metallization pattern(s) (e.g., metallization patterns MP illustrated in FIG. 26A ) is formed on the semiconductor substrate 110 . The metallization pattern(s) may be embedded in the dielectric layers (e.g., the IMD layers), and the metallization patterns (e.g., metal lines, metal vias, metal pads, metal traces, etc.) may be formed of conductive materials such as copper, gold, aluminum, the like, or combinations thereof. In some embodiments, the interconnect structure 120 is electrically coupled to the semiconductor devices formed in and/or on the semiconductor substrate 110 to one another and to external components (e.g., test pads, bonding conductors, etc.). For example, the metallization patterns in the dielectric layers route electrical signals between the semiconductor devices of the semiconductor substrate 110 . The semiconductor devices and metallization patterns are interconnected to perform one or more functions including memory structures (e.g., memory cell), processing structures, input/output circuitry, or the like. The outermost layer of the interconnect structure 120 may be a passivation layer (e.g., a passivation layer PL illustrated in FIG. 26A ) made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics, polyimide, combinations of these, or the like. In some embodiments, each of the semiconductor dies 10 A′ includes a conductive pad (e.g., a conductive pad AP illustrated in FIG. 26A ) disposed over and electrically coupled to the top metallization pattern of the interconnect structure 120 , and the passivation layer of the interconnect structure 120 may have an opening exposing at least a portion of the conductive pad for testing or for further electrical connection.

In some embodiments, the conductive vias 130 are formed to extend into the semiconductor substrate 110 . The conductive vias 130 may be in physical and electrical contact with the metallization patterns of the interconnect structure 120 . For example, when the conductive vias 130 are initially formed, the conductive vias 130 are embedded in the semiconductor substrate 110 and may not extend to the bottom surface 110 b ′ of the semiconductor substrate 110 . That is, for the semiconductor wafer W 1 , the conductive vias 130 are not accessible revealed by the semiconductor substrate 110 .

For example, each of the conductive vias 130 may include a barrier material (e.g., TiN, Ta, TaN, Ti, or the like; not shown) and a conductive material (e.g., copper, tungsten, aluminum, silver, combinations thereof, or the like; not shown). For example, the barrier material may be formed between the conductive material and the semiconductor substrate 110 .

In alternative embodiments, a dielectric liner (not shown) (e.g., silicon nitride, an oxide, a polymer, a combination thereof, etc.) may be further optionally formed between the barrier material of the conductive vias 130 and the semiconductor substrate 110 . In some embodiments, the conductive vias 130 are formed by forming recesses in the semiconductor substrate 110 and respectively depositing the dielectric liner, the barrier material, and the conductive material in the recesses, removing excess materials on the semiconductor substrate 110 . For example, the recesses of the semiconductor substrate 110 are lined with the dielectric liner so as to laterally separate the conductive vias 130 from the semiconductor substrate 110 . The conductive vias 130 may be formed by using a via-first approach. For example, the conductive vias 130 are formed during the formation of the interconnect structure 120 . Alternatively, the conductive vias 130 may be formed by using a via-last approach, and may be formed after the formation of interconnect structure 120 . The disclosure is not limited thereto.

In some embodiments, the dielectric layer 140 is formed on the interconnect structure 120 . For example, the dielectric layer 140 includes one or more layers (e.g., dielectric layers DI 2 , DI 3 , DI 4 illustrated in FIG. 26A ) of dielectric materials (e.g., silicon nitride, silicon oxide, high-density plasma (HDP) oxide, tetra-ethyl-ortho-silicate (TEOS), undoped silicate glass (USG), the like, or a combination thereof). In some embodiments, the dielectric layer 140 laterally covering the bonding conductor 150 is subsequently used for bonding. It should be appreciated that the dielectric layer 140 may include etch stop material layer(s) (not shown) interposed between the dielectric material layers depending on the process requirements. For example, the etch stop material layer is different from the overlying or underlying dielectric material layer(s). The etch stop material layer may be formed of a material having a high etching selectivity relative to the overlying or underlying dielectric material layer(s) so as to be used to stop the etching of layers of dielectric materials. The structure of the dielectric layer 140 will be described in detail later in conjunction with figures.

In some embodiments, the bonding conductors 150 , such as bond vias (e.g., bond vias 150 b illustrated in FIG. 26A ) and/or bond pads (e.g., a bond pad 150 a illustrated in FIG. 26A ), are formed over the interconnect structure 120 to provide an external electrical connection to the circuitry and semiconductor devices. In the disclosure, the bonding conductors 150 each have a bond pad with two or more than two bond vias disposed thereon. The bonding conductors 150 may be formed of conductive materials such as copper, gold, aluminum, the like, or combinations thereof. The bonding conductors 150 may be electrically coupled to the semiconductor devices of the semiconductor substrate 110 through the interconnect structure 120 . The bonding conductors 150 may be substantially leveled with the dielectric layer 140 for bonding. The above examples are provided for illustrative purposes, other embodiments may utilize fewer or additional elements (e.g., conductive pads), and the details of the semiconductor dies will be described later in accompanying with enlarged views. In the other words, for example, it may be also saying that the semiconductor wafer W 1 includes the semiconductor substrate 110 , the interconnect structure 120 , the conductive vias 130 , the dielectric layer 140 , and the bonding conductors 150 , as shown in FIG. 1 .

Referring to FIG. 2 , in some embodiments, the semiconductor wafer W 1 is placed on a temporary carrier TC 1 by a temporary bonding layer TB 1 . A material of the temporary carrier TC 1 may include glass, metal, ceramic, silicon, plastic, combinations thereof, multi-layers thereof, or other suitable material that can provide structural support for the semiconductor wafer W 1 in subsequent processing. In some embodiments, the temporary carrier TC 1 is made of glass, and the temporary bonding layer TB 1 used to adhere the semiconductor wafer W 1 to the temporary carrier TC 1 includes a polymer adhesive layer (e.g., die attach film (DAF)), a ultra-violet (UV) cured layer, such as a light-to-heat conversion (LTHC) release coating, ultra-violet (UV) glue, which reduces or loses its adhesiveness when exposed to a radiation source (e.g., UV light or a laser). Other suitable temporary adhesives may be used. In some embodiments, the temporary carrier TC 1 is a silicon wafer, and the temporary bonding layer TB 1 includes a silicon-containing dielectric material (e.g., silicon oxide, silicon nitride, etc.) or other suitable dielectric material(s) used for bonding. For example, the bonding includes oxide-to-oxide bonding, and the dielectric layer 140 of the semiconductor wafer W 1 is bonded to the temporary bonding layer TB 1 . Alternatively, the temporary bonding layer TB 1 may be omitted.

In some embodiments, a front-side FS of the semiconductor wafer W 1 (e.g. the front surfaces S 1 of the semiconductor dies 10 A′) is attached to the temporary carrier TC 1 and a back-side BS of the semiconductor wafer W 1 (e.g. the bottom surfaces 110 b ′ of the semiconductor dies 10 A′) faces upwardly for subsequent processing, as shown in FIG. 2 . The front-side FS is opposite to the back-side BS along a stacking direction Z of the semiconductor substrate 110 and the interconnect structure 120 , for example.

Referring to FIG. 2 and FIG. 3 , in some embodiments, the semiconductor wafer W 1 is thinned to form a thinned semiconductor wafer W 1 ′ by, for example, etching, grinding, a chemical mechanical polishing (CMP) process, combinations thereof, or other suitable thinning techniques. For example, a thinning process is performed on the back-side BS of the semiconductor wafer W 1 (e.g. the bottom surfaces 110 b ′ of the semiconductor dies 10 A′) to obtain the thinned semiconductor wafer W having a reduced thickness T 2 . That is, the reduced thickness T 2 of the thinned semiconductor wafer W 1 ′ is less than the thickness T 1 of the semiconductor wafer W 1 . In some embodiments, the reduced thickness T 2 is in a range of about 40 μm to about 200 μm. As shown in FIG. 3 , after the thinning process, the conductive vias 130 are not yet accessibly revealed through a back-side BS of the thinned semiconductor wafer W 1 ′ (e.g., a bottom surfaces 110 b ″ of the semiconductor dies 10 A″). In other words, for each semiconductor die 10 A″, bottom surfaces 130 b of the conductive vias 130 are not accessibly exposed by the bottom surface 110 b ″ of the semiconductor dies 10 A″.

Continue to FIG. 4 , in some embodiments, after the wafer backside thinning process, the thinned semiconductor wafer W 1 ′ is mounted on the tape frame TP 1 . For example, the structure shown in FIG. 3 is overturned (e.g., flipped upside down along the stacking direction Z), such that the back-side BS of the thinned semiconductor wafer W 1 ′ (e.g., the bottom surfaces 110 b ″ (of semiconductor substrates 110 ) of the semiconductor dies 10 K′) is disposed on the tape frame TP 1 . Next, a de-bonding process may be performed on the temporary carrier TC 1 to release from the thinned semiconductor wafer W 1 ′. For example, external energy (e.g., UV light or a laser) is applied on the temporary bonding layer TB 1 . Alternatively, the removal process of the temporary carrier TC 1 may include a mechanical peel-off process, a grinding process, an etching process, or the like. In some embodiments, a cleaning process is performed to remove residues of temporary bonding layer TB 1 from the thinned semiconductor wafer W 1 ′ by using suitable solvent, cleaning chemical, or other cleaning techniques. Subsequently, a singulation process is performed on the thinned semiconductor wafer W 1 ′ to obtain a plurality of separated and individual semiconductor die 10 A″. As shown in FIG. 4 , the separated and individual semiconductor die 10 A″ each has the front surface S 1 and the bottom surface 110 b ″, for example.

For example, the tape frame TP 1 holds the thinned semiconductor wafer W 1 ′ in place during the singulation process, and a dicing tool (e.g., a saw) may be used to cut through the thinned semiconductor wafer W 1 ′ along the scribe lines (not shown). In other embodiments, the singulation process is performed prior to mounting on the tape frame TP 1 . In some embodiments, before dicing/singulating, the semiconductor dies 10 A″ included in the thinned semiconductor wafer W 1 ′ are tested for functionality and performance by probing, and only known good dies (KGDs) from the tested semiconductor dies 10 A″ are selected and used for subsequently processing.

In some embodiments, the temporary carrier TC 1 illustrated in FIG. 2 and FIG. 3 may be replaced by the tape frame TP 1 . For example, the semiconductor wafer W 1 is mounted on the first tape frame with the front-side FS of the semiconductor wafer W 1 facing towards the first tape frame, and then the thinning process is performed on the back side BS of the semiconductor wafer W 1 . Subsequently, the thinned semiconductor wafer W 1 ′ is transferred to be mounted on the second tape frame with the back side BS of the thinned semiconductor wafer W 1 ′ (e.g., the bottom surface 110 b ″ of semiconductor dies 10 A″) facing towards the second tape frame, and then the singulation process is performed, and the second tape frame holds the thinned semiconductor wafer W 1 ′ in place during the singulation process. It should be noted that above examples are provided for illustrative purposes, the formation of the semiconductor dies 10 A″ can be formed in any logical order which are not limited in the disclosure.

FIG. 5 through FIG. 24 are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure in accordance with some embodiments of the disclosure, and are taken along a cross-sectional line I-I depicted in FIG. 25 . FIG. 25 is a schematic top view illustrating a relative position between a semiconductor die, a carrier die and an insulating encapsulation of a semiconductor structure in accordance with some embodiments of the disclosure. FIG. 26A is an enlarged and schematic cross-sectional view showing a bonding interface between a semiconductor die and a carrier die underlying thereto in a dashed area A outlined in FIG. 11 in accordance with some embodiments of the disclosure. FIG. 27A is an enlarged and schematic cross-sectional view showing a bonding interface between adjacent tiers of a die stack in a dashed area B outlined in FIG. 17 in accordance with some embodiments of the disclosure. FIG. 28A is an enlarged and schematic cross-sectional view showing a bonding interface between adjacent tiers of a die stack in a dashed area C outlined in FIG. 19 in accordance with some embodiments of the disclosure. FIG. 29A is an enlarged and schematic cross-sectional view illustrating a configuration of an outermost tier of a die stack in a dashed area D outlined in FIG. 19 in accordance with some embodiments of the disclosure. The manufacturing method of the semiconductor structure includes bonding a die stack (e.g., 100 ) to a carrier die (e.g., 10 B), where forming the die stack involves the stacked semiconductor dies (e.g., 10 A and 10 A′). Like elements are designated with the same reference numbers for ease of understanding and the details thereof are not repeated herein, for simplicity.

Referring to FIG. 5 , in some embodiments, at least one semiconductor die 10 B′ is provided. For example, a semiconductor wafer (not shown) is processed in a manner as described in FIG. 1 through FIG. 4 to generate individual semiconductor dies 10 B′, and thus the formation of the semiconductor dies 10 B′ is not repeated here for simplicity. The semiconductor dies 10 B′ each may include a structure similar to the semiconductor dies 10 A″. For example, each of the semiconductor dies 10 B′ has a front surface S 3 and a bottom surface 210 b ′ opposite to the front surface S 3 , and includes the semiconductor substrate 210 having semiconductor devices formed therein, the interconnect structure 220 formed over the semiconductor substrate 210 and including dielectric layers and metallization patterns proximal to the front surface S 3 , and the conductive vias 230 formed in the semiconductor substrate 210 and extending into the dielectric layers of the interconnect structure 220 to be in physical and electrical contact with the metallization pattern of the interconnect structure 220 . The conductive vias 230 of each of the semiconductor dies 10 B′ may be electrically coupled to the semiconductor devices and the metallization patterns of the interconnect structure 220 .

For illustrative purposes, only two semiconductor dies 10 B′ are shown in FIG. 5 ; however, the number of the semiconductor dies 10 B′ is not limited to the disclosure. The number of the semiconductor dies 10 B′ may be one or more than one based on the design layout and demand.

It should be noted that various layers and features of each of the semiconductor dies 10 B′ are omitted from the figures. For example, the interconnect structure 220 includes a passivation layer (not individually illustrated) formed over the top metallization pattern of the interconnect structure 220 in order to provide a degree of protection for the underlying structures. The passivation layer may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics, polyimide, combinations of these, or the like. The conductive pads may be covered by the passivation layer at this point for protection.

It is appreciated that semiconductor dies diced from different semiconductor wafers may have different properties and functions. In some embodiments, the semiconductor dies 10 B′ and the semiconductor dies 10 A″ are singulated from different semiconductor wafers, and may be different in functions and properties. For example, the semiconductor dies 10 B′ depicted in FIG. 5 are logic dies (e.g., a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), etc.). On the other hand, the semiconductor dies 10 A″ described in FIG. 4 are, for example, memory dies (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a synchronous dynamic random access memory (SDRAM), a NAND flash, etc.). As shown in FIG. 5 , for example, two semiconductor dies 10 B′ are shown for illustration purposes; however, the number of the semiconductor dies 10 B′ is not limited to what is depicted in the disclosure, and may be selected and designated based on the demand and design layout.

Referring to FIG. 6 and FIG. 7 , in some embodiments, the semiconductor dies 10 B′ are disposed on the temporary carrier TC 2 through the temporary bonding layer TB 2 . For example, the semiconductor wafer including the semiconductor dies 10 B′ is probed and tested before singulating. After performing the singulation process, only known good semiconductor dies 10 B′ are picked and placed on the temporary carrier TC 2 . In some embodiments, the temporary bonding layer TB 2 is deposited on the temporary carrier TC 2 , and the front surface S 3 of each of the semiconductor dies 10 B′ is attached to the temporary carrier TC 2 through the temporary bonding layer TB 2 . In alternative embodiments, the temporary bonding layer TB 2 may be omitted. The formation and/or material of the temporary bonding layer TB 2 and the temporary carrier TC 2 are similar to the formation and/or material of the temporary bonding layer TB 1 and the temporary carrier TC 1 described in FIG. 2 , thus are not repeated herein. As shown in FIG. 6 , for example, the bottom surfaces 210 b ′ of the semiconductor dies 10 B′ face upwardly for subsequent processing.

Thereafter, for each of the semiconductor dies 10 B′, a thinning process (e.g., etching, grinding, CMP process, or the like) is performed on the bottom surface 210 b ′ of the semiconductor substrate 210 until the conductive vias 230 are exposed by a bottom surface 210 b ″ of the semiconductor substrate 210 so as to form thinned semiconductor dies 10 B″. For example, after attaching the semiconductor dies 10 B′ to the temporary bonding layer TB 2 , the semiconductor dies 10 B′ are thinned to form the thinned semiconductor dies 10 B″ each having a thickness T 3 approximately ranging from 5 μm to 100 μm. In some embodiments, the thickness T 3 is less than the thickness T 2 . As shown in FIG. 7 , in some embodiments, in each of the thinned semiconductor dies 10 B″, bottom surfaces 230 b of the conductive vias 230 are accessibly exposed by the bottom surface 210 b ″ of the semiconductor substrate 210 . For example, in each thinned semiconductor dies 10 B″, the bottom surfaces 230 b of the conductive vias 230 are substantially levelled with and coplanar to the bottom surface 210 b ″ of the semiconductor substrate 210 . In each of the thinned semiconductor dies 10 B″, the conductive vias 230 , which penetrate through the semiconductor substrate 210 , are referred to as through semiconductor vias (TSVs) or through silicon vias when the semiconductor substrate 210 is a silicon substrate.

Referring to FIG. 8 , in some embodiments, the thinned semiconductor dies 10 B″ are recessed such that the conductive vias 230 are protruded from the semiconductor substrate 210 . In other words, the semiconductor substrate 210 of each of the thinned semiconductor dies 10 B″ is partially removed to obtain a bottom surface 210 b , and a portion of each of the conductive vias 230 protrudes out of the bottom surface 210 b of the semiconductor substrate 210 . After recessing, in the cross-section shown in FIG. 8 , a plurality of recesses R 1 are formed, where each of the recesses R 1 is formed on the bottom surface 210 b and between the protruded portions of two adjacent conductive vias 230 . The recesses R 1 each has a depth D 1 approximately ranging from 0.5 μm to 1.5 μm (as measured along the stacked direction Z), for example.

During the recessing process, the semiconductor substrate 210 of each of the thinned semiconductor dies 10 B″ may be partially removed by etching. For example, the etching process has a high etch-rate selectivity to the material of the semiconductor substrate 210 over the material of the conductive vias 230 and the material of the temporary bonding layer TB 2 . For example, the removed amount of the semiconductor substrate 210 may be controlled by adjusting the etching time. In some embodiments, the conductive vias 230 and the temporary bonding layer TB 2 may remain intact during recessing. The etching process may include a dry etching, a wet etching or a combination thereof. In some embodiments, a cleaning process is performed to remove residues of the etching process by using suitable solvent, cleaning chemical, or other cleaning techniques.

Referring to FIG. 9 , in some embodiments, an isolation layer 50 is formed over the temporary carrier TC 2 and on the thinned semiconductor dies 10 B″. In some embodiments, the isolation layer 50 includes a first lateral portion 50 a , a second lateral portion 50 b and a connecting portion 50 c . For example, as shown in FIG. 9 , the first lateral portion 50 a is disposed on and extends over the temporary bonding layer TB 2 , the second lateral portion 50 b is disposed on and extends over the bottom surfaces 210 b of the semiconductor substrates 210 and the bottom surfaces 230 b and sidewalls 230 s of the conductive vias 230 , and the connecting portion 50 c is disposed on the first lateral portion 50 a and extended to be in contact with the second lateral portion 50 b . In some embodiments, the isolation layer 50 has a thickness T 50 approximately ranging from 0.5 μm to 1.6 μm, where the thickness T 50 is measured with a minimum distance between to opposite sides of the isolation layer 50 . As shown in FIG. 9 , the second lateral portion 50 b fills the recesses R 1 . In one embodiment, the thickness T 50 is greater than the depth D 1 , however the disclosure is not limited thereto. In an alternative embodiment, the thickness T 50 is substantially equal to the depth D 1 . In other words, the isolation layer 50 is thick enough to cover the protruded portions of the conductive vias 230 .

In some embodiments, the first lateral portion 50 a and the second lateral portion 50 b are extended laterally, such as along a direction X and/or a direction Y depicted in FIG. 9 . For example, the direction X is different from direction Y, and the directions X and Y are independently perpendicular to the stacking direction Z. In some embodiments, the connecting portion 50 c is extended vertically to connect the first lateral portion 50 a and the second lateral portion 50 b . For example, the connecting portion 50 c may be extended upwards in a manner of straight-form as shown in FIG. 9 . However, the connecting portion 50 c may be extended upwards in a manner of step-form (e.g., a connecting portion 51 c in FIG. 15 ).

In some embodiments, the isolation layer 50 may be conformally formed over the temporary carrier TC 2 by, for example, spin-coating, a chemical vapor deposition (CVD) process, or the like. In some embodiments, a material of the isolation layer 50 may include a nitride (such as silicon nitride), an oxide (such as silicon oxide) or the like (such as, silicon oxynitride, silicon carbide, a polymer, the like). Alternatively, a native oxide that may be formed on the bottom surface 210 of the semiconductor substrate 210 of each thinned semiconductor die 10 B″ before the formation of the isolation layer 50 . As shown in FIG. 9 , for example, the portions of the conductive vias 230 protruded from the bottom surfaces 210 b of the semiconductor substrates 210 are wrapped around by the second lateral portion 50 b of the isolation layer 50 .

Referring to FIG. 9 and FIG. 10 together, in some embodiments, the isolation layer 50 is partially removed to expose the conductive vias 230 . In such embodiments, the isolation layer 50 is patterned via a planarizing process, where one first lateral portion 50 a and a planarized connecting portion 50 c ′ connected thereto together constitutes one isolation structure 50 ( 0 ), and the second lateral portion 50 b of the isolation layer 50 is planarized to form an isolation layer 240 disposed on the bottom surface 210 b . The planarizing process may include a CMP process or the like, for example. Up to here, the carrier dies 10 B are manufactured. In some embodiments, a thickness T 10 B of the carrier dies 10 B each approximately ranges from 3 μm to 90 μm. In some embodiments, the thickness T 10 B is less than or substantially equal to the thickness T 3 . In the disclosure, the carrier dies 10 B each are referred to as a base tier 10 B( 0 ) for one die stack, in the semiconductor structure P 1 a . It should be noted that various layers and features of the semiconductor dies are omitted from the figures, and the carrier dies 10 B may include more elements formed therein to perform different functions.

In some embodiments, for each carrier die 10 B as shown FIG. 10 , the isolation layer 240 accessibly reveals the conductive vias 230 for further electrical connection. In some embodiments, a thickness T 4 of the isolation layer 240 of the carrier die 10 B approximately ranges from 0.3 μm to 1 μm. After the planarizing process, a cleaning process may be optionally performed, for example to clean and remove the residue generated from the planarizing process. However, the disclosure is not limited thereto, and the planarizing process may be performed through any other suitable method. In some embodiments, during planarizing the isolation layer 50 , the conductive vias 230 may also be planarized. In some embodiments, the thickness T 50 of the isolation layer 50 is greater than or substantially equal to the depth D 1 of the recesses R 1 , and the thickness T 4 of the isolation layer 240 is less than or substantially equal to the depth D 1 of the recesses R 1 .

In some embodiments, a bottom surface 240 b of the isolation layer 240 is substantially levelled with the bottom surfaces 230 b of the conductive vias 230 . That is, the surface 240 b of the isolation layer 240 is substantially coplanar to the bottom surfaces 230 b of the conductive vias 230 . In some embodiments, the portion of each of the conductive vias 230 protruding from the bottom surface 210 b of the semiconductor substrate 210 is laterally covered by the isolation layer 240 , and the bottom surfaces 230 b of the conductive vias 230 are accessibly exposed by the isolation layer 240 , as shown in FIG. 10 . With such planarization, the carrier dies 10 B are formed and separated from one another through the isolation structures 50 ( 0 ), in some embodiments. In the disclosure, the carrier dies 10 B each has the front surface S 3 and a back surface S 4 (e.g., the bottom surface 240 b ), the back surface S 4 is opposite to the front surface S 3 , as shown in FIG. 10 , for example.

Referring to FIG. 11 , in some embodiments, a first set of the semiconductor dies 10 A″ are provided, where these semiconductor dies 10 A″ are stacked on the semiconductor dies 10 B. For example, the semiconductor dies 10 A″ and the carrier dies 10 B are separately fabricated as respectively described in conjunction with FIG. 1 through FIG. 4 and FIG. 5 through FIG. 10 . In some embodiments, the semiconductor dies 10 A″ may be removed from the tape frame TP 1 (shown in FIG. 4 ) to be mounted on the carrier dies 10 B by using, for example, a pick-and-place process or other suitable attaching techniques. The semiconductor dies 10 A″ may be tested before bonding, so that only known good die (KGD) is used for attaching. In the disclosure, the semiconductor dies 10 A″ and the carrier dies 10 B are bonded together in a face-to-back configuration. As shown in FIG. 11 , for example, the front surfaces S 1 of the semiconductor dies 10 A″ face toward the back surfaces S 4 of the carrier dies 10 B, respectively.

For illustrative purposes, only one semiconductor die 10 A″ is disposed on one carrier die 10 B are shown in FIG. 11 ; however, the number of the semiconductor die 10 A″ disposed on one carrier die 10 B is not limited to the disclosure. The number of the semiconductor die 10 A″ may be one or more than one based on the design layout and demand. For example, in alternative embodiments, a plurality of semiconductor die 10 A″ are disposed on one carrier die 10 B underlying thereto (see FIG. 45 ).

In some embodiments, a bonding process is performed to bond the semiconductor dies 10 A″ to the carrier dies 10 B. For example, as shown in FIG. 11 and FIG. 26A (illustrating an enlarged cross-sectional view indicated by the dashed box A of FIG. 11 ), a bonding interface IF 1 between one semiconductor die 10 A″ and a respective underlying carrier die 10 B includes metal-to-metal bonding (e.g., copper-to-copper bonding) and dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding, oxide-to-nitride bonding, or nitride-to-nitride bonding). That is, the bonding process includes a hybrid bonding process. For example, the bonding conductor 150 of the semiconductor die 10 A″ and the conductive via 230 of the carrier die 10 B are bonded together through copper-to-copper bonding (known as a direct metal-to-metal bonding), and the dielectric layer 140 (e.g. the dielectric layer DI 4 ) of the semiconductor die 10 A″ and the isolation layer 240 of the carrier die 10 B are bonded together through oxide-to-nitride bonding (known as a direct dielectrics-to-dielectrics bonding). In the disclosure, the bonding interface IF 1 may be referred to as a hybrid bonding interface.

It should be noted that bonding methods described above are merely examples and are not intended to be limiting. In some embodiments, an offset is between a sidewall 150 SW of the bonding conductor 150 and a sidewall 230 SW of the conductive via 230 underlying thereto, as shown in FIG. 26A . In other words, since the bonding conductor 150 has a larger bonding surface than the conductive vias 230 , direct metal-to-metal bonding may still be achieved even if misalignment occurs, thereby exhibiting better reliability. In some embodiments in which the dimensions of conductive vias 230 are greater than those of corresponding bonding conductors 150 , the dielectric layers 140 of the semiconductor dies 10 A″ immediately adjacent to the bonding conductors 150 may be bonded to a portion of the conductive vias 230 of the carrier dies 10 B.

In some embodiments, the conductive vias 130 may be tapered from the interconnect structure 120 to the bottom surface 110 b ″. Alternatively, for example, as shown in FIG. 11 and FIG. 26A , the conductive vias 130 has substantially vertical sidewalls. In a cross-sectional view along the stacking direction Z, the shape of the conductive vias 130 may depend on the design requirements, and is not intended to be limiting in the disclosure. On the other hand, in a top (plane) view on a X-Y plane, the shape of the conductive vias 130 may depend on the design requirements, and may be a circular shape, an oval shape, a rectangular shape, a polygonal shape, or combinations thereof; the disclosure is not limited thereto. Similar geometric specifications may also applied on the conductive vias 230 of the carrier dies, and thus are not repeated therein.

Each bonding conductor 150 of one semiconductor die 10 A″ distributed at the front surface S 1 is in physical and electrical contact with the respective one conductive via 230 of the semiconductor die 10 B underlying thereto, as shown in FIG. 11 and FIG. 26A , for example. In some embodiments, as illustrated in FIG. 26A , such bonding conductor 150 is in physical and electrical contact with the respective metallization patterns MP overlying thereto. However, the disclosure is not limited thereto; in an alternative embodiment, such bonding conductor 150 may be in physical and electrical contact with a respective conductive pad AP overlying thereto, as illustrated in FIG. 26B .

Referring to FIG. 12 , in some embodiments, the isolation structures 50 ( 0 ) are removed from the temporary carrier TC 2 . For example, the isolation structures 50 ( 0 ) may be removed by etching or the like; the disclosure is not limited thereto. The etching process, for example, may include dry etching, wet etching, or a combination thereof. In one embodiment, during the removal of the isolation structures 50 ( 0 ), the isolation layer 240 of each carrier die 10 B being exposed by the overlying semiconductor die 10 A″ is remained, as shown in FIG. 12 . However, in an alternative embodiment, during the removal of the isolation structures 50 ( 0 ), the isolation layer 240 of each carrier die 10 B being exposed by the overlying semiconductor die 10 A″ may be removed simultaneously.

Referring to FIG. 12 and FIG. 13 together, in some embodiments, the thinning process (e.g., grinding, CMP, or the like) may be performed on the bottom surfaces 110 b ″ of the semiconductor dies 10 A″ to form thinned semiconductor dies 10 A′″. In some embodiments, the conductive vias 130 are exposed by bottom surfaces 110 b ′″ of the thinned semiconductor dies 10 A′″. That is, after bonding the semiconductor dies 10 A″ to the carrier dies 10 B, the semiconductor dies 10 A″ are thinned to form the thinned semiconductor dies 10 A′″ having a thickness T 5 approximately ranging from 40 μm to 200 μm. As shown in FIG. 13 , for example, in each of the thinned semiconductor dies 10 A′″, bottom surfaces 130 b of the conductive vias 130 are accessibly exposed by the bottom surface 110 b ′″ of the semiconductor substrate 110 . For example, in each thinned semiconductor dies 10 A′″, the bottom surfaces 130 b of the conductive vias 130 are substantially levelled with and coplanar to the bottom surface 110 b ′″ of the semiconductor substrate 110 . In each of the thinned semiconductor dies 10 A′″, since the conductive vias 130 extend through the semiconductor substrate 110 , the conductive vias 130 are referred to as through semiconductor vias (TSVs) or through silicon vias when the semiconductor substrate 110 is a silicon substrate.

Referring to FIG. 14 , in some embodiments, the thinned semiconductor dies 10 A′″ are recessed such that the conductive vias 130 are protruded from the semiconductor substrate 110 . In other words, the semiconductor substrate 110 of each of the thinned semiconductor dies 10 A′″ is partially removed to obtain a bottom surface 110 b , and a portion of each of the conductive vias 130 is protrudes out of the bottom surfaces 110 b of the semiconductor substrate 110 . After recessing, in the cross-section shown in FIG. 14 , a plurality of recesses R 2 are formed, where each of the recesses R 2 is formed on the bottom surface 110 b and between the protruded portions of two adjacent conductive vias 130 . The recesses R 2 each has a depth D 2 approximately ranging from 0.5 μm to 1.5 μm (as measured along the stacked direction Z), for example. The recessing process is similar to the process described in conjunction with FIG. 8 , and thus is not repeated herein.

Referring to FIG. 15 , in some embodiments, an isolation layer 51 is formed over the temporary carrier TC 2 . In some embodiments, the isolation layer 51 includes a first lateral portion 51 a , a second lateral portion 51 b and a connecting portion 51 c . For example, as shown in FIG. 15 , the first lateral portion 51 a is disposed on and extends over the temporary bonding layer TB 2 , the second lateral portion 51 b is disposed on and extends over the bottom surfaces 110 b of the semiconductor substrates 110 and the bottom surfaces 130 b and sidewalls 130 s of the conductive vias 130 , and the connecting portion 51 c is disposed on the first lateral portion 51 a and extended to be in contact with the second lateral portion 51 b . In some embodiments, the isolation layer 51 has a thickness T 51 approximately ranging from 0.5 μm to 1.6 μm, where the thickness T 51 is measured with a minimum distance between to opposite sides of the isolation layer 51 . As shown in FIG. 15 , the second lateral portion 51 b fills the recesses R 2 . In one embodiment, the thickness T 51 is greater than the depth D 2 , however the disclosure is not limited thereto. In an alternative embodiment, the thickness T 51 is substantially equal to the depth D 2 . In other words, the isolation layer 51 is thick enough to cover the protruded portion of each of the conductive vias 130 . As shown in FIG. 15 , for example, the portions of the conductive vias 130 protruded from the bottom surface 110 b of the semiconductor substrate 110 are wrapped around by the second lateral portion 51 b of the isolation layer 51 .

In some embodiments, the first lateral portion 51 a and the second lateral portion 51 b are extended laterally, such as along the direction X and/or the direction Y, and the connecting portion 51 c may be extended upwards in a manner of step-form, such as along the stacking direction Z in addition to the direction X and/or the direction Y, as shown in FIG. 15 . The formation and material of the isolation layer 51 may be the same as the forming process of isolation layer 50 as described in FIG. 9 , and thus are not repeated herein. In one embodiment, the thickness T 51 of the isolation layer 51 may be the same as the thickness T 50 of the isolation layer 50 . In an alternative embodiment, the thickness T 51 of the isolation layer 51 may be different from the thickness T 50 of the isolation layer 50 .

Referring to FIG. 15 and FIG. 16 together, in some embodiments, the isolation layer 51 is partially removed to expose the conductive vias 130 . In such embodiments, the isolation layer 51 is planarized, where one first lateral portion 51 a and a planarized connecting portion 51 c ′ connected thereto together constitutes one isolation structure 50 ( 1 ), and the second lateral portion 51 b of the isolation layer 51 is planarized to form an isolation layer 160 disposed on the bottom surface 110 b . The planarized process may include by a CMP process or the like, for example. Up to here, the semiconductor dies 10 A are manufactured. In some embodiments, a thickness T 10 A of the semiconductor dies 10 A approximately ranges from 3 μm to 50 μm. In some embodiments, the thickness T 10 A is less than or substantially equal to the thickness 15 . In the disclosure, the semiconductor dies 10 A are referred to as a first tier 10 A( 1 ) of the die stack, in the semiconductor structure P 1 a . It should be noted that various layers and features of the semiconductor dies are omitted from the figures, and the semiconductor dies 10 A may include more elements formed therein to perform different functions.

In some embodiments, as shown in FIG. 16 , the isolation layer 160 accessibly reveals the conductive vias 130 for further electrical connection. In some embodiments, a thickness T 6 of the isolation layer 160 approximately ranges from 0.3 μm to 1 μm. After the planarizing process, a cleaning process may be optionally performed, for example to clean and remove the residue generated from the planarizing process. However, the disclosure is not limited thereto, and the planarizing process may be performed through any other suitable method. In some embodiments, during planarizing the isolation layer 51 , the conductive vias 130 may also be planarized. In some embodiments, the thickness T 51 of the isolation layer 51 is greater than or substantially equal to the depth D 2 of the recesses R 2 , and the thickness T 6 of the isolation layer 160 is less than or substantially equal to the depth D 2 of the recesses R 2 .

In some embodiments, a bottom surface 160 b of the isolation layer 160 is substantially levelled with the bottom surfaces 130 b of the conductive vias 130 . That is, the surface 160 b of the isolation layer 160 is substantially coplanar to the bottom surfaces 130 b of the conductive vias 130 . In some embodiments, the portion of each of the conductive vias 130 protruding from the bottom surface 110 b of the semiconductor substrate 110 is laterally covered by the isolation layer 160 , and the bottom surfaces 130 b of the conductive vias 130 are accessibly exposed by the isolation layer 160 , as shown in FIG. 16 . With such planarization, the semiconductor dies 10 A are formed and separated from one another through the isolation structures 50 ( 1 ), in some embodiments. In the disclosure, the semiconductor dies 10 A each has the front surface S 1 and a back surface S 2 (e.g., the bottom surface 160 b ), the back surface S 2 is opposite to the front surface S 1 , as shown in FIG. 16 , for example. That is, for example, the front surfaces S 1 of the semiconductor dies 10 A (e.g. the first tier 10 A( 1 ) of the die stack) face toward and are bonded to the back surfaces S 4 of the carrier dies 10 B (e.g. the base tiers 10 B( 0 ) for the die stacks), respectively.

Referring to FIG. 17 , in some embodiments, a second set of the semiconductor dies 10 A″ are provided, and these semiconductor dies 10 A″ are respectively stacked on the semiconductor dies 10 A of the first tier 10 A( 1 ). In the disclosure, each semiconductor die 10 A″ (from the second set) is disposed on one of the semiconductor dies 10 A of the first tier 10 A( 1 ) in a face-to-back configuration for forming a second tier (e.g. 10 A( 2 ) depicted in FIG. 18 ) of the die stack. For example, the front surfaces S 1 of the semiconductor dies 10 A″ (from the second set) face toward the back surfaces S 2 of the semiconductor dies 10 A of the first tier 10 A( 1 ), respectively. Similar to the process as described in FIG. 11 , before removing from the tape frame TP 1 (shown in FIG. 4 ) to be mounted on the semiconductor dies 10 A of the first tier 10 A( 1 ), the semiconductor dies 10 A″ may be tested before bonding, so that only known good die (KGD) is used for attaching.

In some embodiments, a bonding process is performed, via hybrid bonding, to bond the semiconductor dies 10 A″ to the semiconductor dies 10 A. For example, as shown in FIG. 17 and FIG. 27A (illustrating an enlarged cross-sectional view indicated by the dashed box B of FIG. 17 ), a bonding interface IF 2 between one semiconductor die 10 A″ and a respective underlying semiconductor dies 10 A includes metal-to-metal bonding (e.g., copper-to-copper bonding) and dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding, oxide-to-nitride bonding, or nitride-to-nitride bonding). For example, the bonding conductor 150 of the semiconductor die 10 A″ and the conductive via 130 of the semiconductor die 10 A are bonded together through copper-to-copper bonding (known as a direct metal-to-metal bonding), and the dielectric layer 140 (e.g. the dielectric layer DI 4 ) of the semiconductor die 10 A″ and the isolation layer 160 of the semiconductor dies 10 A are bonded together through oxide-to-nitride bonding (known as a direct dielectrics-to-dielectrics bonding). In the disclosure, the bonding interface IF 2 may be referred to as a hybrid bonding interface.

It should be noted that bonding methods described above are merely examples and are not intended to be limiting. As shown in FIG. 27A , for example, an offset is between a sidewall 150 SW of the bonding conductor 150 and a sidewall 130 SW of the conductive via 130 underlying thereto. In other words, since the bonding conductor 150 has a larger bonding surface than the conductive vias 130 , direct metal-to-metal bonding may still be achieved even if misalignment occurs, thereby exhibiting better reliability. In some embodiments in which the dimensions of conductive vias 130 are greater than those of corresponding bonding conductors 150 , the dielectric layers 140 of the semiconductor dies 10 A″ immediately adjacent to the bonding conductors 150 may further be bonded to a portion of the conductive vias 130 of the semiconductor dies 10 A, such as a metal-to-dielectrics bonding.

Each bonding conductor 150 of one semiconductor die 10 A″ distributed at the front surface S 1 is in physical and electrical contact with the respective one conductive via 130 of the semiconductor die 10 A underlying thereto, for example, as shown in FIG. 17 and FIG. 27A . In some embodiments, as illustrated in FIG. 27A , such bonding conductor 150 is in physical and electrical contact with the respective metallization patterns MP overlying thereto. However, the disclosure is not limited thereto; in an alternative embodiment, such bonding conductor 150 may be in physical and electrical contact with a respective conductive pad AP overlying thereto, see FIG. 27B .

Referring to FIG. 18 , in some embodiments, the steps described in FIG. 12 through FIG. 17 are repeated to form the die stacks 100 over the carrier dies 10 B of the base tiers 10 B( 0 ). As shown in FIG. 18 , each die stack 100 is located on one carrier die 10 B underlying thereto. In some embodiments, the die stacks 100 each include a topmost tier 10 A(T), where the topmost tier 10 A(T) includes the semiconductor die 10 A″ depicted in FIG. 4 . It should be appreciated that the symbol T indicates the number of tiers for each die stack 100 , and the die stacks 100 respectively disposed on the base tiers 10 B( 0 ) each may include any number of tiers. For example, T is an integer greater than 1. For example, as shown in FIG. 18 , the semiconductor die 10 A″ has the conductive vias 130 not be revealed. In some embodiments, the semiconductor die 10 A″ of the topmost tier 10 A(T) is thicker than any one of the underlying semiconductor dies 10 A of the inner tiers (e.g. 10 A( 1 ) to 10 A(T−1)) in each of the die stacks 100 . For example, the thickness T 2 of the semiconductor die 10 A″ of the topmost tier 10 A(T) is greater than the thickness T 10 A of one tier of the other semiconductor dies 10 A of the inner tiers (e.g. 10 A( 1 ) to 10 A(T−1)).

For example, in each die stack 100 , the semiconductor dies 10 A at the second tier 10 A( 2 ) is fabricated by performing the method described in conjunction with FIG. 13 to FIG. 16 on the structure depicted in FIG. 17 , and thus the semiconductor dies 10 A at the first tier 10 A( 1 ) and at the second tier 10 A( 2 ) may be similar or the same in configurations, functions, and properties. That is, the semiconductor dies 10 A at the first tier 10 A( 1 ) through the (T−1)th tier 10 A(T−1) of each die stack 100 may be similar or the same in configurations, functions, and properties due to the similar forming steps are utilized. For example, the die stacks 100 each have a sidewall 100 S with a flat surface. In some embodiments, along the direction X, a width W 10 B of each carrier die 10 B is greater than a width W 100 of (each semiconductor dies 10 A/ 10 A″ of) each die stack 100 . As shown in FIG. 18 , in some embodiments, an offset is between the sidewall 100 S of one die stack 100 and a sidewall S 5 of the carrier dies 10 B underlying thereto.

In some embodiments, the semiconductor dies (e.g., 10 A and 10 A″) of the tiers (e.g., the inner tiers such as 10 A( 1 )/ 10 A( 2 ) . . . 10 A(T−1) and the topmost tier 10 A(T)) may be tested before bonding, so that only known good dies (KGDs) are used to form the die stacks 100 , thereby increasing manufacturing yield. In some embodiments in which the semiconductor dies (e.g., 10 A and 10 A″) are memory dies, since the semiconductor dies stacked and bonded vertically, faster inter-memory communication may be achieved by the die stacks 100 during operation, which in turn may improve data bandwidth and enable faster data access and data storage. In some embodiments, during operation, the semiconductor die at the first tier 10 A( 1 ) may help to manage data storage and data format interoperability between the respective semiconductor dies at the other tiers (e.g., 10 A( 2 ) through 10 A(T−1) and 10 A(T)) stacked thereon and/or the carrier die 10 B at the base tier 10 B( 0 ).

In some embodiments, the semiconductor dies (e.g., 10 A and 10 A″) of the die stacks 100 are stacked and bonded vertically by hybrid bonding. For example, for every two adjacent tiers of one die stack 100 , the upper tier is bonded to the lower tier in a face-to-back configuration. In some embodiments, as shown in FIG. 18 , the front surface S 1 of the second tier 10 A( 2 ) is bonded to the back surface S 2 of the first tier 10 A( 1 ). By such bonding (without uses of any other external connectors), there is no gap between the dies at two adjacent stacked tiers, therefore the semiconductor structure P 1 a having a better form factor with a die stack of a higher density in devices is achieved. As shown in FIG. 18 , for example, the die stacks 100 are separated and isolated from each other by the isolation structures 50 (T−1), and the carrier dies 10 B are also separated and isolated from each other by the isolation structures 50 (T−1).

Referring FIG. 19 , in some embodiments, the isolation structures 50 (T−1) are removed from the temporary carrier TC 2 . For example, the isolation structures 50 (T−1) may be removed by etching or the like; the disclosure is not limited thereto. The etching process is similar to the step as described in FIG. 12 , and thus is not repeated herein. That is, for example, the die stacks 100 are separated and isolated from each other by gaps, and the carrier dies 10 B are also separated and isolated from each other by the gaps.

As illustrated in FIG. 19 and FIG. 28A (illustrating an enlarged cross-sectional view indicated by the dashed box C of FIG. 19 ), at least one of the semiconductor substrates 110 of the semiconductor dies 10 A in the inner tiers (e.g. 10 A( 1 ) through 10 A(T−1)) may have a rounded edge RE. For example, for each of the semiconductor dies 10 A, the rounded edge RE is connected to the bottom surface 110 b and the sidewall 110 s of the semiconductor substrate 110 . In some embodiments, the dielectric layer 140 of the semiconductor die 10 A at the second tier 10 A( 2 ) is a substantially flat surface so that a gap is formed between the rounded edge RE of the semiconductor die 10 A at the first tier 10 A( 1 ) and the dielectric layer 140 of the semiconductor die 10 A at the second tier 10 A( 2 ). With such embodiment, the gap may be, in a sequential step, filled by a later-formed layer/element, such as a dielectric layer, a conductive layer, or a layer having at least one dielectric layer and at least one conductive layer. That is, the rounded edge RE may be covered by the later-formed layer/element. The disclosure is not limited thereto. In alternative embodiments, the gap may not be filled, and the rounded edge RE may not be covered by any layers/elements. In some embodiments, the rounded edge RE is created during the backside thinning process (e.g., the step described in conjunction with FIG. 13 ). For example, the grinding pad, which is contact with the edges of the semiconductor dies, makes the edges of the semiconductor dies rounded. By forming the rounded edges RE, the semiconductor dies 10 A may spread out the stress in the edge/corner area caused by mechanical/thermal stress and by bonding, thereby preventing cracking.

In other embodiments, as illustrated in FIG. 28B , the rounded edge RE may be substituted by a bevel edge BE, where the bevel edge BE is connected to the bottom surface 110 b and the sidewall 110 s of the semiconductor substrate 110 . In some embodiments, the dielectric layer 140 of the semiconductor die 10 A at the second tier 10 A( 2 ) is a substantially flat surface so that a gap is formed between the bevel edge BE of the semiconductor die 10 A at the first tier 10 A( 1 ) and the dielectric layer 140 of the semiconductor die 10 A at the second tier 10 A( 2 ). With such embodiment, the gap may be, in a sequential step, filled by a later-formed layer/element, such as a dielectric layer, a conductive layer, or a layer having at least one dielectric layer and at least one conductive layer. That is, the bevel edge BE may be covered by the later-formed layer/element. However, in alternative embodiments, the gap may not be filled, and the bevel edge BE may not be covered by any layers/elements. In some embodiments, the bevel edge BE is created by singulation marks formed at the scribe lines for the singulation process (e.g., the step described in conjunction with FIG. 4 ). For example, the singulation marks, which are used to indicate the boundaries of the semiconductor dies, makes the edges of the semiconductor dies bevel. By forming the bevel edge BE, the semiconductor dies 10 A may spread out the stress in the edge/corner area caused by mechanical/thermal stress and by bonding, thereby preventing cracking.

In further other embodiments, as illustrated in FIG. 28C , the bottom surface 110 b and the sidewall 110 s of the semiconductor substrate 110 may be connected directly at a sharp edge SE. In such embodiments, there is no gap being formed between the sharp edge SE of the semiconductor die 10 A at the first tier 10 A( 1 ) and the dielectric layer 140 of the semiconductor die 10 A at the second tier 10 A( 2 ). In some embodiments, the sharp edge SE may or may not be covered by any layers/elements.

As illustrated in FIG. 19 and FIG. 29A (illustrating an enlarged cross-sectional view indicated by the dashed box D of FIG. 19 ), the semiconductor substrate 110 of the semiconductor die 10 A″ at the topmost tier 10 A(T) may have the bevel edge BE. For example, for the semiconductor die 10 A″, the bevel edge BE is connected to the bottom surface 110 b ″ and the sidewall 110 s of the semiconductor substrate 110 . With such embodiment, the bevel edge BE may be, in a sequential step, covered by a later-formed layer/element, such as a dielectric layer, a conductive layer, or a layer having at least one dielectric layer and at least one conductive layer. The disclosure is not limited thereto. In alternative embodiments, the bevel edge BE may not be covered by any layers/elements.

However, the disclosure is not limited thereto. In other embodiments, as illustrated in FIG. 29B , the bottom surface 110 b ″ and the sidewall 110 s of the semiconductor substrate 110 may be connected directly at a sharp edge SE. In some embodiments, the sharp edge SE may or may not be covered by any layers/elements.

Referring to FIG. 20 , in some embodiments, an electromagnetic interference shielding material 60 A is disposed over the temporary carrier TC 2 to be disposed on the die stacks 100 and the carrier dies 10 B of the base tiers 10 B( 0 ). In some embodiments, the electromagnetic interference shielding material 60 A covers the die stacks 100 and the carrier dies 10 B of the base tiers 10 B( 0 ) in conformal manner. In some embodiments, the electromagnetic interference shielding material 60 A has a thickness T 60 approximately ranging from 500 Å to 5000 Å, where the thickness T 60 is measured with a minimum distance between to opposite sides of the electromagnetic interference shielding material 60 A. For example, the electromagnetic interference shielding material 60 A at least covers the sidewalls 100 S and bottom surfaces 100 b of the die stacks 100 and further covers the sidewalls S 5 and portions of the back surfaces S 4 of the carrier dies 10 B of the base tiers 10 B( 0 ).

In some embodiments, the electromagnetic interference shielding material 60 A may be made of an electrically conductive material. Materials used for the electromagnetic interference shielding material 60 A may include copper, nickel, an alloy of nickel and iron, an alloy of copper and nickel, silver, etc., but not limited thereto. In some embodiments, the electromagnetic interference shielding material 60 A may be fabricated by using an electrolytic plating, electroless plating, sputtering, physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), or other suitable metal deposition process. A patterning process may be optionally performed to expose portions of the temporary bonding layer TB 2 , if need. The patterning process may include an etching process, such as dry etching, wet etching, or a combination thereof.

Referring to FIG. 21 , in some embodiments, after forming the electromagnetic interference shielding material 60 A, an insulating material 20 ′ is formed over the temporary carrier TC 2 to encapsulate the electromagnetic interference shielding material 60 A, the die stacks 100 and the carrier dies 10 B. For example, the insulating material 20 ′ may be a molding compound, an epoxy resin, the like, or other suitable electrically insulating materials, and may be applied by compression molding, transfer molding, or the like. In some embodiments, the electromagnetic interference shielding material 60 A, the die stacks 100 and the carrier dies 10 B are over-molded, and then the insulating material 20 ′ is thinned to reduce the overall thickness of the structure by using, for example, grinding, chemical mechanical polishing (CMP), combinations thereof, or other suitable thinning process. For example, the bottom surfaces 100 b of the die stacks 100 (e.g., the bottom surfaces 110 b ″ of the semiconductor dies 10 A″) are exposed by the insulating material 20 ′ after thinning.

In some embodiments, during thinning the insulating material 20 ′, the electromagnetic interference shielding material 60 A is also be patterned to form an electromagnetic interference shielding layer 60 . In certain embodiments, the thinning step may be, for example, performed on the over-molded insulating material 20 ′ to level a surface 20 b of the insulating material 20 ′, the bottom surfaces 100 b of the die stacks 100 (e.g. the bottom surfaces 110 b ″ of the semiconductor dies 10 A″), and a surface S 60 of the electromagnetic interference shielding layer 60 . For example, the surface 20 b of the insulating material 20 ′, the bottom surfaces 100 b of the die stacks 100 (e.g. the bottom surfaces 110 b ″ of the semiconductor dies 10 A″) and the surface S 60 of the electromagnetic interference shielding layer 60 are substantially levelled with each other. In other words, the surface 20 b of the insulating material 20 ′ is substantially coplanar to the bottom surfaces 100 b of the die stacks 100 (e.g. the bottom surfaces 10 b ″ of the semiconductor dies 10 A″) and the surface S 60 of the electromagnetic interference shielding layer 60 . As shown in FIG. 21 , for example, the electromagnetic interference shielding layer 60 does not extend on the bottom surfaces 100 b of the die stacks 100 (e.g. the bottom surfaces 110 b ″ of the semiconductor dies 10 A″), and the carrier dies 10 B and the die stacks 100 disposed thereon are separated from the insulating material 20 ′ through the electromagnetic interference shielding layer 60 .

The insulating material 20 ′ may include a low moisture absorption rate and may be rigid after solidification for protecting the electromagnetic interference shielding layer 60 , the die stacks 100 and the carrier dies 10 B. The electromagnetic interference shielding layer 60 is used for reducing or inhibiting the electromagnetic field in a space by blocking the field with barriers made of conductive or magnetic materials. The electromagnetic interference shielding layer 60 in some embodiments may reduce the coupling of, for example, radio waves, electromagnetic fields and electrostatic fields. In some embodiment, the electromagnetic interference shielding layer 60 may be in electrical contact with a ground (not shown) for being electrically grounded.

In some embodiments, during thinning the insulating material 20 ′, the semiconductor substrate 110 of the semiconductor dies 10 A″ may also be patterned, the disclosure is not limited thereto. In other embodiments, the thinning process may be omitted, and the electromagnetic interference shielding material 60 A, the die stacks 100 and the carrier dies 10 B are buried or covered by the insulating material 20 ′. In such embodiments, the electromagnetic interference shielding material 60 A serves as the electromagnetic interference shielding layer, and is in electrical contact with a ground (not shown) for being electrically grounded.

Referring to FIG. 22 , in some embodiments, another temporary carrier TC 3 is optionally attached to the insulating material 20 ′ opposite to the temporary carrier TC 2 . In some embodiments in which the insulating material 20 ′ is thinned to expose the semiconductor dies 10 A″ at the topmost tier 10 A(T), the temporary carrier TC 3 is, via an temporary bonding layer TB 3 , bonded to the insulating material 20 ′ (e.g. the surface 20 b ) and the bottom surfaces 100 b of the die stack 100 (e.g., the bottom surface 110 b ″ of the semiconductor dies 10 A″). A de-bonding process may be performed, where the temporary carrier TC 2 and the temporary bonding layer TB 2 are released from the carrier dies 10 B at the base tiers 10 B( 0 ) such that the front surfaces S 3 of the carrier dies 10 B and a surface 20 a of the insulating material 20 ′ are exposed. For example, along the stacking direction Z, the surface 20 a of the insulating material 20 ′ is opposite to the surface 20 b of the insulating material 20 ′. In some embodiments, the front surfaces S 3 of the carrier dies 10 B are cleaned after de-bonding the temporary carrier TC 2 for further processing. The de-bonding process has been described in FIG. 4 , and thus is not repeated herein for simplicity.

Referring to FIG. 23 , in some embodiments, after removing the temporary carrier TC 2 and the temporary bonding layer TB 2 , a plurality of conductive terminals 30 are subsequently formed at the exposed front surfaces S 3 of the carrier dies 10 B. The conductive terminals 30 may be formed by using, for example, a sputtering, printing, plating, deposition, or the like. The conductive terminals 30 may be formed of conductive material(s) including copper, aluminum, gold, nickel, silver, palladium, tin, solder, metal alloy, the like, or combinations thereof. For example, each of the conductive terminals 30 includes a bump 31 . The bump 31 may be a micro-bump, a metal pillar, an electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bump, a controlled collapse chip connection (C4) bump, a ball grid array (BGA) bump, or the like. In an embodiment in which the bumps 31 are micro-bumps, a bump pitch between two adjacent bumps 31 ranges from about 35 μm to about 55 μm. The bumps 31 may be solder free and may have substantially vertical sidewalls. In some embodiments, each of the conductive terminals 30 includes a metal cap 32 formed on the top of the bump 31 by, for example, plating, printing, or the like. For example, a material of the metal caps 32 includes nickel, tin, tin-lead, gold, silver, palladium, nickel-palladium-gold, nickel-gold, the like, or any combination of these.

In some embodiments, before forming the conductive terminals 30 , a protection layer 70 is formed at the base tiers 10 B( 0 ) of the die stacks 100 , as shown in FIG. 23 . In some embodiments, the protection layer 70 is disposed on the carrier dies 10 B and the insulating material 20 ′, and extends to cover up the front surfaces S 3 of the carrier dies 10 B and the surface 20 a of the insulating material 20 ′. In other words, the protection layer 70 is in contact with the insulating material 20 ′ and the carrier dies 10 B. For example, the protection layer 70 includes passivation materials such as silicon oxide, silicon nitride, un-doped silicate glass, polyimide, or other suitable insulating materials for protection the underlying structures. In some embodiments, the protection layer 70 includes a plurality of openings OP exposing at least a portion of the underlying conductive features (not illustrated) in the interconnect structure 220 of each of the carrier dies 10 B for further electrical connection. For example, as shown in FIG. 23 , the conductive terminals 30 are formed to be in physical and electrical contact with the conductive features in the interconnect structures 220 of the carrier dies 10 B exposed by the openings OP formed in the protection layer 70 .

Alternatively, the protection layer 70 may be omitted, the disclosure is not limited thereto. In such embodiments, the conductive terminals 30 are directly formed on the carrier dies 10 B to be in physical and electrical contact with the conductive features in the interconnect structures 220 of the carrier dies 10 B.

Alternatively, the protection layer 70 may be substituted with a redistribution circuit structure (not shown) including one or more than one dielectric layer and one or more than one metallization layer arranged in alternation. In such embodiments, the conductive terminals 30 are formed on the redistribution circuit structure to be in electrical contact with the conductive features in the interconnect structures 220 of the carrier dies 10 B through the metallization layer(s) in the redistribution circuit structure.

Referring to FIG. 24 , in some embodiments, the temporary carrier TC 3 and the temporary bonding layer TB 3 are removed from the insulating material 20 ′ and the die stacks 100 by de-bonded process. For example, the de-bonding process includes applying energy to the temporary bonding layer, mechanical peeling, etching, or other suitable removal techniques. Subsequently, a singulation process is performed to form a plurality of separated and individual semiconductor structures P 1 a . The singulation may be performed along the scribe lines (not shown) by, for example, a sawing, laser cutting, or the like. The insulating material 20 ′ may be cut through to form an insulating encapsulation 20 . The insulating encapsulation 20 exposes the bottom surface 100 b of the die stack 100 exposed by the electromagnetic interference shielding layer 60 , and is disposed at the sidewall 100 S of the die stack 100 and the sidewall S 5 and a portion of the back surface S 4 of the carrier die 10 C covered by the electromagnetic interference shielding layer 60 .

In some embodiments, as shown in FIG. 24 , the semiconductor structure P 1 a has the carrier die 10 B, the die stack 100 disposed thereon, the insulating encapsulation 20 formed on the carrier die 10 B and the die stack 100 , the electromagnetic interference shielding layer 60 sandwiched between the insulating encapsulation 20 and the carrier die 10 B and between the insulating encapsulation 20 and the die stack 100 , the protection layer 70 disposed on the carrier die 10 B and the insulating encapsulation 20 , and the conductive terminals 30 disposed on the insulating encapsulation 20 . In some embodiments, the carrier die 10 B is, for example, a logic die configured to perform read, program, erase, and/or other operations, and the die stack 100 is, for example, a memory stack including memory dies stacked upon one another and programmed by the carrier die 10 B. In certain embodiments, the semiconductor structure P 1 a is referred to as a (semiconductor) device package. For example, the semiconductor dies 10 A/ 10 A″ in the die stack 100 of the semiconductor structure P 1 a may be high bandwidth memory (HBM) dies, and the carrier die 10 B may be a logic die providing control functionality for these memory dies. In other words, the semiconductor dies 10 A/ 10 A″ in the die stack 100 and the carrier die 10 B are bonded together through hybrid bonding, and are electrically connected and electrically communicated to each other. Other types of dies may be employed in the semiconductor structure P 1 a depending on the product requirements. In the disclosure, the die stack 100 and the carrier die 10 B together are referred to as a stacked structure SS 1 .

In some embodiments, the sidewall S 5 of the carrier die 10 B covered by the electromagnetic interference shielding layer 60 is further covered by the insulating encapsulation 20 after singulation. For example, a sidewall 20 S of the insulating encapsulation 20 may be substantially leveled with a sidewall 70 S of the protection layer 70 after singulation. That is, the sidewall 20 S of the insulating encapsulation 20 is aligned with the sidewall 70 S of the protection layer 70 . The sidewall 100 S of the die stack 100 is distant from the sidewall 20 S of the insulating encapsulation 20 , and the sidewall S 5 of the carrier die 10 B is also distant from the sidewall 20 S of the insulating encapsulation 20 , as shown in FIG. 24 , in some embodiments.

As illustrated in FIG. 24 and FIG. 25 (a top plane view on the X-Y plane), for the semiconductor structure P 1 a , a positioning location of the die stack 100 is within a positioning location of the carrier die 10 B and within a positioning location of the insulating encapsulation 20 , and the positioning location of the carrier die 10 B is within the positioning location of the insulating encapsulation 20 . In other words, a perimeter of the die stack 100 is less than a perimeter of the carrier die 10 B and a perimeter of the insulating encapsulation 20 , and the perimeter of the carrier die 10 B is less than the perimeter of the insulating encapsulation 20 .

However, the disclosure is not limited thereto. FIG. 30 through FIG. 44 are schematic cross-sectional views respectively showing a semiconductor structure in accordance with some embodiments of the disclosure. Like elements are designated with the same reference numbers for ease of understanding and the details thereof are not repeated herein.

In alternative embodiments, an additional insulating encapsulation may be included. A semiconductor structure P 1 b depicted in FIG. 30 is similar to the semiconductor structure P 1 a depicted in FIG. 24 , the difference is that, the semiconductor structure P 1 b further includes an insulating encapsulation 40 . For example, as shown in FIG. 30 , the insulating encapsulation 40 is at least located between the protection layer 70 and the insulating encapsulation 20 . In some embodiments, the insulating encapsulation 40 is formed prior to the formation of the insulating encapsulation 20 , such that the sidewall S 5 of the carrier die 10 B covered by the electromagnetic interference shielding layer 60 is further covered by the insulating encapsulation 40 . For example, the insulating encapsulation 40 not only further covers the portion of the back surface S 4 of the carrier die 10 B exposed by the die stack 100 and covered by the electromagnetic interference shielding layer 60 , but also covers a portion of the sidewall 100 S of the die stack 100 covered by the electromagnetic interference shielding layer 60 . That is, the insulating encapsulation 40 is further partially located between the insulating encapsulation 20 and the carrier die 10 B. As shown in FIG. 30 , for example, the sidewall 20 S of the insulating encapsulation 20 and the sidewall 70 S of the protection layer 70 are substantially coplanar to and aligned with a sidewall 40 S of the insulating encapsulation 40 .

In some embodiments, the insulating encapsulation 40 may be conformally formed by, for example, spin-coating, deposition or the like. In some embodiments, a material of the insulating encapsulation 40 may include a nitride (such as silicon nitride), an oxide (such as silicon oxide) or the like (such as, silicon oxynitride, silicon carbide, a polymer, the like). The disclosure is not specifically limited. In the disclosure, the insulating encapsulation 40 is different from the insulating encapsulation 20 .

In further alternative embodiment, the insulating encapsulation 20 is substituted by the insulating encapsulation 40 , see a semiconductor structure Plc depicted in FIG. 31 . A semiconductor structure Plc depicted in FIG. 31 is similar to the semiconductor structure P 1 a depicted in FIG. 24 , the difference is that, the semiconductor structure P 1 c employs the insulating encapsulation 40 instead of the insulating encapsulation 20 . For example, the insulating encapsulation 40 completely covers the electromagnetic interference shielding layer 60 . As shown in FIG. 31 , for example, the sidewall 70 S of the protection layer 70 is substantially coplanar to and aligned with the sidewall 40 S of the insulating encapsulation 40 .

In other alternative embodiments, there is no insulating encapsulation (e.g. 20 , 40 ), see a semiconductor structure P 1 d depicted in FIG. 32 . A semiconductor structure P 1 d depicted in FIG. 32 is similar to the semiconductor structure P 1 a depicted in FIG. 24 , the difference is that, the die stack 100 and the carrier die 10 B are only covered by the electromagnetic interference shielding layer 60 . As shown in FIG. 32 , for example, the sidewall 70 S of the protection layer 70 is substantially coplanar to and aligned with a side of a portion of the electromagnetic interference shielding layer 60 located on the sidewall S 5 of the carrier die 10 B.

In some embodiments, as compared with the semiconductor structures P 1 a through P 1 d , an isolation structure (e.g. 50 (T−1) depicted in FIG. 18 ) may be included in semiconductor structures P 2 a through P 2 d respectively depicted in FIG. 33 through FIG. 36 . For example, the semiconductor structure P 2 a depicted in FIG. 33 is similar to the semiconductor structure P 1 a depicted in FIG. 24 , the difference is that, in the semiconductor structure P 2 a , the isolation structures 50 (T−1) is remained on the carrier die 10 B and the die stack 100 . As shown in FIG. 33 , a portion of the sidewall 100 S of the die stack 100 , the sidewall S 5 of the carrier die 10 B and the back surface S 4 of the carrier die 10 B exposed by the die stack 100 are covered by the isolation structure 50 (T−1). For example, the isolation structure 50 (T−1) is located between the die stack 100 /the carrier die 10 B and the insulating encapsulation 20 . As illustrated in FIG. 33 , the protection layer 70 is located on the carrier die 10 B, the isolation structure 50 (T−1), the electromagnetic interference shielding layer 60 and the insulating encapsulation 20 , and the sidewalls of the inner tiers (e.g. 10 A( 1 ) through 10 A(T−1) are covered by the isolation structure 50 (T−1). Similarly, the isolation structure may also be introduced to the semiconductor structures P 1 b , P 1 c and P 1 d to respectively form semiconductor structures P 2 b , P 2 c and P 2 d , as shown in FIG. 34 to FIG. 36 .

On the other hand, in some embodiments, as compared with the semiconductor structures P 2 a through P 2 d , an electromagnetic interference shielding element (e.g. 60 or 60 A) may be excluded in semiconductor structures P 3 a through P 3 d respectively depicted in FIG. 37 through FIG. 40 .

In some embodiments, as compared with the semiconductor structures P 1 a through P 1 d , no electromagnetic interference shielding element (e.g. 60 or 60 A) may be included in semiconductor structures P 4 a through P 4 d respectively depicted in FIG. 41 through FIG. 44 . The semiconductor structure P 4 a depicted in FIG. 41 is similar to the semiconductor structure P 1 a depicted in FIG. 24 , the difference is that, in the semiconductor structure P 4 a , the electromagnetic interference shielding layer 60 is removed from the carrier die 10 B and the die stack 100 . As shown in FIG. 41 , the sidewall 100 S of the die stack 100 , the sidewall S 5 of the carrier die 10 B and the back surface S 4 of the carrier die 10 B exposed by the die stack 100 are in physical contact with the insulating encapsulation 20 . Similarly, the electromagnetic interference shielding element may also be removed from the semiconductor structures P 1 b , P 1 c and P 1 d to respectively form semiconductor structures P 4 b , P 4 c and P 4 d , as shown in FIG. 41 to FIG. 44 .

FIG. 45 is a schematic cross-sectional view showing a semiconductor structure in accordance with some embodiments of the disclosure. FIG. 46A and FIG. 46B are schematic top views respectively illustrating a relative position between a semiconductor die, a carrier die and an insulating encapsulation of a semiconductor structure in accordance with some embodiments of the disclosure. Like elements are designated with the same reference numbers for ease of understanding and the details thereof are not repeated herein. For example, FIG. 45 is the schematic cross-sectional view of a semiconductor structure P 5 taken along a cross-sectional line II-II depicted in FIG. 46A .

The semiconductor structure P 5 depicted in FIG. 41 is similar to the semiconductor structure P 1 a depicted in FIG. 24 , the difference is that, in the semiconductor structure P 4 a , a plurality of the die stacks 100 are disposed on one base tier 10 B( 0 ). In other words, in the semiconductor structure P 5 , multiple semiconductor dies (e.g. 10 A and 10 A″) are disposed on one carrier die 10 B. In some embodiments, through the hybrid bonding, the die stacks 100 are bonded to the carrier die 10 B at the base tier 10 B( 0 ) in a face-to-back configuration. In the disclosure, the die stacks 100 and the carrier die 10 B together are referred to as a stacked structure SS 2 .

As illustrated in FIG. 45 and FIG. 46A , for example, the die stacks 100 are arranged in a matrix form on the carrier die 10 B, such as the N×N or N×M arrays (N, M>0, N may or may not be equal to M). The size of the array for the die stacks 100 can be designated and selected based on the demand, and is not limited to the disclosure. In some embodiment, the die stacks 100 are arranged into a 1×3 array depicted in FIG. 46A . However, the disclosure is not limited thereto; in an alternative embodiment, the die stacks 100 may be arranged into a 2×2 array depicted in FIG. 46B .

In some embodiments, for the semiconductor structure P 5 , positioning locations of the die stacks 100 are within a positioning location of the carrier die 10 B and within a positioning location of the insulating encapsulation 20 , and the positioning location of the carrier die 10 B is within the positioning location of the insulating encapsulation 20 . In other words, the carrier die 10 B and the insulating encapsulation 20 are overlapped with the die stacks 100 arranged side-by-side.

FIG. 47 is a schematic cross-sectional view showing a semiconductor structure in accordance with some embodiments of the disclosure. FIG. 48A and FIG. 48B are schematic top views respectively illustrating a relative position between a semiconductor die, a carrier die and an insulating encapsulation of a semiconductor structure in accordance with some embodiments of the disclosure. Like elements are designated with the same reference numbers for ease of understanding and the details thereof are not repeated herein. For example, FIG. 47 is the schematic cross-sectional view of a semiconductor structure P 6 taken along a cross-sectional line depicted in FIG. 48A .

The semiconductor structure P 6 depicted in FIG. 47 is similar to the semiconductor structure P 1 a depicted in FIG. 24 , the difference is that, the semiconductor structure P 4 a includes multiple stacked structures SS 1 (depicted in FIG. 24 ). As illustrated in FIG. 47 and FIG. 48A , for example, the stacked structures SS 1 are arranged side-by-side in a matrix form in the, such as the N×N or N×M arrays (N, M>0, N may or may not be equal to M). The size of the array for the stacked structures SS 1 can be designated and selected based on the demand, and is not limited to the disclosure. In some embodiment, the stacked structures SS 1 are arranged into a 1×3 array depicted in FIG. 48A . However, the disclosure is not limited thereto; in an alternative embodiment, the stacked structures SS 1 may be arranged into a 2×2 array depicted in FIG. 48B .

As illustrated in FIG. 47 and FIG. 48 (a top plane view on the X-Y plane), for the semiconductor structure P 6 , a positioning location of each die stack 100 is within a positioning location of each carrier die 10 B and within a positioning location of the insulating encapsulation 20 , and the positioning location of each carrier die 10 B is within the positioning location of the insulating encapsulation 20 . In other words, a perimeter of each die stack 100 is less than a perimeter of each carrier die 10 B and a perimeter of the insulating encapsulation 20 , and the perimeter of each carrier die 10 B is less than the perimeter of the insulating encapsulation 20 .

In addition, the stacked structures SS 1 may be replaced with the stacked structure SS 2 depicted in FIG. 45 , in part or all. The disclosure is not limited thereto.

FIG. 49 through FIG. 56 are schematic cross-sectional views showing various stages in a manufacturing method of a semiconductor structure in accordance with some embodiments of the disclosure. FIG. 57 is a schematic top view illustrating a relative position between a semiconductor die, a carrier die and an insulating encapsulation of a semiconductor structure in accordance with some embodiments of the disclosure. For example, FIG. 49 is the schematic cross-sectional view of a semiconductor structure P 7 taken along a cross-sectional line IV-IV depicted in FIG. 57 . Like elements are designated with the same reference numbers for ease of understanding and the details thereof are not repeated herein.

Referring to FIG. 49 , in some embodiments, a semiconductor wafer W 2 is provided. In some embodiments, the semiconductor wafer W 2 includes a plurality of semiconductor dies 10 B′ connected to one another. The details of the semiconductor dies 10 B′ have been described in FIG. 5 , thus is not repeated herein for simplicity. For example, each of the semiconductor dies 10 B′ may include an integrated circuit device (e.g., a logic die, a memory die, a radio frequency die, a power management die, a micro-electro-mechanical-system (MEMS) die, the like, or combinations of these).

Referring to FIG. 50 , in some embodiments, the semiconductor wafer W 2 is disposed on a temporary carrier TC 4 through a temporary bonding layer TB 4 . In some embodiments, the temporary bonding layer TB 4 is deposited on the temporary carrier TC 4 , and the semiconductor wafer W 2 is attached to the temporary carrier TC 4 through the temporary bonding layer TB 4 by placing the front surfaces S 3 of the semiconductor dies 10 B′ to be in contact with the temporary bonding layer TB 4 . Alternatively, the temporary bonding layer TB 4 may be omitted. The formation and/or material of the temporary bonding layer TB 4 and the temporary carrier TC 4 are similar to the formation and/or material of the temporary bonding layer TB 1 and the temporary carrier TC 1 described in FIG. 2 , thus are not repeated herein. As shown in FIG. 50 , for example, the bottom surfaces 210 b ′ of the semiconductor dies 10 B′ face upwardly for subsequent processing.

Referring to FIG. 51 , in some embodiments, the semiconductor wafer W 2 is processed to form a semiconductor wafer W 2 ′ having a plurality of semiconductor dies 10 B connected to one another. The semiconductor dies 10 B are referred to as the carrier dies 10 B, in some embodiment. For example, the semiconductor wafer W 2 is processed through the steps described in FIG. 7 through FIG. 10 , so the detailed descriptions are omitted for brevity. As shown in FIG. 51 , each of the carrier dies 10 B includes the semiconductor substrate 210 having semiconductor devices formed therein, the interconnect structure 220 formed over the semiconductor substrate 210 and including dielectric layers and metallization patterns proximal to the front surface S 3 , the isolation layer 240 formed over the semiconductor substrate 210 opposite to the interconnect structure 220 , and the conductive vias 230 formed in the semiconductor substrate 210 , extending into the dielectric layers of the interconnect structure 220 to be in physical and electrical contact with the metallization pattern of the interconnect structure 220 and penetrating through the isolation layer 240 . The conductive vias 230 of each of the carrier dies 10 B may be electrically coupled to the semiconductor devices in the semiconductor substrate 210 through the metallization patterns of the interconnect structure 220 . In some embodiments, the semiconductor dies 10 B each have the front surface S 3 and the back surface S 4 opposite to the front surface S 3 . In some embodiments, each of the carrier dies 10 B is referred to as one base tier 10 B( 0 ) for one die stack 100 .

Referring to FIG. 52 , in some embodiments, a first set of semiconductor dies 10 A″ are provided, where these semiconductor dies 10 A″ are stacked on the carrier dies 10 B. For example, the semiconductor dies 10 A″ are fabricated as described in conjunction with FIG. 1 through FIG. 4 . In some embodiments, the semiconductor dies 10 A″ are bonded to the carrier dies 10 B in a face-to-back configuration, through a hybrid bonding process. The bonding process and the bonding relationship/configuration are described in FIG. 11 in combination with FIG. 26A and FIG. 26B (illustrating the enlarged cross-sectional views indicated by the dashed box A), and thus are not repeated herein. For example, as shown in FIG. 52 , the front surfaces S 1 of the semiconductor dies 10 A″ are bonded to the back surface S 4 of the carrier dies 10 B, respectively.

Referring to FIG. 53 , in some embodiments, the first set of the semiconductor dies 10 A″ are processed to form semiconductor dies 10 A of the first tier 10 A( 1 ) in the die stacks 100 . For example, the semiconductor dies 10 A″ are processed through the steps described in FIG. 12 through FIG. 16 , so the detailed descriptions are omitted for brevity. As shown in FIG. 53 , each of the semiconductor die 10 A includes the semiconductor substrate 110 having semiconductor devices (not shown) formed therein, the interconnect structure 120 formed on the semiconductor substrate 110 , the plurality of conductive vias 130 formed in the semiconductor substrate 110 and extending into the interconnect structure 120 , the dielectric layer 140 formed on the interconnect structure 120 and opposite to the semiconductor substrate 110 , the bonding conductors 150 formed over the interconnect structure 120 and laterally covered by the dielectric layer 140 , and the isolation layer 160 disposed on the semiconductor substrate 110 opposite to the interconnect structure 120 and with the conductive vias 130 penetrating therethrough. In some embodiments, the semiconductor dies 10 A each have the front surface S 1 and the back surface S 2 opposite to the front surface S 1 . For example, as shown in FIG. 53 , the semiconductor dies 10 A are separated from each other through the isolation structure 50 ( 1 ), where the isolation structure 50 ( 1 ) is over the semiconductor wafer W 2 ′.

Referring to FIG. 54 , in some embodiments, a second set of the semiconductor dies 10 OA″ are provided, and these semiconductor dies 10 A″ are respectively stacked on the semiconductor dies 10 A of the first tier 10 A( 1 ). In the disclosure, each semiconductor die 10 A″ (from the second set) is disposed on one of the semiconductor dies 10 A of the first tier 10 A( 1 ) in a face-to-back configuration for forming a second tier (e.g. 10 A( 2 ) depicted in FIG. 55 ) of the die stacks 100 . In some embodiments, the semiconductor dies 10 A″ (from the second set) are bonded to the semiconductor dies 10 A of the first tier 10 A( 1 ) through a hybrid bonding process. The bonding process and the bonding relationship/configuration are described in FIG. 17 in combination with FIG. 27A and FIG. 27B (illustrating the enlarged cross-sectional views indicated by the dashed box B), and thus are not repeated herein. For example, as shown in FIG. 54 , the front surfaces S 1 of the semiconductor dies 10 A″ (from the second set) are bonded to the back surface S 2 of the semiconductor dies 10 A of the first tier 10 A( 1 ), respectively. For example, the conductive vias 130 are not yet accessibly revealed by the semiconductor substrate 110 .

Referring to FIG. 55 , in some embodiments, the die stacks 100 is formed over the carrier dies 10 B. For example, each of the die stacks 100 includes at least one inner tier (e.g. 10 A( 1 ) through 10 A(T−1)) and a topmost tier 10 A(T). In some embodiments, the structure depicted in FIG. 54 is processed to form the die stacks 100 . For example, in each die stack 100 , each inner tier (e.g. 10 A( 2 ) through 10 A(T−1)) may be fabricated by the same steps forming the first tier 10 A( 1 ) as described in FIG. 53 , and the topmost tier 10 A(T) may be fabricated by the process as described in FIG. 54 , and thus the detailed descriptions are omitted for brevity. That is, the semiconductor dies 10 A at the inner tiers (e.g., 10 A( 1 ) through 10 A(T−1)) may be individually fabricated by repeating the steps as described in conjunction with FIG. 12 through FIG. 16 , and the topmost tier 10 A(T) may be fabricated by repeating the steps as described in conduction with FIG. 17 . With such, the semiconductor dies 10 A at the first tier 10 A( 1 ) through the (T−1)th tier 10 A(T−1) of each die stack 100 may be similar or the same in configurations, functions, and properties due to the similar forming steps are utilized. In some embodiments, after forming the die stacks 100 , the isolation structure is removed from the semiconductor wafer W 2 ′. For example, for every two adjacent tiers of each die stack 100 , the upper tier is bonded to the lower tier in a face-to-back configuration. By such bonding (without uses of any other external connectors), the semiconductor structure P 7 having a better form factor with a die stack of a higher density in devices is achieved.

Referring to FIG. 56 , in some embodiments, the semiconductor structure P 7 is manufactured by processing the structure depicted in FIG. 55 with the steps described in FIG. 20 through FIG. 24 , thus the detailed descriptions are omitted for brevity. In some embodiments, the semiconductor structure P 7 has the carrier die 10 B, the die stack 100 disposed thereon, the insulating encapsulation 20 formed on the carrier die 10 B and the die stack 100 , the electromagnetic interference shielding layer 60 sandwiched between the insulating encapsulation 20 and the carrier die 10 B and between the insulating encapsulation 20 and the die stack 100 , the protection layer 70 disposed on the carrier die 10 , and the conductive terminals 30 disposed on the insulating encapsulation 20 . As shown in FIG. 56 , a sidewall 20 S of the insulating encapsulation 20 is aligned with a sidewall S 5 of the carrier die 10 B and a sidewall 70 S of the protection layer 70 , for example. That is, the sidewall 20 S of the insulating encapsulation 20 may be substantially levelled with and coplanar to the sidewall S 5 of the carrier die 10 B and the sidewall 70 S of the protection layer 70 .

As illustrated in FIG. 56 and FIG. 57 (a top plane view on the X-Y plane), for the semiconductor structure P 7 , a positioning location of the die stack 100 is within a positioning location of the carrier die 10 B and within a positioning location of the insulating encapsulation 20 , where the edges of the carrier die 10 B are overlapped with the edges of the insulating encapsulation 20 . In other words, a perimeter of the die stack 100 is less than a perimeter of the carrier die 10 B and a perimeter of the insulating encapsulation 20 , and the perimeter of the carrier die 10 B is substantially equal to the perimeter of the insulating encapsulation 20 .

In addition, the modifications to the semiconductor structure P 1 a may also be adopted by the semiconductor structures P 5 , P 6 , and P 7 . Since the details of the modifications to the semiconductor structure P 1 a are described in FIG. 30 to FIG. 44 , so the detailed descriptions are omitted for brevity.

FIG. 58 is a schematic cross-sectional view showing an application of a semiconductor structure in accordance with some embodiments of the disclosure. Like elements are designated with the same reference numbers for ease of understanding and the details thereof are not repeated herein. Referring to FIG. 58 , a component assembly SC including a first component C 1 and a second component C 2 disposed over the first component C 1 is provided. The first component C 1 may be or may include an interposer, a package substrate, a printed circuit board (PCB), a printed wiring board, and/or other carrier that is capable of carrying integrated circuits. In some embodiments, the second component C 2 mounted on the first component C 1 is similar to one of the semiconductor structures P 1 a -P 1 d , P 2 a -P 2 d , P 3 a -P 3 d , P 4 a -P 4 d , P 5 , P 6 and P 7 described above. For example, one or more the semiconductor structures (e.g., P 1 a -P 1 d , P 2 a -P 2 d , P 3 a -P 3 d , P 4 a -P 4 d , P 5 , P 6 and P 7 ) may be electrically coupled to the first component C 1 through a plurality of terminals CT. The terminals CT may be the conductive terminals 30 .

In some embodiments, an underfill layer UF is formed between the gap of the first component C 1 and the second component C 2 to at least laterally cover the terminals CT. Alternatively, the underfill layer UF is omitted. In one embodiment, the underfill layer UF may be formed by underfill dispensing or any other suitable method. In some embodiments, a material of the underfill layer UF may be the same or different from a material of the insulating encapsulations 20 , 40 , the disclosure is not limited thereto. Owing to the underfill layer UF, a bonding strength between the first component C 1 and the second component C 2 is enhanced.

In some other embodiments, the second component C 2 mounted on the first component C 1 may be an integrated fan-out (InFO) package including at least one semiconductor structure (e.g., P 1 a -P 1 d , P 2 a -P 2 d , P 3 a -P 3 d , P 4 a -P 4 d , P 5 , P 6 and P 7 respectively described above in conjunction with FIG. 24 , FIG. 31 through FIG. 44 , FIG. 45 , FIG. 47 and FIG. 56 ) packaged therein. For example, the second component C 2 includes a plurality of semiconductor structures (e.g., any combinations of semiconductor structures P 1 a -P 1 d , P 2 a -P 2 d , P 3 a -P 3 d , P 4 a -P 4 d , P 5 , P 6 and P 7 ) disposed side by side and surrounding by a packaging encapsulation (not shown; e.g., a molding compound). The second component C 2 may further include a fan-out redistribution structure (not shown) formed on the packaging encapsulation and these semiconductor structures laterally encapsulated by the packaging encapsulation, and the fan-out redistribution structure may be electrically coupled to these semiconductor structures. In such embodiments, the terminals CT may be controlled collapse chip connection (C4) bumps, ball grid array (BGA) bumps, other suitable terminals having the dimension greater than the conductive terminals of the semiconductor structures, and/or the like. For example, the terminals CT are formed on the fan-out redistribution structure to be electrically coupled to the first component C 1 , and these semiconductor structures are electrically coupled to the terminals CT through the fan-out redistribution structure.

Other packaging techniques may be used to form the component assembly SC, which are not limited in the disclosure. For example, the component assembly SC is formed using a wafer level packaging (WLP), a chip-on-wafer-on-substrate (CoWoS) process, a chip-on-chip-on-substrate (CoCoS) process, etc. The component assembly SC may be a part of an electronic system for such as computers (e.g., high-performance computer), computational devices used in conjunction with an artificial intelligence system, wireless communication devices, computer-related peripherals, entertainment devices, etc. The component assembly SC including the semiconductor structure(s) discussed herein may provide high bandwidth data communication. It should be noted that other electronic applications are also possible. Alternatively, an additional terminals may be physical and electrical contact with first component C 1 opposite to the terminals CT for electrical connection to any other external component(s).

In accordance with some embodiments, a semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.

In accordance with some embodiments, a semiconductor structure includes a semiconductor device, a plurality of conductive terminals, and a connection structure. The semiconductor device includes a base tier and a die stack. The base tier includes a first die. The die stack is bonded to the base tier and includes second dies arranged into at least one inner tier and an outmost tier. The die stack and the base tier are bonded through a first hybrid bonding interface. The at least one inner tier and the outmost tier are bonded through a second hybrid bonding interface. An offset is between a sidewall of the base tier and a sidewall of the die stack, wherein the first die and the second dies are electrically communicated to each other. The plurality of conductive terminals are over and electrically connected to the semiconductor device. The connection structure is located between the semiconductor device and the plurality of conductive terminals, wherein the base tier is located between the connection structure and the die stack, and the at least one inner tier is located between the base tier and the outmost tier.

In accordance with some embodiments, a method of manufacturing semiconductor structure includes the following steps, forming at least one stacked structure comprising: providing a base tier comprising a first semiconductor die and forming a die stack comprising second semiconductor dies on the base tier through hybrid bonding, wherein a first dimension of the base tier is greater than a second dimension of the die stack along a lateral direction, and the first semiconductor die is electrically connected to the second semiconductor dies; forming a connection structure over the at least one stacked structure, the base tier being between the connection structure and the die stack; and disposing a plurality of conductive terminals over the at least one stacked structure and electrically connecting the plurality of conductive terminals to the first semiconductor die, the connection structure being between the plurality of conductive terminals and the base tier.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.