Phase change memory apparatus and read control method to reduce read disturb and sneak current phenomena

The invention relates in general to a memory device and associated control method, and more particularly to a memory device and associated control method for performing a read operation.

As is well known, consumer electronics has exponentially increased the need for memory size. Therefore, usage demands of nonvolatile memories (hereinafter, NVM) are continuously growing, and new class of memory technologies has rapidly developed.

Among various NVM technologies, phase change materials (hereinafter, PCM) technology has made rapid progress in a short time. Conventionally, the minimum lithographic resolution is commonly referred to as “F” and an area equal to “4F 2 ” is often considered a desired design goal for a memory cell to achieve maximum density.

FIG. 1 is a schematic diagram of a PCM memory array based on a crossbar scheme. As shown in FIG. 1 , a PCM memory cell is corresponding to an area equal to “4F 2 ”. That is, the PCM memory cell size is marching towards minimum achievable feature size. The cost of manufacturing memory is inversely related to bit density. Therefore, the PCM technology becomes attractive because the PCM memory can be manufactured at very high density.

The memory array in FIG. 1 is electrically connected to 4 bit lines (BL 1 ˜BL 4 ) and 4 word lines (WL 1 ˜WL 4 ). The memory array includes 16 PCM memory cells (M 11 ˜M 44 ) which are arranged at intersections of the bit lines BL 1 ˜BL 4 and the word lines WL 1 ˜WL 4 . The PCM memory cells operate in two phases, a highly conductive state (that is, poly-crystalline state) and a highly resistive state (that is, amorphous state). Transition between the two phases is achieved by changing voltage difference between two terminals of the PCM memory cell.

In a case that a read operation is performed to the memory cell M 32 , a read current originating from the bit line BL 3 flows through the memory cell M 32 and flows to the word line WL 2 . Then, the read current flowing through the memory cell CM 32 is utilized to determine a storage state of the memory cell M 32 . The storage state of the memory cell M 32 is corresponding to data content to be stored at the memory cell M 32 . However, the storage state of the PCM memory cell can be disturbed by inadvertently larger voltage difference between the bit lines and the word lines dropped on PCM device after a selector switch was turned on, and the cell was scathed a little and finally the data content may be incorrectly fetched. Therefore, performing a reliable read operation to the PCM memory is an important issue.

The invention is directed to a memory device and associate control method. A control method is applied to a read operation of the memory device. According to the control method, voltages to be applied to the bit line and the word line which are connected to a selected memory cell are changed in different stages of the read operation in order to prevent from causing read disturb phenomenon.

According to a first aspect of the present disclosure, a memory device is provided. The memory device is electrically connected to M bit lines and N word lines. The memory device includes a memory array and a controller. The memory array includes MxN memory cells being located at intersections of the M bit lines and the N word lines. A memory cell being electrically connected to an m-th bit line among the M bit lines and an n-th word line among the N word lines is defined as a selected memory cell. The selected memory cell includes a storage element and a selector switch. The storage element is electrically connected to one of the m-th bit line and the n-th word line. The storage element receives a predefined constant voltage during a read duration including a first duration, a second duration, and a post duration. The selector switch is electrically connected to the other one of the m-th bit line and the n-th word line. The controller is electrically connected to the memory array. The controller changes a cell cross voltage of the selected memory cell in the first duration, the second duration, and the post duration, respectively. The cell cross voltage in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration. Then, the controller compares a sensing voltage and a reference voltage to determine a storage state of the storage element. The sensing voltage is related to voltage of the other one of the m-th bit line and the n-th word line.

According to a second aspect of the present disclosure, a control method applied to a memory cell in a memory device is provided. The memory cell includes a storage element and a selector switch. The storage element is electrically connected to an m-th bit line and the selector switch is electrically connected to an n-th word line. The control methods includes following steps. Firstly, the m-th bit line is applied with a predefined constant voltage during a read duration including a first duration, a second duration, and a post duration. A selector cross voltage is greater than a threshold voltage of the selector switch in the first duration. Then, voltage of the n-th word line is changed during the read duration. A cell cross voltage of the memory cell in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration. Later, a sensing voltage and a reference voltage are compared to determine a storage state of the storage element, wherein the sensing voltage is related to the voltage of the n-th word line.

According to a third aspect of the present disclosure, a control method applied to a memory cell in a memory device is provided. The memory cell includes a storage element and a selector switch. The storage element is electrically connected to an n-th word line and the selector switch is electrically connected to an m-th bit line. The control methods includes following steps. Firstly, the n-th word line is applied with a predefined constant voltage during a read duration comprising a first duration, a second duration, and a post duration. A selector cross voltage is greater than a threshold voltage of the selector switch in the first duration. Then, voltage of the m-th bit line is changed during the read duration. A cell cross voltage of the memory cell in the first duration is greater than the cell cross voltage in the post duration, and the cell cross voltage in the post duration is greater than the cell cross voltage in the second duration. Later, a sensing voltage and a reference voltage are compared to determine a storage state of the storage element, wherein the sensing voltage is related to the voltage of the m-th bit line.

The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.

FIG. 1 (Prior Art) is a schematic diagram of a PCM memory array based on a crossbar scheme.

FIG. 2 is a schematic diagram illustrating voltage control of the PCM memory array.

FIG. 3A is a schematic diagram illustrating a read operation performed to the selected memory cell according to an embodiment of the present disclosure.

FIG. 3B is a schematic diagram illustrating a memory device having a column decoder, a row decoder and memory cells being read with the read operation shown in FIG. 3A .

FIG. 3C is a schematic diagram illustrating a read operation performed to the selected memory cell according to another embodiment of the present disclosure.

FIG. 3D is a schematic diagram illustrating a memory device having a column decoder, a row decoder and memory cells being read with the read operation shown in FIG. 3C .

FIG. 4A is a schematic diagram illustrating current-voltage characteristic of the selector switch.

FIG. 4B is a schematic diagram illustration changes of the selector cross voltage ΔVsw during the read operation of the memory cell.

FIG. 5 is a schematic diagram illustrating changes of the cell cross voltage ΔVmem during the read operation of the memory cell.

FIG. 6 is a schematic block diagram illustration design of the read circuit according to the embodiment shown in FIG. 3A .

FIG. 7 is a schematic waveform diagram illustration signal control of the bock diagram shown in FIG. 6 .

FIG. 8 is a schematic flow diagram illustrating the control method applied to the memory device according to the embodiment of the present disclosure.

FIG. 9 is a schematic block diagram illustrating a circuitry implementation of FIG. 6 .

FIG. 10 is a schematic block diagram illustration design of the read circuit according to the embodiment shown in FIG. 3C .

FIG. 11 is a schematic waveform diagram illustration signal control of the bock diagram shown in FIG. 9 .

FIG. 12 is a schematic flow diagram illustrating the control method applied to the memory device according to the embodiment of the present disclosure.

FIG. 13 is a schematic circuit diagram illustrating a circuitry implementation of FIG. 11 .

FIG. 2 is a schematic diagram illustrating voltage control of the PCM memory array. The memory cells M 31 , M 12 , M 22 , M 42 , M 33 , M 34 are shown in saltires to represent no current flowing though. The memory cells M 11 , M 21 , M 41 , M 13 , M 23 , M 43 , M 14 , M 24 , M 44 shown in diagonal stripes to represent that they are semi-conducted. The memory cell M 32 being fully conducted is shown in white rectangle. Moreover, a cross voltage of the memory cell M 32 is represented as a cell cross voltage ΔVmem.

In order to detect the storage state of the memory cell M 32 , the bit line BL 3 is applied with a read high voltage (that is, 2.2V), and the word line WL 2 is applied with a read low voltage (that is, 0.8V). The rest bit lines BL 1 , BL 2 , BL 4 and the rest word lines WL 1 , WL 3 , WL 4 which are not selected are applied with the default voltage (that is, 1.5V). The memory cell M 32 is fully conducted because the voltage difference between the bit line BL 3 and the word line WL 2 is 1.4V, and the read current, as shown by block arrow, flows from the bit line BL 3 to the word line WL 2 . Meanwhile, some sneak currents (leakage currents), as shown by dotted arrows, can flow through memory cells M 31 , M 12 , M 22 , M 42 , M 33 , M 34 which are located at the same column or same row of the memory cell M 32 .

In order to prevent sneak current phoneme of the storage element (for example, a PCM cell), each of the storage element PCM is used together with a selector switch SEL. The selector switch SEL is laid in serial with the storage element PCM, without requiring additional area. As enlarged at the lower right corner of FIG. 2 , each memory cell includes a storage element PCM and a selector switch SEL.

The resistance of the selector switch SEL before the threshold switching is highly resistive with several MΩ order and after the threshold switching drops steeply to around 20 kΩ to 30 kΩ. The resistance of the storage element PCM is around 20 kΩ when the storage element PCM is highly conductive (SET state), and the order of magnitude of resistance of the storage element PCM is MΩ when the storage PCM is highly resistive (RESET state).

Basically, operation of the selector switch SEL is known as threshold switching phenomenon. When the selector switch SEL whose corresponding storage element PCM is not selected, resistance of the selector switch SEL is relatively high so that no current is conducted. When a selector switch SEL whose corresponding storage element PCM is selected, resistance of the selector is relatively low so that a large current is conducted.

Alternatively speaking, the selector switch SEL is likely to block the sneak currents accompanied with the storage elements PCM which are not actually selected for read operation but suffered from the voltage rise of the bit line BL 3 or the voltage drop of the word line WL 2 . That is, the selector switches SEL at memory cells M 31 , M 12 , M 22 , M 42 , M 33 , M 34 can suppress the side effects caused by the sneak currents.

In the context, the memory array is assumed to include MxN memory cells, and a memory cell located at the intersection of the m-th bit line and the n-th word line is selected (that is, a selected memory cell MEMmn). The variables M, N, m, and n are positive integers, m is smaller or equivalent to M, and n is smaller or equivalent to N. For example, in FIG. 2 , it is assumed that M=4, N=4, m=3, and n=2. According to the embodiments of the present disclosure, each of the memory cells includes a storage element PCM and a selector switch SEL. The storage element PCM and the selector switch SEL are electrically connected in serial.

FIG. 3A is a schematic diagram illustrating a read operation performed to the selected memory cell according to an embodiment of the present disclosure. The storage element PCM in the selected memory cell MEMmn is electrically connected to the m-th bit line BLm, and the selector switch SEL in the selected memory cell MEMmn is electrically connected to the n-th word line WLn.

In FIG. 3A , the memory device is assumed to include the memory array having MxN memory cells, a controller and N read circuits. The N read circuits are respectively corresponding to the N word lines. Among the N read circuits, an n-th read circuit 131 is electrically connected to the n-th word line WLn to acquire a sensing voltage Vsen being generated based on voltage of a dynamic control terminal Nvc. The controller sets the m-th bit line at a predefined constant voltage V const _ H and changes the voltage of the n-th word line WLn during a read duration Trd. Then, the sensing voltage Vsen is acquired by the n-th read circuit 131 to generate a comparison signal Scmp so that the controller can accordingly determine a storage state of the storage element PCM.

In some applications, decoding circuits can be used together with the read circuits so that the number of read circuit can be less than N. FIG. 3B is a schematic diagram illustrating a memory device having a column decoder, a row decoder and memory cells being read with the read operation shown in FIG. 3A .

The memory device 12 includes a controller 121 , a power source 122 , a read circuit 124 , a row decoder 125 , a column decoder 123 , and a memory array 126 . In FIG. 3B , it is assumed that the memory array 126 includes 16 memory cells, and the 16 memory cells are arranged in four rows and four columns (that is, M=4 and N=4).

The storage elements PCM of the memory cells are electrically connected to the power source 122 through four bit lines BL 1 ˜BL 4 and the column decoder 123 . With the column decoder 123 , the voltage supplied by the power source 122 can be transmitted to any of the four bit lines BL 1 ˜BL 4 .

The selector switches SEL of the memory cells are respectively electrically connected to the read circuit through four word lines WL 1 ˜WL 4 and the row decoder 125 . With the row decoder 125 , the read circuit 124 can sense voltage level of any of the four word lines WL 1 ˜WL 4 .

FIG. 3C is a schematic diagram illustrating a read operation performed to the selected memory cell according to another embodiment of the present disclosure. The selector switch SEL in the selected memory cell MEMmn is electrically connected to the m-th bit line BLm, and the storage element PCM in the selected memory cell MEMmn is electrically connected to the n-th word line WLn.

In FIG. 3C , the memory device includes the memory array having MxN memory cells, a controller and M read circuits. The M read circuits are respectively corresponding to M bit lines. Among the M read circuits, an m-th read circuit 133 is electrically connected to the m-th bit line BLm to acquire a sensing voltage Vsen being generated based on voltage of a dynamic control terminal Nvc. The controller sets the n-th word line WLn at a predefined constant voltage level V const _ L , and changes the voltage of the m-th bit line BLm during the read duration Trd. Then, the sensing voltage Vsen is acquired by the m-th read circuit 133 to generate a comparison signal Scmp so that the controller can accordingly determine the storage state of the storage element PCM.

In some applications, decoding circuits can be used together with the read circuits so that the number of read circuit can be less than M. FIG. 3D is a schematic diagram illustrating a memory device having a column decoder, a row decoder and memory cells being read with the read operation shown in FIG. 3C .

The memory device 14 includes a controller 141 , a power source 144 , a read circuit 142 , a row decoder 145 , a column decoder 143 , and a memory array 146 . In FIG. 3D , it is assumed that the memory array 146 includes 16 memory cells, and the 16 memory cells are arranged in four rows and four columns (that is, M=4 and N=4).

The storage elements PCM of the memory cells are electrically connected to the power source 144 through four word lines WL 1 ˜WL 4 and the row decoder 145 . With the row decoder 145 , the voltage transmitted by the power source 144 can be transmitted to any of the four word lines WL 1 ˜WL 4 .

The selector switches SEL of the memory cells are respectively electrically connected to the read circuit 142 through four bit lines BL 1 ˜BL 4 and the column decoder 143 . With the column decoder 143 , the read circuit 142 can sense voltage level of any of the four bit lines BL 1 ˜BL 4 .

As shown in FIGS. 3A and 3C , a cross voltage of the storage element PCM is defined as a storage cross voltage ΔVpcm, and a cross voltage of the selector switch SEL is defined as a selector cross voltage ΔVsw. The summation of the storage cross voltage ΔVpcm and the selector cross voltage ΔVsw is equivalent to the cell cross voltage ΔVmem.

The resistance of the selector switch SEL is varied with the state of the selector switch SEL. In a case that the selector switch SET is at the “OFF” state, the resistance of the selector switch SEL is much greater than the resistance of the storage element PCM. On the other hand, in a case that the selector switch SET is at the “ON” state, the resistance of the selector switch SEL is much less than the resistance of the storage element PCM.

Because the selector switch SEL and the storage element PCM are serially connected that the same current flows though both of which, relationship between the resistances of the selector switch SET and the storage element PCM is positively related to the relationship between the selector cross voltage ΔVsw and the storage cross voltage ΔVpcm.

As illustrated above, the resistance of the selector switch SEL is much greater than the resistance of the storage element PCM when the selector switch SET is at the “OFF” state. Accordingly, the storage cross voltage ΔVpcm is much lower than the selector cross voltage ΔVsw of the selector switch SET if the selector switch SEL is at the OFF state.

On the other hand, the resistance of the selector switch SEL is much less than the resistance of the storage element PCM when the selector switch SET is at the “ON” state. Meanwhile, the selector cross voltage ΔVsw is equivalent to the hold voltage Vhld, and the storage cross voltage ΔVpcm is much greater than the selector cross voltage ΔVsw of the selector switch SET because the resistance of the storage element PCM is greater than the resistance of the selector switch SEL at the ON state.

FIG. 4A is a schematic diagram illustrating current-voltage characteristic of the selector switch. The selector switch SEL can be, for example, an Ovonic Threshold Switch (hereinafter, OTS). The selector switch SEL transits between the “ON” state and the “OFF” state in response to the selector cross voltage ΔVsw. The arrow a 1 in FIG. 4A shows that the state of the selector switch SEL changes from the OFF state to the ON state when the selector cross voltage ΔVsw exceeds a threshold voltage Vth. Once the selector cross voltage ΔVsw is greater than or equivalent to the threshold voltage Vth, the ON state is triggered and the selector switch SEL is in a substantially conductive state.

As shown by the arrow a 2 , if the selector cross voltage ΔVsw drops and becomes lower than a hold voltage Vhld, the selector switch SEL will return to the OFF state. On the other hand, once the selector cross voltage ΔVsw becomes greater than the threshold voltage Vth and drops back, and the selector cross voltage ΔVsw still remains to be greater than the hold voltage Vhld, the selector switch SEL stays at the ON state.

The threshold voltage Vth of the selector switch SEL is not always constant. In practical applications, the threshold voltage Vth gradually increases with aging of the memory device. That is, the longer the memory device is used, the greater the threshold voltage Vth of the selector switch SEL is. In order to ensure the selector switch SEL can be correctly and successfully turned on whenever necessary, the controller usually applies the selector cross voltage ΔVsw which is higher than actually required to the turn on the selector switch SEL. Since the selector switch SEL and the storage element PCM are manufactured and tied together in the memory cell, increase of the selector cross voltage ΔVsw implies that the cell cross voltage ΔVmem is increased. However, the design that a cell cross voltage ΔVmem with the value higher than necessity for turning on the selector switch SEL may degrade the characteristic of the storage element PCM.

In short, the voltages being applied to the n-th word line and the m-th bit line in order to turn on the selector switch SEL may result in read disturb phenomenon to the storage element PCM. To reduce the side effects caused by applying the high cell cross voltage ΔVmem, the current-voltage characteristic of the selector switch SEL is utilized in performing a read operation of the memory cell including the storage element PCM and the selector switch SEL. A generic concept about the relationship between the selector cross voltage ΔVsw and the read operation is firstly introduced.

FIG. 4B is a schematic diagram illustration changes of the selector cross voltage ΔVsw during the read operation of the memory cell. The duration of the read operation Trd can include a preset duration Tpre and a post duration Tpost. The preset duration Tpre further includes two sub durations, that is, a first duration T 1 between time point t 1 and time point t 2 , and a second duration T 2 between time point t 2 and time point t 3 .

During the first duration T 1 , the selector cross voltage ΔVsw is controlled to be greater than the threshold voltage Vth. During the second duration T 2 , the selector cross voltage ΔVsw is controlled to be lower than the threshold voltage Vth but greater than the hold voltage Vhld. During the post duration Tpost, the selector cross voltage ΔVsw increases again. The selector cross voltage ΔVsw during the post duration Tpost is lower than its value in the first duration T 1 and greater than its value in the second duration T 2 .

The length of the durations T 1 and T 2 , and the post duration Tpost are related to types and characteristic of the selector switch SEL. For example, the first duration T 1 can be greater than or equivalent to 20 ns, the second duration T 2 can be equivalent to 20 ns, and the post duration Tpost can be equivalent to 200 ns.

As illustrated above, the cell cross voltage ΔVmem is equivalent to summation of the selector cross voltage ΔVsw and the storage cross voltage ΔVpcm. Therefore, the cell cross voltage ΔVmem has similar character as the selector cross voltage ΔVsw shown in FIG. 4B .

FIG. 5 is a schematic diagram illustrating changes of the cell cross voltage ΔVmem during the read operation of the memory cell. According to the embodiments of the present disclosure, the control method to be applied in read operation of the memory device can be divided into three stages, the first duration T 1 , the second duration T 2 , and the post duration Tpost.

The cell cross voltage ΔVmem during the first duration T 1 is defined as a first voltage difference ΔV 1 , the cell cross voltage ΔVmem during the second duration T 2 is defined as a second voltage difference ΔV 2 , and the cell cross voltage ΔVmem during the post duration Tpost is defined as a third voltage difference ΔV 3 . The first voltage difference ΔV 1 is greater than the third voltage difference ΔV 3 , and the third voltage difference ΔV 3 is greater than the second voltage difference ΔV 2 .

The first voltage difference ΔV 1 during the first duration T 1 can force the selector switch SEL changes from the OFF state to the ON state. On the other hand, the second voltage difference ΔV 2 shrinks the cross voltage ΔVmem. Lowering the voltage difference of ΔVmem soon after the selector switch SEL is turned on can ensure the selector switch SEL remains to be at the ON state without generating a big current flowing through the selector switch SEL, so as the storage element PCM. Therefore, the read disturb phenomenon caused at the storage element PCM can be prevented.

FIG. 6 is a schematic block diagram illustration design of the read circuit according to the embodiment shown in FIG. 3A . The read circuit 23 includes a sense module 234 , a comparison circuit 233 , and a voltage providing circuit 231 , and the sense module 234 further includes a first preset circuit 237 a , a second preset circuit 237 b and a sense circuit 235 . The memory cell 21 includes a storage element PCM and a selector switch SEL.

The n-th word line WLn, the first preset circuit 237 a , the second preset circuit 237 b , and the sense circuit 235 are electrically connected to each other through the dynamic control terminal Nvc. Voltage of the dynamic control terminal Nvc is changed in a stage based control manner during the read duration Trd. During the read duration Trd, the storage element PCM receives a predefined constant voltage V const _ H through the m-th bit line BLm.

During a read operation, the comparison circuit 233 receives a sensing voltage Vsen from the sense circuit 235 . Because the resistance of the storage element PCM is related to the storage state of the storage element PCM, the cell cross voltage ΔVmem is changed in response to the storage state of the storage element PCM. Consequentially, the voltage of the n-th word line WLn and the sensing voltage Vsen are related to the storage state of the storage element PCM.

In addition, the voltage providing circuit 231 provides a reference voltage Vref to the comparison circuit 233 . After receiving the sensing voltage Vsen and the reference voltage Vref, the comparison circuit 233 accordingly generates a comparison signal Scmp to the controller 25 . For example, if the sensing voltage Vsen is greater than the reference voltage Vref, the comparison signal Scmp is at a first voltage level, and if the sensing voltage Vsen is lower than the reference voltage Vref, the comparison signal Scmp is at a second voltage level.

The comparison signal Scmp is corresponding to the storage state of the storage element PCM in the memory cell 21 , and the storage state of the storage element PCM represents data content being stored at the storage element PCM. Later, the controller 25 determines data content of the storage element PCM based on the voltage level of the comparison signal Scmp. For example, the controller 25 determines the data content of the storage element PCM in the memory cell is “1” when the comparison signal Scmp is at the first voltage level; and the controller 25 determines the data content of the storage element PCM in the memory cell is “O” when the comparison signal Scmp is at the second voltage level.

In FIG. 6 , the comparison circuit 233 receives a comparison enable signal ENcmp from the controller 25 , the sense circuit 235 receives a read enable signal ENrd from the controller 25 , the first preset circuit 237 a receives a first enable signal ENpre 1 from the controller 25 , and the second preset circuit 237 b receives a second enable signal ENpre 2 from the controller 25 . These enable signals are generated by the controller 25 to control their counterpart circuits. Details about usage and function of the first enable signal ENpre 1 , the second enable signal ENpre 2 , the read enable signal ENrd, and the comparison enable signal ENcmp are illustrated in FIG. 7 .

FIG. 7 is a schematic waveform diagram illustration signal control of the bock diagram shown in FIG. 6 . The duration while the read circuit performing the read operation is defined as the read duration Trd. Moreover, a voltage difference between the m-th bit line BLm and the n-th word line WLn is equivalent to the cell cross voltage ΔVmem.

The first enable signal ENpre 1 is at the high logic level between time point t 1 and time point t 2 , that is, the first duration T 1 . The second enable signal ENpre 2 is at the high logic level between time point t 2 and time point t 3 , that is, the second duration T 2 . The read enable signal ENrd is at the high logic level between time point t 1 and time point t 5 , that is, the read duration Trd. The comparison enable signal ENcmp is at the high logic level between time point t 4 and time point t 5 , that is, the sensing duration Tsen.

Both the m-th bit line BLm and the n-th word line WLn are set at the default voltage (1.5V) before and after the read duration Trd. The m-th bit line BLm rises at time point t 1 to the predefined constant voltage V const _ H (for example, 2.2V) and remains at the predefined constant voltage during the read duration Trd. During the read duration Trd, the first enable signal ENpre 1 , the second enable signal ENpre 2 , the read enable signal ENrd and the comparison enable signal ENcmp jointly change the voltage of the n-th word line WLn.

In the first duration T 1 , the voltage of the n-th word line WLn drops from the default voltage (1.5V) to a relatively low level. In the second duration T 2 , the voltage of the n-th word line WLn increase from the relatively low level to a relatively high level. During the post duration Tpost, the voltage of the n-th word line WLn changes from the relatively high level to a middle level and basically remains at the middle level until the comparison enable signal ENcmp drops to the low logic level. After the read duration Trd, voltages of the m-th bit line BLM and the n-th word line WLn gradually return to the default voltage (1.5V).

Details about how the first enable signal ENpre 1 , the second enable signal ENpre 2 , the read enable signal ENrd and the comparison enable signal ENcmp cause voltage changes of the n-th word line WLn, how voltage of the n-th word line WLn changes in response, and how the controller receives the comparison signal are illustrated below.

FIG. 8 is a schematic flow diagram illustrating the control method applied to the memory device according to the embodiment of the present disclosure. The controller 25 receives a read command from a host (not shown) (step S 301 ), and the controller 25 sets the voltage of the m-th bit line BLm at the predefined constant voltage V const _ H (step S 303 ).

Then, the read duration Trd and the preset Tpre duration start. In the preset duration Tpre, the first enable signal ENpre 1 firstly enables the first preset circuit 237 a . After being enabled, the first preset circuit 237 a conducts the n-th word line WLn toward a lower voltage VRDP+|Vtp| so that the voltage of the n-th word line WLn is decreased (step S 305 ). The variable Vtp represents the threshold voltage of the PMOS transistor.

The second enable signal ENpre 2 then enables the second preset circuit 237 b . After being enabled, the second preset circuit 237 b conducts the n-th word line to the supply voltage terminal (Vcc) so that the voltage of the n-th word line WLn is increased (step S 307 ).

After the preset duration Tpre, the post duration Tpost starts. At the beginning of the post duration Tpost, the read circuit 23 waits a settling period to be well prepared to discriminate the state of accessed cell before the sensing duration Tsen starts. The voltage of the dynamic control terminal Nvc becomes stable before the sensing duration Tsen starts, and the voltage of the dynamic control terminal Nvc is directly related to the sensing voltage Vsen. In the sensing duration Tsen, the comparison circuit 233 generates comparison signal Scmp according to the sensing voltage Vsen and the reference voltage Vref (step S 309 ). Consequentially, the controller 25 determines the storage state of storage element PCM according to the comparison signal Scmp (step S 311 ).

Please refer to FIGS. 6, 7 and 8 together. The sense circuit 235 is controlled by the read enable signal ENrd. Because the read enable signal ENrd is at the high logic level during the read duration Trd, the sense circuit 235 continually operates during the read duration Trd.

The read duration Trd includes the preset duration Tpre and the post duration Tpost, and the preset duration Tpre further includes the first duration T 1 and the second duration T 2 . In the first duration T 1 , the first preset circuit 237 a is enabled by the first enable signal ENpre 1 . Therefore, a first preset current Ipre 1 originating from the dynamic control terminal Nvc flows through the first preset circuit 237 a toward a lower voltage equivalent to VRDP+|Vtp|, and the voltage of the n-th word line WLN drops during the first duration T 1 .

Although the sense circuit 235 is in operation, no current flows through the sense circuit 235 during the first duration T 1 because the cell cross voltage ΔVmem is not big enough so that the selector cross voltage ΔVsw is not greater than the threshold voltage Vth of the selector switch SEL. Alternatively speaking, the selector cross voltage ΔVsw is insufficient to change the state of the selector switch SEL, and the selector switch SEL is still at OFF state during the first duration T 1 . Such case represents that the storage element PCM is not selected and the waveform shown in FIG. 7 is not applicable. The following descriptions are based on the assumption that the selector switch SEL is turned on at the end of the first duration T 1 .

By time point t 2 , the selector cross voltage ΔVsw is big enough so that the selector cross voltage ΔVsw is greater than the threshold voltage Vth of the selector switch SEL. In consequence, the selector switch SEL changes its state to the ON state and remains at the ON state during the second duration T 2 . Because the selector switch SEL is at the ON state during the second duration T 2 , a memory current Imem originating from the m-th bit line BLm flows through the memory cell and the n-th word line WLn to the sense circuit 235 .

In order to read the storage state (data bit) of the storage element PCM, the controller applies a reading voltage Vread to the memory cell whose storage element PCM has been selected for reading. By receiving the reading voltage Vread, the selector switch SEL corresponding to the storage element PCM being selected is turned on, and a threshold current Ith thus flows through the memory cell. Meanwhile, the selector cross voltage ΔVsw is equivalent to the threshold voltage of the switch selector SEL.

In a case that the storage element PCM is at a SET state and the selector switch SEL is turned on, the selector cross voltage ΔVsw is equivalent to the threshold voltage of the switch selector SEL (ΔVsw=Vth) and the storage cross voltage ΔVpcm is equivalent to a product of a set-state resistance of the storage element PCM (Rset) and the threshold current (Ith) (ΔVpcm=Rset*Ith). The product of the set-state resistance of the storage element PCM (Rset) and the threshold current (Ith) can be considered as a reading threshold voltage Vth_rd_set of the storage element PCM at the “SET” state (Vth_rd_set=Rset*Ith). Accordingly, the cell cross voltage ΔVmem can be obtained by ΔVmem=ΔVsw+ΔVpcm=Vth+Rset*Ith if the storage element PCM of the memory cell being selected for the read operation is at the “SET” state.

In a case that the storage element PCM is at a RESET state and the selector switch SEL is turned on, the selector cross voltage ΔVsw is equivalent to the threshold voltage of the switch selector SEL (ΔVsw=Vth) and the storage cross voltage ΔVpcm is equivalent to a product of a reset-state resistance of the storage element PCM (Rreset) and the threshold current (Ith) (ΔVpcm=Rreset*Ith). The product of the reset-state resistance of the storage element PCM (Rreset) and the threshold current (Ith) can be considered as a reading threshold voltage Vth_rd_reset of the storage element PCM at the “RESET” state (Vth_rd_reset=Rreset*Ith). Accordingly, the cell cross voltage ΔVmem can be obtained by ΔVmem=ΔVsw+ΔVpcm=Vth+Rreset*Ith if the storage element PCM of the memory cell being selected for the read operation is at the “RESET” state.

For the storage element PCM, the reading threshold voltage of the storage element PCM at the “RESET” state (Vth_rd_reset) is greater than the reading threshold voltage of the storage element PCM at the “SET” state (Vth_rd_set). That is, Vth_rd_reset>Vth_rd_set. Such difference of the reading threshold voltage of the storage element PCM can thus be utilized to distinguish the SET/RESET state of the storage element PCM.

For the sake of illustration, a summation of the threshold voltage Vth of the switch selector SEL and the reading threshold voltage of the storage element PCM at the “SET” state Vth_rd_set can be defined as a cell reading threshold voltage of the SET state, and another summation of the threshold voltage Vth of the switch selector SEL and the reading threshold voltage Vth_rd_set of the storage element PCM at the “RESET” state can be defined as a cell reading threshold voltage of the RESET state.

When the reading voltage Vread is applied to the memory cell so that the cell cross voltage ΔVmem is greater than the cell reading threshold voltage of the SET state and lower than the cell reading threshold voltage of the RESET state, the storage element PCM at the “SET” state can conduct the threshold current Ith but the storage element PCM at the “RESET” state cannot. Therefore, by providing the reading voltage Vread which is greater than the cell reading threshold voltage of the SET state and lower than the cell reading threshold voltage of the RESET state, the storage state of the storage element PCM can be easily confirmed by detecting whether the threshold current Ith generates. In response to generation of the threshold current Ith, the sense circuit 235 can accordingly change the sensing voltage Vsen.

Based on the illustrations above, the cell cross voltage ΔVmem at the time point t 2 needs to be sufficient to turn on the selector switch SEL whose corresponding storage element PCM is at the “SET” state, but not sufficient to turn on the selector switch SEL whose corresponding storage element PCM is at the “RESET” state.

Moreover, during the second duration T 2 , the second preset circuit 237 b is enabled by the second enable signal ENpre 2 so that a second preset current Ipre 2 is conducted from the supply voltage terminal (Vcc) to the dynamic control terminal Nvc. Furthermore, the voltage of the n-th word line WLn increases during the second duration T 2 because of the second preset current Ipre 2 .

In the second duration T 2 , the memory current Imem and the second preset current Ipre 2 flow to and merge at the n-th word line WLn, and a merged current Imer is formed. The merged current Imer then flows through the sense circuit 235 . Accordingly, the selector switch SEL is maintained at the ON state during the second duration T 2 so that the cell cross voltage ΔVmem of the storage element PCM being at the SET state can be reduced.

After the second enable signal ENpre 2 drops to the low logic level at time point t 3 , the second preset circuit 237 b is disabled. Therefore, the second preset current Ipre 2 no longer exists during the post duration Tpost, and voltage of the dynamic control terminal Nvc drops. Then, voltage of the n-th word line WLn drops and becomes a little bit lower than its voltage level duration the second duration T 2 .

During the post duration Tpost, the memory current Imem continually flows from the m-th bit line BLm to the dynamic control terminal Nvc. The memory current Imem is considered as a sensing current Isen that flows through the sense circuit 235 to the ground terminal Gnd. With the sensing current Isen, the voltage of the n-th word line WLn is still greater than its voltage value at time point t 2 . Then, the sense circuit 235 generates the sensing voltage Vsen based on the memory current Imem.

During the sensing duration Tsen, the comparison enable signal ENcmp is at the high logic level to enable the comparison circuit 233 . In addition to the sensing voltage Vsen, the comparison circuit 233 also receives the reference voltage Vref from the voltage providing circuit 231 .

If the sensing voltage Vsen is greater than the reference voltage Vref, the comparison circuit 233 generates the comparison signal Scmp at a first logic level. If the sensing voltage Vsen is lower than the reference voltage Vref, the comparison circuit 233 generates the comparison signal Scmp at a second logic level. Based on the logic level of the comparison signal Samp, the controller 25 can determine the storage state of storage element PCM in the memory cell 21 .

FIG. 9 is a schematic block diagram illustrating a circuitry implementation of FIG. 6 . The sense circuit, the memory cell, and the replica module are respectively illustrated. In the embodiment, the voltage providing circuit 231 can have replica circuits which are symmetric to the memory cell 21 , the sense circuit 235 , the first preset circuit 237 a , and the second preset circuit 237 b.

In FIG. 9 , the voltage providing circuit 231 is assumed to include a replica memory cell 231 c , a replica sense circuit 231 d , a first replica preset circuit 231 a , and a second replica preset circuit 231 b . The replica memory cell 231 c includes a replica storage element PCM′ and a replica selector switch SEL′. The replica storage element PCM′ is electrically connected to a reference bit line BL_R, and the replica selector switch SEL′ is electrically connected to the replica sense circuit 231 d . The first replica preset circuit 231 a and the second replica preset circuit 231 b respectively receive the first enable signal ENpre 1 and the second enable signal ENpre 2 from the controller 25 .

The operations of the circuits in the voltage providing circuit 231 are basically similar to their counterparts and details are not redundantly described. The replica storage element PCM′ is assumed to have a resistance equivalent to a middle value of the resistance when the storage element PCM is highly conductive and the resistance when the storage element PCM is at highly resistive. For example, if the resistance of the storage element PCM at the highly conductive state is 100 k ohm, and the resistance of the storage element PCM at the highly resistive state is 1 M ohm, the resistance of the replica storage element PCM′ can be set to 500K ohm.

In FIG. 9 , the first preset circuit 237 a includes a PMOS transistor MP 0 P and an NMOS transistor MN 0 P. Similarly, the first replica preset circuit 231 a includes a PMOS transistor MP 1 P and an NMOS transistor MN 1 P.

The drain terminals of the PMOS transistor MP 0 P and the NMOS transistor MN 0 P are electrically connected to each other, and the drain terminals of the PMOS transistor MP 1 P and the NMOS transistor MN 1 P are electrically connected to each other. The source terminals of the NMOS transistors MN 0 P and MN 1 P are electrically connected to the ground terminal (Gnd).

The PMOS transistors MP 0 P and MP 1 P are controlled by a first bias voltage VRDP, and the NMOS transistors MN 0 P and MN 1 P are controlled by the second enable signal ENpre 2 . The source terminal of the PMOS transistor MP 0 P is electrically connected to the n-th word line WLn, and the source terminal of the PMOS transistor MP 1 P is electrically connected to a reference word line WL_R. The first bias voltage VRDP is assumed to be constant to keep the PMOS transistors MP 0 P and MN 1 P turned on.

Once the first enable signal ENpre 1 is at the high logic level, the NMOS transistors MN 0 P and MN 1 P are turned on, and the first preset current Ipre 1 and a first replica preset current Ipre 1 ′ are conducted in response. The first preset current Ipre 1 flows through the PMOS transistor MP 0 P and the NMOS transistor MN 0 P, and the first replica preset current Ipre 1 ′ flows through the PMOS transistor MP 1 P and the NMOS transistor MN 1 P.

In FIG. 9 , the second preset circuit 237 b includes an inverter INV, a PMOS transistor MP 2 P and an NMOS transistor MN 2 P. Similarly, the second replica preset circuit 231 b includes an inverter INV_R, a PMOS transistor MP 3 P and an NMOS transistor MN 3 P.

The source terminals of the PMOS transistors MP 2 P and MP 3 P are electrically connected to the supply voltage terminal (Vcc). The drain terminals of the PMOS transistor MP 2 P and the NMOS transistor MN 2 P are electrically connected to each other, and the drain terminals of the PMOS transistor MP 3 P and the NMOS transistor MN 3 P are electrically connected to each other. The source terminal of the NMOS transistor MN 2 P is electrically connected to the n-th word line WLn, and the source terminal of the NMOS transistor MN 3 P is electrically connected to the reference word line WL_R.

In the second preset circuit 237 b , the inverter INV receives the second enable signal ENpre 2 to control the PMOS transistor MP 2 P, and the NMOS transistor MN 2 P is controlled by a second bias voltage VRDN. In the second replica preset circuit 231 b , the inverter INV_R receives the second enable signal ENpre 2 to control the PMOS transistor MP 3 P, and the NMOS transistor MN 3 P is controlled by the second bias voltage VRDN. The second bias voltage VRDN is assumed to be constant to keep the NMOS transistors MN 2 P and MN 3 P turned on.

Once the second enable signal ENpre 2 is at the high logic level, the PMOS transistors MP 2 P and MP 3 P are turned on, and the second preset current Ipre 2 and a second replica preset current Ipre 2 ′ are conducted in response. The second preset current Ipre 2 flows through the PMOS transistor MP 2 P and the NMOS transistor MN 2 P, and the second replica preset current Ipre 2 ′ flows through the PMOS transistor MP 3 P and the NMOS transistor MN 3 P.

In FIG. 9 , the sense circuit 235 includes a PMOS transistor MP 0 , a resistor R 0 , and an NMOS transistor MN 0 R. Similarly, the replica sense circuit 231 d includes a PMOS transistor MP 1 , a resistor R 1 , and an NMOS transistor MN 1 R. The resistances of the resistor R 0 and R 1 are equivalent.

The source terminal of the PMOS transistor MP 0 is electrically connected to the n-th word line WLn, and the source terminal of the PMOS transistor MP 1 is electrically connected to the reference word line WL_R. The drain terminal of the PMOS transistor MP 0 and the resistor R 0 are jointly electrically connected to an input of the comparison circuit 233 . The drain terminal of the PMOS transistor MP 1 and the resistor R 1 are jointly electrically connected to another input of the comparison circuit 233 . The drain terminal and the source terminal of the NMOS transistor MN 0 R are respectively electrically connected to the resistor R 0 and the ground terminal (Gnd). The drain terminal and the source terminal of the NMOS transistor MN 1 R are respectively electrically connected to the resistor R 1 and the ground terminal (Gnd).

In the sense circuit 235 , the PMOS transistor MP 0 is controlled by a read bias voltage VRD, and the NMOS transistor MN 0 R is controlled by the read enable signal ENrd. In the replica sense circuit 231 d , the PMOS transistor MP 1 is controlled by the read bias voltage VRD, and the NMOS transistor MN 1 R is controlled by the read enable signal ENrd. The read bias voltage VRD is assumed to be constant to keep the PMOS transistors MP 0 and MP 1 turned on.

Once the read enable signal ENrd is at the high logic level, the NMOS transistors MN 0 R and MN 1 R are turned on, and the sensing current Isen and a replica sensing current Isen′ are conducted in response. The sensing current Isen flows through the PMOS transistor MP 0 , the resistor R 0 , and the NMOS transistor MN 0 R, and the replica sensing current Isen′ flows through the PMOS transistor MP 1 , the resistor R 1 and the NMOS transistor MN 1 R. Then, the sensing voltage Vsen can be obtained by timing the current value of the sensing current Isen and the resistance of the resistor R 0 , and the reference voltage Vref can be obtained by timing the current value of the replica sensing current Isen′ and the resistance of the resistor R 1 .

Because the resistance of the resistors R 0 and R 1 are equivalent, comparison between the sensing voltage Vsen and the reference voltage Vref is related to the current values of the sensing current Isen and the replica sensing current Isen′, which are actually dominated by the resistance of the storage element PCM and the replica storage element PCM′, respectively. For this reason, the comparison signal Scmp can represent the storage state of the storage element PCM.

In FIG. 9 , the comparison circuit 233 is a sense amplifier AMP being enabled by the comparison enable signal ENcmp. The sense amplifier AMP receives the sensing voltage Vsen from the sense circuit 235 , and the reference voltage Vref from the replica sense circuit 231 d . Then, the sense amplifier AMP outputs the comparison signal Scmp if the comparison enable signal ENcmp is at the high logic level.

FIG. 10 is a schematic block diagram illustration design of the read circuit according to the embodiment shown in FIG. 3C . The read circuit 43 includes a sense module 434 , a comparison circuit 433 and a voltage providing circuit 431 , and the sense module 434 further includes a first preset circuit 437 a , a second preset circuit 437 b , and a sense circuit 435 . The memory cell 41 includes a storage element PCM and a selector switch SEL.

The m-th bit line BLm, the first preset circuit 437 a , the second preset circuit 437 b , and the sense circuit 435 are electrically connected to each other through the dynamic control terminal Nvc. Voltage of the dynamic control terminal Nvc is changed in a stage based control manner during the read duration Trd. During the read duration Trd, the storage element PCM receives a predefined constant voltage V const _ L through the n-th word line WLn.

During a read operation, the comparison circuit 433 receives a sensing voltage Vsen from the sense circuit 435 . In addition, the voltage providing circuit 431 provides a reference voltage Vref to the comparison circuit 433 . After receiving the sensing voltage Vsen and the reference voltage Vref, the comparison circuit 433 accordingly generates a comparison signal Scmp to the controller 45 .

The comparison signal Scmp is corresponding to the storage state of the storage element PCM in the memory cell 41 . Later, the controller 45 determines data content of the storage element PCM based on the comparison signal Scmp.

In FIG. 10 , the comparison circuit 433 receives a comparison enable signal ENcmp from the controller 45 , the sense circuit 235 receives a read enable signal ENrd from the controller 45 , the first preset circuit 437 a receives a first enable signal ENpre 1 from the controller 45 , the second preset circuit 437 b receives a second enable signal ENpre 2 from the controller 45 . Basically, the circuits in FIG. 10 are similar to the ones in FIG. 6 except some polarities of the voltage are inversed so that current directions are opposite.

FIG. 11 is a schematic waveform diagram illustration signal control of the bock diagram shown in FIG. 9 . The first enable signal ENpre 1 , the second enable signal ENpre 2 , the read enable signal ENrd, and the comparison enable signal ENcmp are the same as the ones in FIG. 7 . Similarly, a voltage difference between the m-th bit line BLm and the n-th word line WLn is equivalent to the cell cross voltage ΔVmem.

Both the m-th bit line BLm and the n-th word line WLn are set at the default voltage (1.5V) before and after the read duration Trd. In FIG. 11 , the voltage of the m-th bit line BLm changes in different durations, and the voltage of the n-th word line WLn is set at the predefined constant voltage V const _ L (for example, 0.8V).

In the first duration T 1 , the voltage of the m-th word line BLm increases from the default voltage (1.5V) to a relatively high level so that the selector cross voltage ΔVsw is greater than the threshold voltage Vth of the selector switch SEL in the first duration T 1 . In consequence, the selector switch PCM is turned on at the end of the first duration T 1 . In the second duration T 2 , the voltage of the m-th bit line BLm decreases from the relatively high level to a relatively low level. During the post duration Tpost, the voltage of the m-th bit line WLm changes from the relatively low level to a middle level and basically remains at the middle level until the comparison enable signal ENcmp drops to the low logic level.

The n-th word line WLn starts to drop at time point t 1 to the predefined constant voltage V const _ L and remains at the predefined constant voltage V const _ L during the read duration Trd. After the read duration Trd, voltages of the m-th bit line BLm and the n-th word line WLn gradually return to the default voltage (1.5V).

FIG. 12 is a schematic flow diagram illustrating the control method applied to the memory device according to the embodiment of the present disclosure. The controller 45 receives a read command from a host (not shown) (step S 501 ), and the controller 45 sets the voltage of the n-th word line WLn at the predefined constant voltage V const _ L (step S 503 ).

Then, the read duration Trd and the preset Tpre duration start. In the preset duration Tpre, the first enable signal ENpre 1 firstly enables the first preset circuit 437 a . After being enabled, the first preset circuit 437 a conducts the m-th bit line BLm to the supply voltage terminal (Vcc) so that voltage of the m-th bit line BLm is increased (step S 505 ).

The second enable signal ENpre 2 then enables the second preset circuit 437 b . After being enabled, the second preset circuit 437 b conducts the m-th bit line BLm toward VRDP+|Vtp| so that voltage of the m-th bit line BLm is decreased (step S 507 ).

After the preset duration Tpre, the post duration Tpost starts. At the beginning of the post duration Tpost, the read circuit 23 waits a setting period before the sensing duration Tsen starts. The voltage of the dynamic control terminal Nvc becomes stable before the sensing duration Tsen starts, and the voltage of the dynamic control terminal Nvc is directly related to the sensing voltage Vsen. In the sensing duration Tsen, the comparison circuit 433 generates the comparison signal Scmp according to the sensing voltage Vsen and the reference voltage Vref (step S 509 ). Consequentially, the controller 45 determines the storage state of storage element PCM according to the comparison signal Scmp (step S 511 ).

FIG. 13 is a schematic block diagram illustrating a circuitry implementation of FIG. 10 . In the embodiment, the voltage providing circuit 431 can have replica circuits which are symmetric to the memory cell 41 , the sense circuit 435 , the first preset circuit 437 a , and the second preset circuit 437 b.

In FIG. 13 , the voltage providing circuit 231 is assumed to include a replica memory cell 431 c , a replica sense circuit 431 d , a first replica preset circuit 431 a , and a second replica preset circuit 431 b . The replica memory cell 231 c includes a replica storage element PCM′ and a replica selector switch SEL′. The replica storage element PCM′ is electrically connected to a reference word line WL_R, and the replica selector switch SEL′ is electrically connected to the replica sense circuit 431 d . The first replica preset circuit 431 a and the second replica preset circuit 431 b respectively receive the first enable signal ENpre 1 and the second enable signal ENpre 2 from the controller 45 .

The operations of the circuits in the voltage providing circuit 431 are basically similar to the ones described in FIG. 9 for the voltage providing circuit 231 . Similarly, the storage element PCM in the replica memory cell 431 c is assumed to have a resistance equivalent to a middle value of the resistance when the storage element PCM is highly conductive and the resistance when the storage element PCM is highly resistive.

In FIG. 13 , the first preset circuit 437 a includes an inverter INV 0 P, a PMOS transistor MP 0 P and an NMOS transistor MN 0 P. Similarly, the first replica preset circuit 431 a includes an inverter INV 1 P, a PMOS transistor MP 1 P and an NMOS transistor MN 1 P. The PMOS transistors MP 0 P and MP 1 P are both controlled by a first bias voltage VRDN, and the NMOS transistors MN 0 P and MN 1 P are both controlled by the inversed enable signal ENpre 1 . The first bias voltage VRDN is assumed to be constant to keep the NMOS transistors MN 0 P and MN 1 P turned on.

Once the first enable signal ENpre 1 is at the high logic level, the PMOS transistors MP 0 P and MP 1 P are turned on, and the first preset current Ipre 1 and a first replica preset current Ipre 1 ′ are conducted in response. The first preset current Ipre 1 originates from the supply voltage terminal (Vcc), flows through the PMOS transistor MP 0 P and the NMOS transistor MN 0 P to the m-th bit line BLm. Meanwhile, the first replica preset current Ipre 1 ′ originates from the supply voltage terminal (Vcc), flows through the PMOS transistor MP 1 P and the NMOS transistor MN 1 P to the reference bit line BL_R.

In FIG. 13 , the second preset circuit 437 b includes a PMOS transistor MP 2 P and an NMOS transistor MN 2 P. Similarly, the second replica preset circuit 431 b includes a PMOS transistor MP 3 P and an NMOS transistor MN 3 P. In the second preset circuit 437 b , the PMOS transistor MP 2 P is controlled by a second bias voltage VRDP, and the NMOS transistor MN 2 P is controlled by the second enable signal ENpre 2 . In the second replica preset circuit 431 b , the PMOS transistor MP 3 P is controlled by the second bias voltage VRDP, and the NMOS transistor MN 3 P is controlled by the second enable signal ENpre 2 . The second bias voltage VRDP is assumed to be constant to keep the PMOS transistors MP 2 P and MP 3 P turned on.

Once the second enable signal ENpre 2 is at the high logic level, the NMOS transistors MN 2 P and MN 3 P are turned on, and the second preset current Ipre 2 and a second replica preset current Ipre 2 ′ are conducted in response. Starting from the m-th bit line BLm, the second preset current Ipre 2 flows through the PMOS transistor MP 2 P and the NMOS transistor MN 2 P to the ground terminal (Gnd). Starting from the reference bit line BL_R, the second replica preset current Ipre 2 ′ flows through the PMOS transistor MP 3 P and the NMOS transistor MN 3 P to the ground terminal (Gnd).

In FIG. 13 , the sense circuit 435 includes an inverter INV 0 , a PMOS transistor MP 0 R, a resistor R 0 , and an NMOS transistor MN 0 . Similarly, the replica sense circuit 431 d includes an inverter INV 1 , a PMOS transistor MP 1 R, a resistor R 1 , and an NMOS transistor MN 1 . The resistances of the resistor R 0 and R 1 are equivalent. In the sense circuit 435 , the PMOS transistor MP 0 R is controlled by the read enable signal ENrd, and the NMOS transistor MN 0 is controlled by the read bias voltage VRD. In the replica sense circuit 431 d , the PMOS transistor MP 1 R is controlled by the read enable signal ENrd, and the NMOS transistor MN 1 is controlled by the read bias voltage VRD. The read bias voltage VRD is assumed to be constant to keep the NMOS transistors MN 0 and MN 1 turned on.

Once the read enable signal ENrd is at the high logic level, the PMOS transistors MP 0 R and MP 1 R are turned on, and the sensing current Isen and a replica sensing current Isen′ are conducted in response. The sensing current Isen originating from the supply voltage terminal (Vcc) flows through the PMOS transistor MP 0 R, the resistor R 0 , and the NMOS transistor MN 0 , and the replica sensing current Isen′ originating from the supply voltage terminal (Vcc) flows through the PMOS transistor MP 1 R, the resistor R 1 and the NMOS transistor MN 1 . Then, the sensing voltage Vsen can be obtained by a voltage difference between the supply voltage terminal (Vcc) and timing result of the current value of the sensing current Isen and the resistance of the resistor R 0 ; and the reference voltage Vref can be obtained by another voltage difference between the supply voltage terminal (Vcc) and timing result of the current value of the replica sensing current Isen′ and the resistance of the resistor R 1 .

Because the resistance of the resistors R 0 and R 1 are equivalent, comparison between the sensing voltage Vsen and the reference voltage Vref is related to the current values of the sensing current Isen and the replica sensing current Isen′, which are actually dominated by the resistance of the storage element PCM and the replica storage element PCM′, respectively. For this reason, the comparison signal Scmp can represent the storage state of the storage element PCM.

In FIG. 13 , the comparison circuit 433 is a sense amplifier AMP. The sense amplifier AMP receives the sensing voltage Vsen from the sense circuit 435 , and receives the reference voltage Vref from the replica sense circuit 431 d . Then, the sense amplifier AMP outputs the comparison signal Scmp.

According to the embodiments of the present disclosure, the cell cross voltage ΔVmem is dynamically adjusted in a stage based manner. The first duration T 1 is utilized to enlarge the cell cross voltage ΔVmem so that the selector switch SEL can be turned on. The second duration T 2 is utilized to shrink the cell cross voltage ΔVmem so that the selector SEL can stay at the ON state without causing read disturb at the storage element PCM. Then, the storage state of the storage element PCM is acquired in the post duration Tpost. In practical application, the storage elements can be other types of memristor such as resistive random-access memory (RRAM or ReRAM), magnetoresistive random-access memory (MRAM) and so forth.

While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.