Inventor

Hsin-Yi Ho

Inventor
Hsinchu, TW

Overview

40→
Patents
2002–2021
Patent span
Physics
Primary field (CPC G)

Patents· 40 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores70%
G06FElectric digital data processing13%
G05FSystems for regulating electric or magnetic variables2%
H01LSemiconductor devices2%
H03KPulse technique2%
H03MCoding2%
H10BElectronic memory devices2%
H10DInorganic electric semiconductor devices2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
11,049,557Leakage current compensation in crossbar array202110,497,437Decoding scheme for 3D cross-point memory array201910,297,316Phase change memory apparatus and read control method to reduce read disturb and sneak current phenomena20199,779,813'Phase change memory array architecture achieving high write/read speed'20179,646,692'Programming verify for nonvolatile memory'20179,558,818'Memory and memory managing method'20179,507,663'Memory device and operation method'20169,471,485'Difference L2P method'20169,152,557'Program method, data recovery method, and flash memory using the same'20159,146,569'Low drop out regulator and current trimming device'20159,009,566'Outputting information of ECC corrected bits'20158,947,961'Management of non-volatile memory'20158,738,844'Program method, data recovery method, and flash memory using the same'20148,456,906'Memory and operation method therefor'20138,258,815'Clock generator circuits for generating clock signals'20128,259,484'3D chip selection for shared input packages'20128,239,619'Method and apparatus for high-speed byte-access in block-based flash memory'20128,194,462'Integrated circuit of device for memory cell'20128,189,357'Memory with multiple reference cells'20128,094,494'Memory and operation method therefor'20128,077,513'Method and apparatus for programming a multi-level memory'20118,045,403'Programming method and memory device using the same'20118,031,523'Memory and reading method thereof'20118,023,333'Reading method for MLC memory and reading circuit using the same'20117,961,513'Method for programming a multilevel memory'20117,835,203'Programming method and memory device using the same'20107,812,754'Digital to analog converter and method thereof'20107,796,436'Reading method for MLC memory and reading circuit using the same'20107,694,650'Exhaust monitoring cup'20107,649,772'Memory and method for programming in multiple storage region multi-level cells'20107,580,292'Method for programming a multilevel memory'20097,539,058'Non-volatile memory and operating method thereof'20097,474,565'Programming scheme for non-volatile flash memory'20097,397,705'Method for programming multi-level cell memory array'20087,251,166'Method for verifying a programmed flash memory'20076,845,052'Dual reference cell sensing scheme for non-volatile memory'20056,665,216'Apparatus and system for reading non-volatile memory with dual reference cells'20036,563,735'NOR-structured semiconductor memory device'20036,545,911'Flash memory erase method'20036,421,267'Memory array architecture'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2021Patents assigned to MACRONIX INT CO LTD (39)· patent assignee history
2002–2021Based in Hsinchu, TW· patent location history
2011–2014Patents assigned to HO HSIN-YI (8)· patent assignee history
2011–2015Patents assigned to HUNG CHUN-HSIUNG (7)· patent assignee history
2012–2013Patents assigned to CHOU YUN-CHEN (2)· patent assignee history
2012–2015Patents assigned to HO HSIN YI (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MACRONIX INT CO LTD392002–2021
HO HSIN-YIself82011–2014
HUNG CHUN-HSIUNG72011–2015
CHOU YUN-CHEN22012–2013
HO HSIN YIself22012–2015
Locations
LocationPatentsSpan
Hsinchu, TW402002–2021