Semiconductor device

The disclosure of Japanese Patent Application No. 2013-119998 filed on Jun. 6, 2013 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

This invention relates to semiconductor devices, and for example, is a technique applicable to a semiconductor device in which a first semiconductor chip and a second semiconductor chip are stacked over a wiring board.

One of the methods for packaging a plurality of semiconductor chips over a wiring board employs stacking a second semiconductor chip over a first semiconductor chip. Japanese Unexamined Patent Publication No. 2005-183934 discloses a technique of coupling a second semiconductor chip to a first semiconductor chip through bumps.

On the other hand, a method for coupling a semiconductor chip to another semiconductor chip by using through-silicon vias is under study. Through-silicon vias are provided so as to pass through a substrate of the semiconductor chip along the thickness of the substrate. For example, a method disclosed in Japanese Unexamined Patent Publication No. 2011-243724 includes stacking memory chips, each having through-silicon vias formed therein, and coupling these memory chips using the through-silicon vias.

In Japanese Unexamined Patent Publication No. 2011-243724, the lowermost memory chip is coupled to a wiring board through solder bumps. Around the lowermost memory chip, a frame-like metal member is provided so as to enclose the memory chip. In addition, a metal substrate is mounted over the uppermost memory chip with an adhesive member therebetween. The frame-like member in the publication is provided in order to increase the rigidity of the wiring board.

If a second semiconductor chip is mounted over a first semiconductor chip, the heat dissipation performance of the second semiconductor chip is deteriorated. Hence, the inventors of the present invention have recognized the need for preventing heat from transferring to the second semiconductor chip as much as possible. Especially in the case where the first semiconductor chip and the second semiconductor chip are coupled to each other with through-silicon vias provided in the first semiconductor chip, the inventors have recognized the need for preventing heat generated in the first semiconductor chip from transferring to the second semiconductor chip through the through-silicon vias. The other problems and novel features of the present invention will become apparent from the following description in the present specification and the accompanying drawings.

According to an embodiment, a first semiconductor chip is mounted over a first surface of a wiring board and is rectangular in plan. The first semiconductor chip has an element formation surface facing the first surface of the wiring board. The first semiconductor chip is coupled to the wiring board through connection terminals. The first semiconductor chip has a plurality of first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). A second semiconductor chip is disposed over the first semiconductor chip and is electrically coupled to the first through-silicon vias of the first semiconductor chip. The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of the connection terminals are positioned between the first circuit formation area and the through-silicon via area.

This embodiment can reduce the transfer of heat, which is generated in the first semiconductor chip, to the second semiconductor chip through the through-silicon vias.

FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to an embodiment.

FIG. 2 schematically illustrates the relative positions of a wiring board, a first semiconductor chip, and a second semiconductor chip which form the semiconductor device.

FIG. 3 is a cross-sectional view to illustrate the configuration of a part in which the first semiconductor chip is coupled to the wiring board and a part in which the first semiconductor chip is coupled to the second semiconductor chip.

FIG. 4 illustrates an exemplary arrangement of first through-silicon vias in a through-silicon via area.

FIG. 5 illustrates an exemplary shape of an opening of the wiring board.

FIGS. 6A to 6C illustrate a method for manufacturing the semiconductor device.

FIGS. 7A and 7B illustrate the method for manufacturing the semiconductor device.

FIG. 8 is a plan view to illustrate the configuration of the wiring board.

FIG. 9 is a cross-sectional view showing the configuration of a semiconductor device according to the first modification.

FIG. 10 illustrates the cross-sectional structure of second semiconductor chips.

FIG. 11 is a plan view showing the configuration of a semiconductor device according to the second modification.

FIG. 12 is a plan view of an electronic device according to the third modification.

FIG. 13 is a block diagram showing the functional configuration of the electronic device shown in FIG. 12 .

With reference to the accompanying drawings, an embodiment will be described below. Note that in all drawings like components are denoted by like numerals and therefore the explanations thereof will not be reiterated if not necessary.

[Embodiment]

FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device SD according to the first embodiment. FIG. 2 schematically illustrates the relative positions of a wiring board IP, a first semiconductor chip SC 1 , and a second semiconductor chip SC 2 which form the semiconductor device SD. FIG. 1 corresponds to a cross section taken along A-A′ in FIG. 2 . The semiconductor device SD according to the first embodiment includes a wiring board IP, a first semiconductor chip SC 1 , and a second semiconductor chip SC 2 .

The first semiconductor chip SC 1 is mounted over a first surface of the wiring board IP and is rectangular in plan. The first semiconductor chip SC 1 has an element formation surface SFC 11 facing the first surface. The first semiconductor chip SC 1 is coupled to the wiring board IP through connection terminals CUP.

The first semiconductor chip SC 1 has a plurality of first through-silicon vias TSV 1 . Each of the first through-silicon vias TSV 1 is arranged on any of grid points arranged in m rows and n columns (m>n). In the example shown in FIGS. 1 and 2 , a direction in parallel with long sides SID 11 , SID 13 of the first semiconductor chip SC 1 (X-direction in FIG. 2 ) is defined as a column direction, and a direction perpendicular to the long sides SID 11 , SID 13 (Y-direction in FIG. 2 ) is defined as a row direction. However, the row direction can be a direction in parallel with short sides SID 12 , SID 14 of the first semiconductor chip SC 1 .

The second semiconductor chip SC 2 is disposed over the first semiconductor chip SC 1 and is electrically coupled to the first through-silicon vias TSV 1 of the first semiconductor chip SC 1 .

The first semiconductor chip SC 1 also has a first circuit formation area LGC 1 . A first circuit is formed in the first circuit formation area LGC 1 . The first circuit performs signal processing while communicating with the second semiconductor chip SC 2 . In plan view, the first circuit formation area LGC 1 does not overlap with an area defined by coupling the outermost grid points arranged in m rows and n columns (hereinafter, referred to as a through-silicon via area TSVA 1 ). In plan view, some of the connection terminals CUP are positioned between the first circuit formation area LGC 1 and the through-silicon via area TSVA 1 . This arrangement allows at least a portion of heat generated in the first circuit formation area LGC 1 to transfer to the wiring board IP through the connection terminals CUP. Hence, heat transferring from the first semiconductor chip SC 1 to the second semiconductor chip SC 2 through the first through-silicon vias TSV 1 can be reduced.

As described above, the element formation surface SFC 11 of the first semiconductor chip SC 1 faces the first surface of the wiring board IP. This arrangement makes the second semiconductor chip SC 2 less susceptible to heat from the first semiconductor chip SC 1 in comparison with the case where the element formation surface SFC 11 faces the second semiconductor chip SC 2 . This arrangement also makes it easy for heat to transfer from the first semiconductor chip SC 1 to the wiring board IP.

The configuration of the semiconductor device SD will be described in detail below.

Referring to FIG. 1 , the configuration of the semiconductor device SD will be described. The wiring board IP is, for example, a resin interposer having wiring layers on at least both sides. The wiring board IP may have two wiring layers or four or more wiring layers. The thickness of the wiring board IP is, for example, from 100 μm to 300 μm. However, the wiring board IP can be thicker or thinner than those thicknesses. The wiring on the side of the first surface (i.e., a side where the first semiconductor chip SC 1 is mounted) of the wiring board IP includes electrodes IEL (which will be described later by referring to FIG. 3 ). The electrodes IEL are electrically coupled to the first semiconductor chip SC 1 .

The wiring board IP has a wiring layer on a second surface, which is the opposite side of the first surface, and electrodes LND are disposed over the wiring layer on the second surface. The electrodes LND are coupled to the electrodes IEL through at least coupling members provided in the wiring board IP (e.g., a conductive layer provided in a through hole). External connection terminals SB are provided over the electrodes LND. The external connection terminals SB are used to attach the semiconductor device SD to a circuit board (e.g., a motherboard). The external connection terminals SB are, for example, solder balls. The electrodes LND and external connection terminals SB are arranged at least along the edges of the wiring board IP. However, the electrodes LND and external connection terminals SB can be additionally disposed at the center of the wiring board IP. In this case, the electrodes LND and external connection terminals SB may be provided across the entire surface of the wiring board IP, or a group of the external connection terminals SB arranged at the center of the wiring board IP and a group of the external connection terminals SB arranged at the edges of the wiring board IP may have a space therebetween, which is larger than a distance between the grid points of the respective groups.

As described above, the first semiconductor chip SC 1 is coupled to the electrodes IEL of the wiring board IP. In the example shown in the drawings, the first semiconductor chip SC 1 is coupled to the electrodes IEL via connection terminals CUP. The connection terminals CUP are, for example, conductor posts made of metal, such as Cu. However, solder bumps can be also used as the connection terminals.

The first semiconductor chip SC 1 has a thickness thinner than the wiring board IP or, for example, is half the thickness of the wiring board IP or thinner. The thickness of the first semiconductor chip SC 1 is, for example, 50 μm to 60 μm, but is not limited thereto.

The first semiconductor chip SC 1 is thinner than the second semiconductor chip SC 2 . Accordingly, the first through-silicon vias TSV 1 are relatively short, thereby more easily transfer heat from the first semiconductor chip SC 1 to the second semiconductor chip SC 2 .

Over the element formation surface SFC 11 of the first semiconductor chip SC 1 , at least one logic circuit (e.g., a circuit in the first circuit formation area LGC 1 ) is formed. This logic circuit is coupled to the second semiconductor chip SC 2 via the first through-silicon vias TSV 1 .

The second semiconductor chip SC 2 is, for example, a memory chip. The memory included in the second semiconductor chip SC 2 may be a Wide I/O memory or a double data rate (DDR) memory (such as DDR2 and DDR3). However, the second semiconductor chip SC 2 can be a semiconductor chip with a logic circuit or a semiconductor chip having both a logic circuit and a memory circuit. The second semiconductor chip SC 2 has an element formation surface SFC 21 facing a back surface SFC 12 of the first semiconductor chip SC 1 .

In the example shown in FIG. 1 , the through-silicon via area TSVA 1 is aligned with the center of the first semiconductor chip SC 1 , the center of the second semiconductor chip SC 2 , and the center of the wiring board IP as viewed in a cross section taken along a short side of the first semiconductor chip SC 1 . However, the relative positions of the first semiconductor chip SC 1 , second semiconductor chip SC 2 , and wiring board IP are not limited to the example shown in FIG. 1 .

The space between the first semiconductor chip SC 1 and the first surface of the wiring board IP is sealed with first sealing resin UFR 1 . The space between the second semiconductor chip SC 2 and the first surface of the wiring board IP is also sealed with second sealing resin UFR 2 . Consequently, the first sealing resin UFR 1 is covered with the second sealing resin UFR 2 . The first sealing resin UFR 1 may be a die attachment film (DAF) or may be formed by dripping liquid resin. The second sealing resin UFR 2 is formed by, for example, dripping liquid resin.

The thickness of the first sealing resin UFR 1 , in other words, the distance between the first semiconductor chip SC 1 and wiring board IP, is preferably less than the thickness of the second sealing resin UFR 2 , in other words, the distance between the first semiconductor chip SC 1 and second semiconductor chip SC 2 . The thinner first sealing resin UFR 1 allows more amounts of heat to be transferred from the first semiconductor chip SC 1 to the wiring board IP, and the thicker second sealing resin UFR 2 can decrease the amount of heat transferring from the first semiconductor chip SC 1 to, the second semiconductor chip SC 2 .

In addition, the thermal conductivity of the first sealing resin UFR 1 is preferably higher than that of the second sealing resin UFR 2 . The first sealing resin UFR 1 with higher thermal conductivity can further increase the amount of heat transferring from the first semiconductor chip SC 1 to the wiring board IP. Consequently, the amount of heat transferring from the first semiconductor chip SC 1 to the second semiconductor chip SC 2 through the second sealing resin UFR 2 is further decreased.

The first surface of the wiring board IP, the first semiconductor chip SC 1 , the second sealing resin UFR 2 , and the second semiconductor chip SC 2 are sealed with sealing resin MDR 1 . In the example shown in FIG. 1 , the sealing resin MDR 1 has side surfaces flush with the side surfaces of the wiring board IP. However, as viewed in plan view, the side surfaces of the sealing resin MDR 1 can be positioned more inwardly than the side surfaces of the wiring board IP.

With reference to FIG. 2 , the configuration of the semiconductor device SD will be described. The first semiconductor chip SC 1 is rectangular in plan and has a long side SID 11 , a short side SID 12 , a long side SID 13 , and a short side SID 14 . The first through-silicon vias TSV 1 are located in a through-silicon via area TSVA 1 defined by coupling the outermost grid points arranged in m rows and n columns, and arranged on the grid points, respectively. The through-silicon via area TSVA 1 is a rectangle having long sides (i.e., the row direction) in parallel with the short sides SID 12 , SID 14 of the first semiconductor chip SC 1 . The first circuit formation area LGC 1 is located between a long side of the through-silicon via area TSVA 1 and the short side SID 12 . According to this arrangement, the first circuit formation area LGC 1 can be located apart from the through-silicon via area TSVA 1 . Among the circuits possessed by the first semiconductor chip SC 1 , the first circuit in the first circuit formation area LGC 1 generates the greatest amount of heat. Hence, an area where the temperature rises to the highest in the first semiconductor chip SC 1 is an area overlapping with the first circuit in plan view. The first circuit is, for example, a central processing unit (CPU).

The long sides of the through-silicon via area TSVA 1 can be in parallel with the long sides SID 11 , SID 13 of the first semiconductor chip SC 1 .

As viewed in a cross section taken along a short side of the first semiconductor chip SC 1 , the center (or center of gravity) of the first semiconductor chip SC 1 is aligned with the center (or center of gravity) of the wiring board IP.

In addition, some of the connection terminals CUP (i.e., connection terminals CUP 1 ) are disposed along the four sides (long side SID 11 , short side SID 12 , long side SID 13 , and short side SID 14 ) of the first semiconductor chip SC 1 . In the example shown in FIG. 2 , the connection terminals CUP 1 are disposed along the four sides of the first semiconductor chip SC 1 so as to form multiple lines.

Some of the connection terminals. CUP (i.e., connection terminals CUP 2 ) are located between the first circuit formation area LGC 1 and the through-silicon via area TSVA 1 . Due to this arrangement, at least a portion of heat generated in the first circuit formation area LGC 1 can escape to the wiring board IP through the connection terminals CUP 2 before reaching the first through-silicon vias TSV 1 . Even if stress is applied onto the first semiconductor chip SC 1 , the connection terminal CUP 2 can prevent the through-silicon via area TSVA 1 from suffering warpage. Therefore, it can be prevented that the substrate SUB 1 of the first semiconductor chip SC 1 becomes cracked starting from the through-silicon via area TSVA 1 . The connection terminals CUP 2 can have a larger cross-sectional area than the connection terminals CUP 1 . The larger cross-sectional area of the connection terminals CUP 2 increases the aforementioned effects. In the example shown in FIG. 2 , the connection terminals CUP 2 are arranged so as to surround the through-silicon via area TSVA 1 .

In plan view, the total area of the connection terminals CUP 1 is larger than that of the first through-silicon vias TSV 1 . This makes it harder for heat to transfer from the first semiconductor chip SC 1 to the second semiconductor chip SC 2 , while making it easier for heat to transfer from the first semiconductor chip SC 1 to the wiring board IP.

At least some of the connection terminals CUP 2 can be coupled to the first through-silicon vias TSV 1 through the lines and vias formed in a multilevel interconnection layer MIL of the first semiconductor chip SC 1 . In this case, the connection terminals CUP 2 directly coupled to the electrodes EL 11 are coupled to a power electrode or a ground electrode of the second semiconductor chip SC 2 .

Other connection terminals CUP may be provided on the outside of the connection terminals CUP 2 . The connection terminals CUP can be also coupled to the first through-silicon vias TSV 1 through the lines and vias formed in the multilevel interconnection layer MIL of the first semiconductor chip SC 1 . These connection terminals can be also used, for example, as terminals for testing the second semiconductor chip SC 2 .

The electrodes IEL over the wiring board IP are also arranged so as to correspond with the connection terminals CUP.

The second semiconductor chip SC 2 extends out further than at least one side of the first semiconductor chip SC 1 in plan view. In the example shown in FIG. 2 , the long sides of the second semiconductor chip SC 2 are in parallel with the short side SID 12 of the first semiconductor chip SC 1 .

In a case where the second semiconductor chip SC 2 is a memory chip, the first through-silicon vias TSV 1 are arranged in accordance with specifications set out in JEDEC JESD 229. Accordingly, four through-silicon via areas TSVA 1 are arranged in two rows and two columns. In addition, the first semiconductor chip SC 1 has a control circuit formation area CNT at areas around the through-silicon via areas TSVA 1 in plan view. In the control circuit formation areas CNT, a memory control circuit is formed to control the memory of the second semiconductor chip SC 2 . Among coupling paths for coupling the memory control circuit and the second semiconductor chip SC 2 , this arrangement can shorten coupling paths formed in the multilevel interconnection layer MIL of the first semiconductor chip SC 1 .

In plan view, a second circuit formation area LGC 2 is arranged opposite to the first circuit formation area LGC 1 with respect to the through-silicon via areas TSVA 1 . A second circuit is formed in the second circuit formation area LGC 2 . The second circuit generates a lesser amount of heat than the first circuit, but the amount of heat generation is greater than that of the circuits in the control circuit formation area CNT. The second circuit is, for example, a graphics processing unit (GPU).

Furthermore, in plan view, an I/O circuit IF is formed between a short side close to the first circuit formation area LGC 1 (i.e., short side SID 12 in FIG. 2 ) and the first circuit formation area LGC 1 . Another I/O circuit IF is formed between the connection terminals CUP 1 disposed along the short side SID 14 and the second circuit formation area LGC 2 . The amount of heat generated by the I/O circuit IF is smaller than the amount of heat generated by the second circuit, but greater than the amount of heat generated by the circuits in the control circuit formation area CNT. The I/O circuit IF is also formed between a short side close to the second circuit formation area LGC 2 (i.e., short side SID 14 in FIG. 2 ) and the second circuit formation area LGC 2 .

FIG. 3 is a cross-sectional view to illustrate the configuration of a coupling part of the first semiconductor chip SC 1 and the wiring board IP and a coupling part of the first semiconductor chip SC 1 and the second semiconductor chip SC 2 .

The first semiconductor chip SC 1 is made up with a substrate SUB 1 . The substrate SUB 1 is a semiconductor substrate, such as a silicon substrate. Transistors Tr 1 are formed over the substrate SUB 1 . Over the surface of the substrate SUB 1 where the transistors Tr 1 are formed, a multilevel interconnection layer MIL 1 is formed. Various circuits of the first semiconductor chip SC 1 are configured with lines in the multilevel interconnection layer MIL 1 and the transistors Tr 1 .

First through-silicon vias TSV 1 are formed in the substrate SUB 1 . The first through-silicon vias TSV 1 are made of a conductive material, such as copper, so as to pass through the substrate SUB 1 . An insulating film (not shown) is formed between the first through-silicon vias TSV 1 and the substrate SUB 1 .

Over the uppermost wiring layer of the multilevel interconnection layer MIL 1 , electrodes EL 11 are formed. Over each electrode EL 11 , a connection terminal CUP, which is a conductor post typified by a Cu pillar, is formed. The connection terminals CUP are coupled to electrodes IEL on the first surface of the wiring board IP with solder SLD 1 therebetween. An insulating layer SR, such as a solder resist layer, is provided over the first surface of the wiring board IP. The insulating layer SR has an opening SRO at a position overlapping with the electrodes TEL. The periphery of the electrodes IEL may be covered with the insulating layer SR or may be exposed from the insulating layer SR.

Some electrodes EL 11 are coupled through the lines and vias in the multilevel interconnection layer MIL 1 to ends of the first through-silicon vias TSV 1 on the side of the element formation surface SFC 11 . The other ends of the first through-silicon vias TSV 1 on the side of the back surface SFC 12 are coupled to connection terminals EL 21 of the second semiconductor chip SC 2 through solder SLD 2 .

In the example shown in FIG. 3 , the connection terminals EL 21 of the second semiconductor chip SC 2 overlap with the first through-silicon vias TSV 1 of the first semiconductor chip SC 1 in plan view. However, at least some of the connection terminals EL 21 do not need to overlap with the corresponding first through-silicon vias TSV 1 in plan view. In this case, at least one wiring layer is formed over the back surface SFC 12 of the first semiconductor chip SC 1 . Through the wiring layer, the connection terminals EL 21 are coupled to the first through-silicon vias TSV 1 .

The first through-silicon vias TSV 1 are arranged with a smaller pitch than the pitch between the connection terminals CUP. Arranging the connection terminals CUP with a relatively large pitch can make the connection terminals CUP thicker than the first through-silicon vias TSV 1 . Making the connection terminals CUP thicker can enhance the mechanical reliability when the first semiconductor chip SC 1 is coupled to the wiring board IP. In addition, the connection terminals CUP can be increased in height. In the example shown in FIG. 3 , in plan view, some of the first through-silicon vias TSV 1 at least partially overlap with the connection terminals CUP. This can ease restrictions on the layout of the connection terminals CUP and the first through-silicon vias TSV 1 . Alternatively, the first through-silicon vias TSV 1 can be designed not to overlap with any of the connection terminals CUP.

FIG. 4 , illustrates an exemplary arrangement of the first through-silicon vias TSV 1 in a through-silicon via area TSVA 1 . As shown in FIG. 4 , the first through-silicon vias TSV 1 are arranged on grid points, respectively, in the through-silicon via area TSVA 1 . The long side of the through-silicon via area TSVA 1 is, for example, ten or more times longer than the short side thereof. In the grid pattern where the first through-silicon vias TSV 1 are arranged, adjacent four grid points form, for example, a square, a rectangle, or a parallelogram, but the shape is not limited thereto. In addition, it is not necessary to arrange the first through-silicon vias TSV 1 on all the grid points. The ratio of grid points on which the first through-silicon vias TSV 1 are not arranged to all the grid points is, for example, 10% or less.

FIG. 5 illustrates an exemplary shape of the opening SRO of the wiring board IP. In the example shown in FIG. 5 , the opening SRO is not provided for every single electrode IEL, but is provided as a common opening for plural electrodes IEL. Specifically, a first opening SRO is continuously formed along the edges of the wiring board IP so as to overlap with the electrodes IEL corresponding to the connection terminals CUP 1 . Then, a second opening SRO is formed at the center of the wiring board IP so as to overlap with electrodes IEL corresponding to the connection terminals CUP 2 and electrodes IEL corresponding to connection terminals CUP 3 . In the example shown in FIG. 5 , the ends of the second opening SRO are coupled to the first opening SRO. However, the first opening SRO and second opening SRO can be separated from each other. Alternatively, the second opening SRO can be split into plural openings that are each allocated to each through-silicon via area TSVA 1 .

Referring to FIGS. 6 to 8 , a method for manufacturing the semiconductor device SD will be described. First, a first semiconductor chip SC 1 and a second semiconductor chip SC 2 are prepared. The first semiconductor chip SC 1 and the second semiconductor chip SC 2 are formed, for example, in the following manner.

First, an element isolation film is formed on a substrate in the form of a wafer (e.g., a substrate SUB 1 ). With this element isolation film, element formation areas are isolated. The element isolation film is formed by, for example, an STI method, but also can be formed by a LOCOS method. Then, a gate insulating film and a gate electrode are formed in the element formation area of the substrate SUB 1 . The gate insulating film may be a silicon oxide film or a High-k dielectric film (e.g., a hafnium silicate film) with a dielectric constant higher than that of silicon oxide films. If the gate insulating film is a silicon oxide film, the gate electrode is made of a polysilicon film. If the gate insulating film is a High-k dielectric film, the gate electrode is made of a laminated film of a metal film (e.g., TiN) and a polysilicon film. In the case where the gate electrode is made of polysilicon, a polysilicon resistor can be formed over the element isolation film in the course of forming the gate electrode.

Next, an extension region for a source and a drain is formed in the element formation area of the substrate. Then, a sidewall is formed on the sides of the gate electrode. Then, an impurity region to be a source and a drain is formed in the element formation area of the substrate. Thus, a transistor (e.g., a transistor Tr 1 ) is formed over the substrate.

Subsequently, a multilevel interconnection layer (e.g., multilevel interconnection layer MIL 1 ) is formed over the element isolation film and transistors. Electrodes (e.g., electrodes EL 11 ) are formed over the uppermost layer of the multilevel interconnection layer. Then, a protection insulating film (passivation film) is formed over the multilevel interconnection layer. An opening is formed in the protection insulating film over the electrodes.

In the course of forming the multilevel interconnection layer, a capacitative element, which serves as a memory cell, is also formed for the second semiconductor chip SC 2 .

Connection terminals CUP are formed over the electrodes EL 11 of the first semiconductor chip SC 1 . If the connection terminals CUP are conductor posts, the connection terminals CUP are formed by, for example, plating. Over the connection terminals CUP, a solder layer is formed.

Then, first through-silicon vias TSV 1 are formed in the first semiconductor chip SC 1 at any point in time in the aforementioned steps. For example, the first through-silicon vias TSV 1 may be formed before the transistor Tr 1 is formed or after the electrode EL 11 and protection insulating film have been formed. Alternatively, the first through-silicon vias TSV 1 can be formed after the transistor Tr 1 and multilevel interconnection layer have been partially formed. In this case, ends of the first through-silicon vias TSV 1 on the side of the element formation surface SFC 11 are coupled to any wiring layer of the multilevel interconnection layer. In addition, electrodes may be formed over the back surface SFC 12 of the first semiconductor chip SC 1 to couple to the first through-silicon vias TSV 1 , at any point in time.

Subsequently, the wafer is cut into semiconductor chips.

Wiring boards IP as shown in FIG. 8 are prepared. FIG. 8 shows that a plurality of wiring boards IP coupled to each other with scribe regions SL (see FIGS. 6A, 6B, 6C and other drawings).

Then, as shown in FIG. 6A , a first semiconductor chip SC 1 is mounted over a wiring board IP. At this point, connection terminals CUP are coupled to electrodes IEL, and first sealing resin UFR 1 is formed. The first sealing resin UFR 1 can be formed by using film-shaped resin, such as a die attachment film (DAF), or can be formed by dripping liquid resin. In the former case, the first sealing resin UFR 1 is applied over the wiring board IP before the first semiconductor chip SC 1 is mounted over the wiring board IP. This can make it easier to form the planar shape of the first sealing resin UFR 1 as described with reference to FIG. 2 . In the latter case, the first sealing resin UFR 1 is applied after the first semiconductor chip SC 1 has been mounted over the wiring board IP. Also in the latter case, the end part of the first sealing resin UFR 1 forms a fillet extending at least downward along the sides of the first semiconductor chip SC 1 .

Next, as shown in FIG. 6B , a second semiconductor chip SC 2 is mounted over the first semiconductor chip SC 1 . At this point, the first through-silicon vias TSV 1 of the first semiconductor chip SC 1 are coupled to the connection terminals EL 21 of the second semiconductor chip SC 2 . The second sealing resin UFR 2 is formed afterward. The second sealing resin UFR 2 is formed, for example, by dripping liquid resin. Hence, the end part of the second sealing resin UFR 2 forms a fillet extending at least downward along the sides of the second semiconductor chip SC 2 .

The steps shown in FIGS. 6A and 6B are performed on each of the wiring boards IP.

Subsequently, as shown in FIG. 6C , sealing resin MDR 1 is formed. The sealing resin MDR 1 is formed over the wiring boards IP all at once (batch molding method), for example, by using a single cavity (not shown) formed by a set of mold components (not shown).

In the step of forming the sealing resin MDR 1 , a cavity can be provided for every wiring board IP. In this case, a stack of the first semiconductor chip SC 1 and the second semiconductor chip SC 2 is sealed for every individual wiring board IP (individual molding method). In this case, since each of the wiring boards IP is covered with an individual cavity (not shown), the side surfaces of the wiring board IP are not flush with the side surfaces of the sealing resin MDR 1 .

Then, as shown in FIG. 7A , external connection terminals SB are provided to every wiring board IP.

Subsequently, as shown in FIG. 7B , the wiring boards IP and sealing resin MDR 1 are divided along the scribe regions SL. Thus, the semiconductor devices SD are prepared.

Next, the main action and effects of this embodiment will be described. According to this embodiment, in plan view, some of the connection terminals CUP 2 are positioned between the first circuit formation area LGC 1 and the through-silicon via area TSVA 1 . This arrangement allows at least a portion of heat generated in the first circuit formation area LGC 1 to transfer to the wiring board IP through the connection terminals CUP. Resultantly, heat transferring from the first semiconductor chip SC 1 to the second semiconductor chip SC 2 through the first through-silicon via TSV 1 can be reduced. Especially, in this embodiment, the connection terminals CUP 2 are arranged so as to surround the through-silicon via areas TSVA 1 entirely. Therefore, the aforementioned effect is further enhanced.

[First Modification]

FIG. 9 is a cross-sectional view showing the configuration of a semiconductor device SD according to the first modification. The semiconductor device SD according to this modification has the same configuration as the semiconductor device SD of the embodiment except for the following.

The first difference is that the semiconductor device SD includes plural second semiconductor chips SC 2 . The second semiconductor chips SC 2 are stacked on top of each other. At least one of the second or higher positioned second semiconductor chips SC 2 , for example, the uppermost second semiconductor chip SC 21 is made thicker than the other second semiconductor chips SC 2 . However, the uppermost second semiconductor chip SC 21 also can have the same thickness as the other second semiconductor chips SC 2 . The second semiconductor chips SC 2 that are stacked on top of each other are stacked over the first semiconductor chip SC 1 .

Each of the second semiconductor chips SC 2 has second through-silicon vias TSV 2 . The second through-silicon vias TSV 2 couple one second semiconductor chip SC 2 to another second semiconductor chip SC 2 positioned thereabove. Thus, the first semiconductor chip SC 1 is electrically coupled to the second or higher positioned second semiconductor chips SC 2 through the second through-silicon vias TSV 2 . The second semiconductor chips SC 2 are, for example, all memory chips. However, at least one of the second semiconductor chips SC 2 may include a logic circuit. In the example shown in FIG. 9 , the four sides of the respective second semiconductor chips SC 2 overlap with each other in plan view. In addition, the second through-silicon vias TSV 2 of the respective second semiconductor chips SC 2 overlap with each other in plan view.

As viewed in plan view, at least some of the second through-silicon vias TSV 2 overlap with any of the first through-silicon vias TSV 1 . Laying out the vias in the aforementioned manner can simplify the pattern of conductors between the second through-silicon vias TSV 2 and the first through-silicon vias TSV 1 coupled thereto.

In the example shown in FIG. 9 , the second through-silicon vias TSV 2 are arranged on the same grid points as the first through-silicon vias TSV 1 . The second semiconductor chips SC 2 also have areas like the through-silicon via areas TSVA 1 . For instance, in the case where the second semiconductor chips SC 2 are memory chips, the second through-silicon vias TSV 2 are arranged in accordance with specifications set out in JEDEC JESD 229. The grids made by the array of the first through-silicon vias TSV 1 overlap with the grids made by the array of the second through-silicon vias TSV 2 , respectively, in plan view.

FIG. 10 illustrates the cross-sectional structure of the second semiconductor chips SC 2 . In the example shown in FIG. 10 , a second through-silicon via TSV 2 is formed in a substrate SUB 2 of a second semiconductor chip SC 2 . The second through-silicon via TSV 2 is made of a conductive material, such as copper, and passes through the substrate SUB 2 . Also, an insulating film is embedded in the substrate SUB 2 so as to surround the second through-silicon via TSV 2 . This insulating film may be thicker than the insulating film between the substrate SUB 1 of the first semiconductor chip SC 1 and the first through-silicon via TSV 1 .

Over an element formation surface SFC 21 of the substrate SUB 2 , a multilevel interconnection layer MIL 2 is formed. The second through-silicon via TSV 2 is coupled to a connection terminal EL 21 provided over the multilevel interconnection layer MIL 2 through vias or the like in the multilevel interconnection layer. The connection terminal EL 21 is, for example, a conductor post made of copper or other materials. In addition, an electrode EL 22 is formed over the back surface SFC 22 of the substrate SUB 2 . The electrode EL 22 is coupled to the second through-silicon via TSV 2 .

The method for manufacturing the semiconductor device SD according to the first modification is the same as that according to the first embodiment, except that the second semiconductor chips SC 2 are stacked on top of each other in advance.

The first modification can also provide the same effect as the embodiment. In addition, making the insulating film, which surrounds the second through-silicon via TSV 2 in the substrate SUB 2 of the second semiconductor chip SC 2 , thicker than the insulating film between the substrate SUB 1 of the first semiconductor chip SC 1 and the first through-silicon via TSV 1 can reduce the amount of heat flowing into the substrate SUB 2 through the first through-silicon vias TSV 1 and the second through-silicon vias TSV 2 .

[Second Modification]

FIG. 11 is a plan view showing the configuration of a semiconductor device SD according to the second modification. The semiconductor device SD according to this modification has the same configuration as the embodiment or the first modification except for the following.

As viewed in a cross section taken along a short side of the through-silicon via area TSVA 1 , the center of the through-silicon via area TSVA 1 is off center of the first semiconductor chip SC 1 in an opposite direction to the first circuit formation area LGC 1 . Especially in this cross section, it is preferable that the center of the first semiconductor chip SC 1 is not aligned with the center of the through-silicon via area TSVA 1 .

Also in this cross section, the first circuit formation area LGC 1 is arranged on one side with respect to the center of the wiring board IP and the through-silicon via area TSVA 1 is arranged on the other side.

With respect to the through-silicon via area TSVA 1 , the second circuit formation area LGC 2 is placed on the same side as the first circuit formation area LGC 1 . In plan view, at least a part of the first circuit formation area LGC 1 does not overlap with the second semiconductor chip SC 2 . Also, at least a part of the second circuit formation area LGC 2 does not overlap with the second semiconductor chip SC 2 in plan view.

In the aforementioned cross section, the center of the second semiconductor chip SC 2 is off center of the wiring board IP. This arrangement can make the distance from at least one side surface of the second semiconductor chip SC 2 to a side surface of the semiconductor device SD shorter, thereby making it easy to discharge heat of the second semiconductor chip SC 2 from the side surface of the semiconductor device SD.

Also, in this cross section, the distance from the center of the second semiconductor chip SC 2 to the center of the wiring board IP is shorter than the distance from the first semiconductor chip SC 1 to the center of the wiring board IP.

If the first semiconductor chip SC 1 is divided by an area, which is made by extending the through-silicon via area TSVA 1 in parallel with the long sides of the through-silicon via area TSVA 1 , an area including the first circuit formation area LGC 1 has more connection terminals CUP in number than the other area. This arrangement allows the heat from the first circuit formation area LGC 1 to easily escape through the connection terminals CUP to the wiring board IP.

The second modification can also provide the same effect as the embodiment or the first modification. As viewed in a cross section taken along a short side of the through-silicon via area TSVA 1 , the center of the through-silicon via area TSVA 1 is off center of the first semiconductor chip SC 1 in an opposite direction to the first circuit formation area LGC 1 . Hence, the distance between the first circuit formation area LGC 1 and through-silicon via area TSVA 1 can be still increased. Therefore, the heat that is generated in the first circuit formation area LGC 1 and reaches the second semiconductor chip SC 2 through the first through-silicon via TSV 1 can be further reduced. In the aforementioned cross section, the center of the second semiconductor chip SC 2 is preferably aligned with the through-silicon via area TSVA 1 . This arrangement can smooth the temperature distribution in the second semiconductor chip SC 2 .

In addition, the distance from the center of the second semiconductor chip SC 2 to the center of the wiring board IP is shorter than the distance from the first semiconductor chip SC 1 to the center of the wiring board IP. Accordingly, at least one side surface of the second semiconductor chip SC 2 can be placed near a side surface of the semiconductor device SD. Therefore, the heat of the second semiconductor chip SC 2 can be easily discharged from the side surface of the semiconductor device SD.

In addition, with respect to the through-silicon via area TSVA 1 , the second circuit formation area LGC 2 is placed on the same side as the first circuit formation area LGC 1 . Hence, the area of the the first semiconductor chip SC 1 where the first circuit formation area LGC 1 and second circuit formation area LGC 2 are located increases in temperature, thereby making the temperature gradient greater between the first semiconductor chip SC 1 and resin around the first semiconductor chip SC 1 . As a result, the amount of heat escaping out of the first semiconductor chip SC 1 can be increased.

[Third Modification]

FIG. 12 is a plan view of an electronic device ED according to the third modification. The electronic device ED shown in FIG. 12 is a portable electronic device, such as a portable communication terminal, a portable video game console, and a portable personal computer, and includes the semiconductor device SD. The electronic device ED also includes a display DIS. The display DIS is controlled by using the semiconductor device SD.

FIG. 13 is a block diagram showing a functional configuration of the electronic device ED. In the example shown in FIG. 13 , the second semiconductor chip SC 2 is a memory chip. The first semiconductor chip SC 1 uses the second semiconductor chip SC 2 to control the electronic device ED. The first circuit formation area LGC 1 of the first semiconductor chip SC 1 is a core central processing unit (CPU), and the second circuit formation area LGC 2 of the first semiconductor chip SC 1 is a graphic processing unit (GPU). The first semiconductor chip SC 1 further includes plural circuitry areas LGC 3 , LGC 4 (e.g., a modem circuit, speech processing circuit, etc.). The electronic device ED also includes a nonvolatile memory (NVM).

The first semiconductor chip SC 1 communicates with a communication unit (either wired or wireless), a communication interface for wireless tag, such as RFIC, an analog-to-digital converter, a digital-to-analog converter, a power controller, an SIM card, an image pickup unit, a memory card, a user input unit (e.g., keypad), a USB communication unit, and an NVM.

It should be further understood by those skilled in the art that although the foregoing description has been made on an embodiment of the invention, the invention is not limited thereto and various changes and modifications may be made without departing from the spirit of the invention and the scope of the appended claims.