A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

Description

113 parts

›CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. application Ser. No. 13/379,329, filed Feb. 28, 2012, which is a National Stage application of International Application PCT/JP2010/060308 having the International Filing Date of Jun. 17, 2010, and having the benefit of the earlier filing dates of Japanese Application No. 2009-145637, filed Jun. 18, 2009, Japanese Application No. 2009-149856, filed Jun. 24, 2009, Japanese Application No. 2009-153919, filed Jun. 29, 2009, Japanese Application No. 2009-206139, filed Sep. 7, 2009, Japanese Application No. 2009-241547, filed Oct. 20, 2009, Japanese Application No. 2009-241548, filed Oct. 20, 2009, Japanese Application No. 2009-241549, filed Oct. 20, 2009, Japanese Application No. 2009-241591, filed Oct. 20, 2009, Japanese Application No. 2009-256873, filed Nov. 10, 2009, Japanese Application No. 2009-256874, filed Nov. 10, 2009, Japanese Application No. 2009-256875, filed Nov. 10, 2009, Japanese Application No. 2009-256877, filed Nov. 10, 2009, Japanese Application No. 2009-256878, filed Nov. 10, 2009, Japanese Application No. 2009-256879, filed Nov. 10, 2009, Japanese Application No. 2009-256880, filed Nov. 10, 2009, Japanese Application No. 2009-266678, filed Nov. 24, 2009, Japanese Application No. 2010-000556, filed Jan. 5, 2010, and Japanese Application No. 2010-040398, filed Feb. 25, 2010. All of the identified applications are fully incorporated herein by reference.

›FIELD OF THE ART

The present invention relates to a semiconductor device.

›BACKGROUND ART

Semiconductor devices are normally distributed in a state where a semiconductor chip is sealed (packaged) together with bonding wires by a resin. Inside the package, electrode pads of the semiconductor chip are electrically connected by the bonding wires to electrode leads that are partially exposed from the resin package. Electrical connection of the semiconductor chip and a mounting board is thus achieved by connecting the electrode leads as external terminals to wirings on a mounting board.

Although conventionally, gold wires are mainly used as the bonding wires connecting the electrode pads and the electrode leads, recently, the use of copper wires that are cheaper than gold wires is being examined for reducing the use of high-priced gold.

›PRIOR ART DOCUMENT(S)

Patent Document(s)

Patent Document 1: Japanese Published Unexamined Patent Application No. Hei 10-261664

›OUTLINE OF THE INVENTION

Object(s) of the Invention

However, when a semiconductor device is placed under a high humidity environment, water may penetrate into an interior of the package. For example, water vapor inside a test tank readily penetrates into the interior of the package during execution of a humidity resistance evaluation test, such as a PCT (pressure cooker test), HAST (highly accelerated temperature and humidity stress test).

In a case where copper wires are used as the wires connected to electrode pads made of aluminum that have become the mainstream in recent years, corrosion of aluminum proceeds readily near a bond interface of an electrode pad and a bonding wire when the penetrating water enters the bond interface. An electrically open state may thus occur between the pad and the wire.

An object of the present invention is to provide a semiconductor device that can be improved in reliability of connection of a bonding wire made of copper with an electrode pad made of a metal material that contains aluminum.

Means for Achieving the Object(s)

A semiconductor device according to the present invention for achieving the above object includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

By this arrangement, the entire electrode pad and the entire pad bond portion are integrally covered by the water-impermeable film. A peripheral edge of a bond interface (pad bond interface) of the electrode pad and the pad bond portion is thereby covered by the water-impermeable film without being exposed.

Thus, even if water penetrates into an interior of the resin package, the water can be blocked by the water-impermeable film and contact of the pad bond interface with water can be suppressed. Consequently, progress of corrosion of the electrode pad can be suppressed and occurrence of an electrically open state between the pad and the wire can be suppressed. Connection reliability of the semiconductor device can thus be improved.

›BRIEF DESCRIPTION OF THE DRAWINGS · 1 of 7

FIG. 1 is a schematic bottom view of a semiconductor device according to a first preferred embodiment of the present invention.

FIG. 2 is a schematic sectional view of the semiconductor device according to the first preferred embodiment of the present invention.

FIG. 3A is an enlarged view of principal portions of a portion surrounded by a broken-line circle A in FIG. 2 .

FIG. 3B is an enlarged view of principal portions of a portion surrounded by a broken-line circle B in FIG. 2 .

FIG. 4A is a schematic sectional view for describing a method for manufacturing the semiconductor device of FIG. 2 .

FIG. 4B is a diagram of a step subsequent to that of FIG. 4A .

FIG. 4C is a diagram of a step subsequent to that of FIG. 4B .

FIG. 4D is a diagram of a step subsequent to that of FIG. 4C .

FIG. 4E is a diagram of a step subsequent to that of FIG. 4D .

FIG. 5 is a schematic sectional view of a semiconductor device according to a modification example of the semiconductor device of FIG. 2 .

FIG. 6A is an enlarged view of principal portions of a portion surrounded by a broken-line circle A in FIG. 5 .

FIG. 6B is an enlarged view of principal portions of a portion surrounded by a broken-line circle B in FIG. 5 .

FIG. 7A is a schematic sectional view for describing a method for manufacturing the semiconductor device of FIG. 5 .

FIG. 7B is a diagram of a step subsequent to that of FIG. 7A .

FIG. 7C is a diagram of a step subsequent to that of FIG. 7B .

FIG. 7D is a diagram of a step subsequent to that of FIG. 7C .

FIG. 7E is a diagram of a step subsequent to that of FIG. 7D .

FIG. 8 is a schematic sectional view of a semiconductor device according to a modification example of the semiconductor device of FIG. 2 .

FIG. 9 is a schematic sectional view of a semiconductor device according to a modification example of the semiconductor device of FIG. 2 .

FIG. 10 is a schematic sectional view of a semiconductor device according to a second preferred embodiment of the present invention.

FIG. 11 is an exploded plan view of the semiconductor device of FIG. 10 with a resin package removed.

FIG. 12A is an enlarged view of a vicinity of an electrode pad of FIG. 11 .

FIG. 12B is a sectional view taken along the sectioning line B-B of FIG. 12A .

FIG. 12C is a sectional view taken along the sectioning line C-C of FIG. 12A .

FIG. 13A is a diagram of a first modification example of the semiconductor device of FIG. 10 and is a diagram corresponding to FIG. 12A .

FIG. 13B is a diagram of the first modification example of the semiconductor device of FIG. 10 and is a diagram corresponding to FIG. 12B .

FIG. 13C is a diagram of the first modification example of the semiconductor device of FIG. 10 and is a diagram corresponding to FIG. 12C .

FIG. 14 is a diagram of a second modification example of the semiconductor device of FIG. 10 .

FIG. 15 is a diagram of a third modification example of the semiconductor device of FIG. 10 .

FIG. 16 is an enlarged view of principal portions of a first bond portion in a conventional semiconductor device.

FIG. 17 is a diagram of a fourth modification example of the semiconductor device of FIG. 10 .

FIG. 18 is a schematic bottom view of a semiconductor device according to a third preferred embodiment of the present invention.

FIG. 19 is a schematic sectional view of the semiconductor device according to the third preferred embodiment of the present invention.

FIG. 20 is an enlarged view of a portion surrounded by a broken-line circle in FIG. 19 .

FIG. 21 is a conceptual diagram for determining a volume of a pad bond portion.

FIG. 22A is a schematic sectional view for describing a method for manufacturing the semiconductor device of FIG. 2 .

FIG. 22B is a diagram of a step subsequent to that of FIG. 22A .

FIG. 22C is a diagram of a step subsequent to that of FIG. 22B .

FIG. 22D is a diagram of a step subsequent to that of FIG. 22C .

FIG. 22E is a diagram of a step subsequent to that of FIG. 22D .

FIG. 23 is a diagram of a modification example of the semiconductor device of FIG. 19 .

FIG. 24 is a diagram showing SEM images and FAB forming conditions of Examples 1 to 3 and Comparative Examples 1 to 3 of the third preferred embodiment.

FIG. 25 is a diagram showing SEM images and FAB forming conditions of Examples 4 to 7 and Comparative Examples 4 to 7 of the third preferred embodiment.

FIG. 26 is a diagram showing SEM images and FAB forming conditions of Examples 8 and 9 and Comparative Examples 8 and 9 of the third preferred embodiment.

FIG. 27 is a schematic bottom view of a semiconductor device according to a fourth preferred embodiment of the present invention.

FIG. 28 is a schematic sectional view of the semiconductor device according to the fourth preferred embodiment of the present invention.

FIG. 29 is an enlarged view of a portion surrounded by a broken-line circle in FIG. 28 .

FIG. 30A is a schematic sectional view for describing a method for manufacturing the semiconductor device of FIG. 27 .

FIG. 30B is a diagram of a step subsequent to that of FIG. 30A .

FIG. 30C is a diagram of a step subsequent to that of FIG. 30B .

FIG. 30D is a diagram of a step subsequent to that of FIG. 30C .

FIG. 30E is a diagram of a step subsequent to that of FIG. 30D .

FIG. 31 is a diagram of a state of occurrence of excessive splash at an electrode pad.

FIG. 32 is a diagram of a modification example of the semiconductor device of FIG. 28 .

FIG. 33 is a timing chart of load and ultrasonic waves in Example 1 of the fourth preferred embodiment.

FIG. 34 is a timing chart of load and ultrasonic waves in Comparative Example 1 of the fourth preferred embodiment.

FIG. 35 is an SEM image of a pad bond portion of Example 1 of the fourth preferred embodiment.

FIG. 36 is an SEM image of a pad bond portion of Comparative Example 1 of the fourth preferred embodiment.

FIG. 37 is a schematic sectional view of a semiconductor device according to a fifth preferred embodiment of the present invention.

FIG. 38 is a sectional view of principal portions of a semiconductor chip and is an enlarged view of a portion surrounded by a broken-line circle in FIG. 38 .

›BRIEF DESCRIPTION OF THE DRAWINGS · 2 of 7

FIG. 39 is a plan view of an electrode pad shown in FIG. 38 .

FIG. 40 is a diagram of a first modification example of the semiconductor device of FIG. 37 and is a diagram corresponding to FIG. 38 .

FIG. 41 is a diagram of a second modification example of the semiconductor device of FIG. 37 and is a diagram corresponding to FIG. 38 .

FIG. 42 is a diagram of a third modification example of the semiconductor device of FIG. 37 .

FIG. 43 shows schematic sectional views of semiconductor devices of examples and comparative examples of the fifth preferred embodiment, each showing a vicinity of an electrode pad in an enlarged manner.

FIG. 44 is a schematic sectional view of a semiconductor device according to a sixth preferred embodiment of the present invention.

FIG. 45 is an exploded plan view of the semiconductor device of FIG. 44 with a resin package removed.

FIG. 46 is a sectional view of principal portions of a semiconductor chip and is an enlarged view of a portion surrounded by a broken-line circle in FIG. 44 .

FIG. 47 is an enlarged plan view of an electrode pad shown in FIG. 46 .

FIG. 48A is a schematic sectional view for describing a method for manufacturing the semiconductor device of FIG. 44 .

FIG. 48B is a diagram of a step subsequent to that of FIG. 48A .

FIG. 48C is a diagram of a step subsequent to that of FIG. 48B .

FIG. 48D is a diagram of a step subsequent to that of FIG. 48C .

FIG. 48E is a diagram of a step subsequent to that of FIG. 48D .

FIG. 49 is a diagram of a modification example of the semiconductor device of FIG. 44 .

FIG. 50A is a distribution diagram of sizes of base portions of Example 1 and Comparative Example 1 of the sixth preferred embodiment and is a distribution diagram of base diameters in an X-direction and a Y-direction.

FIG. 50B is a distribution diagram of sizes of the base portions of Example 1 and Comparative Example 1 of the sixth preferred embodiment and is a distribution diagram of thickness in a Z-direction.

FIG. 51A is a distribution diagram of sizes of base portions of Example 2 and Comparative Example 2 of the sixth preferred embodiment and is a distribution diagram of base diameters in an X-direction and a Y-direction.

FIG. 51B is a distribution diagram of sizes of the base portions of Example 2 and Comparative Example 2 of the sixth preferred embodiment and is a distribution diagram of thickness in a Z-direction.

FIG. 52A is a distribution diagram of sizes of base portions of Example 3 and Comparative Example 3 of the sixth preferred embodiment and is a distribution diagram of base diameters in an X-direction and a Y-direction.

FIG. 52B is a distribution diagram of sizes of the base portions of Example 3 and Comparative Example 3 of the sixth preferred embodiment and is a distribution diagram of thickness in a Z-direction.

FIG. 53A is a distribution diagram of sizes of base portions of Example 4 and Comparative Example 4 of the sixth preferred embodiment and is a distribution diagram of base diameters in an X-direction and a Y-direction.

FIG. 53B is a distribution diagram of sizes of the base portions of Example 4 and Comparative Example 4 of the sixth preferred embodiment and is a distribution diagram of thickness in a Z-direction.

FIG. 54A is a distribution diagram of sizes of base portions of Example 5 and Comparative Example 5 of the sixth preferred embodiment and is a distribution diagram of base diameters in an X-direction and a Y-direction.

FIG. 54B is a distribution diagram of sizes of the base portions of Example 5 and Comparative Example 5 of the sixth preferred embodiment and is a distribution diagram of thickness in a Z-direction.

FIG. 55 is a correlation diagram of a relationship between an applied energy E 1 of a first cycle and a ball diameter of a pad bond portion.

FIG. 56 is a schematic sectional view of a semiconductor device according to a seventh preferred embodiment of the present invention.

FIG. 57 is a schematic bottom view of the semiconductor device shown in FIG. 56 .

FIG. 58 is an enlarged view of a portion surrounded by broken lines shown in FIG. 56 .

FIG. 59A is a schematic sectional view of a state in a middle of manufacture (middle of wire bonding) of the semiconductor device shown in FIG. 56 .

FIG. 59B is a schematic sectional view of a step subsequent to that of FIG. 59A .

FIG. 59C is a schematic sectional view of a step subsequent to that of FIG. 59B .

FIG. 59D is a schematic sectional view of a step subsequent to that of FIG. 59C .

FIG. 60 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad.

FIG. 61 is a schematic sectional view of a standard type capillary.

FIG. 62 is a schematic sectional view of a bottleneck type capillary.

FIG. 63 is an SEM image of a vicinity of a first ball portion obtained in test 1 of the seventh preferred embodiment.

FIG. 64 is an SEM image of a vicinity of a first ball portion obtained in test 2 of the seventh preferred embodiment.

FIG. 65 is an SEM image of a vicinity of a first ball portion obtained in test 3 of the seventh preferred embodiment.

FIG. 66 is an SEM image of a vicinity of a first ball portion obtained in test 4 of the seventh preferred embodiment.

FIG. 67 is an SEM image of a vicinity of a first ball portion obtained in test 5 of the seventh preferred embodiment.

FIG. 68 is a diagram of a modification example of the semiconductor device of FIG. 56 .

FIG. 69 is a schematic sectional view of a semiconductor device according to an eighth preferred embodiment of the present invention.

FIG. 70 is a schematic sectional view of a pad and a portion of a copper wire bonded to the pad.

FIG. 71 is a schematic sectional view of a pad and a portion of a copper wire bonded to the pad according to another structure.

FIG. 72 is a schematic sectional view of a pad and a portion of a copper wire bonded to the pad according to yet another structure.

FIG. 73 is a diagram of a modification example of the semiconductor device of FIG. 69 .

›BRIEF DESCRIPTION OF THE DRAWINGS · 3 of 7

FIG. 74 is a schematic sectional view of a semiconductor device according to a ninth preferred embodiment of the present invention.

FIG. 75 is a schematic plan view of the semiconductor device shown in FIG. 74 and shows a state where illustration of a resin package is omitted.

FIG. 76 is a schematic sectional view of a first modification example of the semiconductor device shown in FIG. 74 .

FIG. 77 is a schematic sectional view of a second modification example of the semiconductor device shown in FIG. 74 .

FIG. 78 is a schematic sectional view of a third modification example of the semiconductor device shown in FIG. 74 .

FIG. 79 is a schematic sectional view of a fourth modification example of the semiconductor device shown in FIG. 74 .

FIG. 80 is a schematic sectional view of a semiconductor device according to another mode of the first modification example.

FIG. 81 is a schematic sectional view of a semiconductor device according to another mode of the second modification example.

FIG. 82 is a schematic sectional view of a semiconductor device according to another mode of the third modification example.

FIG. 83 is a schematic sectional view of a semiconductor device according to a tenth preferred embodiment of the present invention.

FIG. 84 is a schematic plan view of the semiconductor device shown in FIG. 83 as viewed from a rear surface side and shows a state where illustration of a resin package is omitted.

FIG. 85 is a schematic sectional view of a first modification example of the semiconductor device shown in FIG. 83 .

FIG. 86 is a schematic plan view of the semiconductor device shown in FIG. 85 as viewed from a rear surface side and shows a state where illustration of a resin package is omitted.

FIG. 87 is a schematic sectional view of a second modification example of the semiconductor device shown in FIG. 83 .

FIG. 88 is a schematic plan view of the semiconductor device shown in FIG. 87 as viewed from a rear surface side and shows a state where illustration of a resin package is omitted.

FIG. 89 is a schematic sectional view of a third modification example of the semiconductor device shown in FIG. 83 .

FIG. 90 is a schematic plan view of the semiconductor device shown in FIG. 89 as viewed from a rear surface side and shows a state where illustration of a resin package is omitted.

FIG. 91 is a schematic sectional view of a fourth modification example of the semiconductor device shown in FIG. 83 .

FIG. 92 is a schematic sectional view of a semiconductor device according to another mode of the first modification example.

FIG. 93 is a schematic sectional view of a semiconductor device according to another mode of the second modification example.

FIG. 94 is a schematic sectional view of a semiconductor device according to another mode of the third modification example.

FIG. 95 is a schematic bottom view of a semiconductor device according to an eleventh preferred embodiment of the present invention.

FIG. 96 is a schematic sectional view of the semiconductor device according to the eleventh preferred embodiment of the present invention.

FIG. 97 is an enlarged view of principal portions of a portion surrounded by a broken-line circle in FIG. 96 .

FIG. 98A is a schematic sectional view for describing a method for manufacturing the semiconductor device shown in FIG. 2 .

FIG. 98B is a schematic sectional view of a step subsequent to that of FIG. 98A .

FIG. 98C is a schematic sectional view of a step subsequent to that of FIG. 98B .

FIG. 98D is a schematic sectional view of a step subsequent to that of FIG. 98C .

FIG. 99 is a diagram of a first modification example of the semiconductor device of FIG. 96 .

FIG. 100 is a diagram of a second modification example of the semiconductor device of FIG. 96 .

FIG. 101A is an enlarged view of principal portions of a portion surrounded by a broken-line circle A in FIG. 100 .

FIG. 101B is an enlarged view of principal portions of a portion surrounded by a broken-line circle B in FIG. 100 .

FIG. 102 is a diagram of the second modification example of the semiconductor device of FIG. 96 .

FIG. 103 is a diagram of a third modification example of the semiconductor device of FIG. 96 .

FIG. 104 is a schematic sectional view of a semiconductor device according to another mode of the first modification example.

FIG. 105 is a schematic sectional view of a semiconductor device according to another mode of the second modification example.

FIG. 106 is a schematic sectional view of a semiconductor device according to a twelfth preferred embodiment of the present invention.

FIG. 107 is a schematic bottom view of the semiconductor device shown in FIG. 106 .

FIG. 108 is an enlarged view of a portion surrounded by broken lines shown in FIG. 106 .

FIG. 109A is a schematic sectional view of a state in a middle of manufacture (middle of wire bonding) of the semiconductor device shown in FIG. 106 .

FIG. 109B is a schematic sectional view of a step subsequent to that of FIG. 109A .

FIG. 109C is a schematic sectional view of a step subsequent to that of FIG. 109B .

FIG. 109D is a schematic sectional view of a step subsequent to that of FIG. 109C .

FIG. 110 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad.

FIG. 111 is a graph of a relationship between an area of bonding of a first ball portion to a pad and an initial load.

FIG. 112 is a graph of changes with time of diameters (ball diameters) measured in test 1.

FIG. 113 is a graph of changes with time of thicknesses (ball thicknesses) measured in test 1.

FIG. 114 is a graph of changes with time of diameters (ball diameters) measured in test 2.

FIG. 115 is a graph of changes with time of thicknesses (ball thicknesses) measured in test 2.

FIG. 116 is a graph of changes with time of diameters (ball diameters) measured in test 3.

FIG. 117 is a graph of changes with time of thicknesses (ball thicknesses) measured in test 3.

FIG. 118 is an SEM image of a vicinity of a first ball portion formed when an initial load is applied to the FAB.

›BRIEF DESCRIPTION OF THE DRAWINGS · 4 of 7

FIG. 119 is an SEM image of a vicinity of a first ball portion formed when a movement speed of the FAB to the pad is increased.

FIG. 120 is a modification example of the semiconductor device of FIG. 106 .

FIG. 121 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Example 1 of the twelfth preferred embodiment.

FIG. 122 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Comparative Example 1 of the twelfth preferred embodiment.

FIG. 123 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Comparative Example 2 of the twelfth preferred embodiment.

FIG. 124 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Comparative Example 3 of the twelfth preferred embodiment.

FIG. 125 is an SEM image of a vicinity of a first ball portion of Example 1 of the twelfth preferred embodiment.

FIG. 126 is an SEM image of a vicinity of a first ball portion of Comparative Example 1 of the twelfth preferred embodiment.

FIG. 127 is an SEM image of a vicinity of a first ball portion of Comparative Example 2 of the twelfth preferred embodiment.

FIG. 128 is an SEM image of a vicinity of a first ball portion of Comparative Example 3 of the twelfth preferred embodiment.

FIG. 129 is an SEM image of a bond surface of the first ball portion of Example 1 of the twelfth preferred embodiment.

FIG. 130 is an SEM image of a bond surface of the first ball portion of Comparative Example 1 of the twelfth preferred embodiment.

FIG. 131 is an SEM image of a bond surface of the first ball portion of Comparative Example 2 of the twelfth preferred embodiment.

FIG. 132 is an SEM image of a bond surface of the first ball portion of Comparative Example 3 of the twelfth preferred embodiment.

FIG. 133 is an image of a pad of Example 1 of the twelfth preferred embodiment.

FIG. 134 is an image of a pad of Comparative Example 1 of the twelfth preferred embodiment.

FIG. 135 is an image of a pad of Comparative Example 2 of the twelfth preferred embodiment.

FIG. 136 is an image of a pad of Comparative Example 3 of the twelfth preferred embodiment.

FIG. 137 is an image of a top surface of an interlayer insulating film of Example 1 of the twelfth preferred embodiment.

FIG. 138 is an image of a top surface of an interlayer insulating film of Comparative Example 1 of the twelfth preferred embodiment.

FIG. 139 is an image of a top surface of an interlayer insulating film of Comparative Example 2 of the twelfth preferred embodiment.

FIG. 140 is an image of a top surface of an interlayer insulating film of Comparative Example 3 of the twelfth preferred embodiment.

FIG. 141 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Example 2 and Comparative Examples 4 to 8 of the twelfth preferred embodiment.

FIG. 142 is a graph of crack occurrence rates in Example 2 and Comparative Examples 4 to 8 of the twelfth preferred embodiment.

FIG. 143 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Examples 3 to 7 and Comparative Examples 9 to 11 of the twelfth preferred embodiment.

FIG. 144 is a graph of crack occurrence rates in Examples 3 to 7 and Comparative Examples 9 to 11 of the twelfth preferred embodiment.

FIG. 145 is an SEM image of a vicinity of a first ball portion of Example 8 of the twelfth preferred embodiment.

FIG. 146 is an SEM image of a vicinity of a first ball portion of Comparative Example 12 of the twelfth preferred embodiment.

FIG. 147 is an SEM image of a vicinity of a first ball portion of Comparative Example 13 of the twelfth preferred embodiment.

FIG. 148 is an SEM image of a vicinity of a first ball portion of Comparative Example 14 of the twelfth preferred embodiment.

FIG. 149 is an image of a pad after breakage of Example 8 of the twelfth preferred embodiment.

FIG. 150 is an image of a pad after breakage of Comparative Example 12 of the twelfth preferred embodiment.

FIG. 151 is an image of a pad after breakage of Comparative Example 13 of the twelfth preferred embodiment.

FIG. 152 is an image of a bottom surface of a first ball portion (surface bonded to a pad) after breakage of Comparative Example 13 of the twelfth preferred embodiment.

FIG. 153 is an image of a pad after breakage of Comparative Example 13 of the twelfth preferred embodiment.

FIG. 154 is a graph of measurement results of diameters of first ball portions of Example 8 and Comparative Examples 12 to 14 of the twelfth preferred embodiment.

FIG. 155 is a graph of measurement results of thicknesses of first ball portions of Example 8 and Comparative Examples 12 to 14 of the twelfth preferred embodiment.

FIG. 156 is a graph of measurement results of forces (shear strengths) required for breakage of portions of bonding of the first ball portion and pad of Example 8 and Comparative Examples 12 to 14 of the twelfth preferred embodiment.

FIG. 157 is a schematic sectional view of a semiconductor device according to a thirteenth preferred embodiment of the present invention.

FIG. 158 is a schematic bottom view of the semiconductor device shown in FIG. 157 .

FIG. 159 is an enlarged view of a portion surrounded by broken lines shown in FIG. 157 .

FIG. 160A is a schematic sectional view of a state in a middle of manufacture (middle of wire bonding) of the semiconductor device shown in FIG. 157 .

FIG. 160B is a schematic sectional view of a step subsequent to that of FIG. 160A .

FIG. 160C is a schematic sectional view of a step subsequent to that of FIG. 160B .

FIG. 160D is a schematic sectional view of a step subsequent to that of FIG. 160C .

›BRIEF DESCRIPTION OF THE DRAWINGS · 5 of 7

FIG. 161 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad.

FIG. 162 is a diagram of a modification example of the semiconductor device of FIG. 157 .

FIG. 163 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Example 1 and Comparative Examples 1 to 5 of the thirteenth preferred embodiment.

FIG. 164 is a graph of crack occurrence rates in Example 1 and Comparative Examples 1 to 5 of the thirteenth preferred embodiment.

FIG. 165 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Examples 2 to 6 and Comparative Examples 6 to 8 of the thirteenth preferred embodiment.

FIG. 166 is a graph of crack occurrence rates in Examples 2 to 6 and Comparative Examples 6 to 8 of the thirteenth preferred embodiment.

FIG. 167 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Examples 7 and 8 and Comparative Examples 9 to 12 of the thirteenth preferred embodiment.

FIG. 168 is a graph of crack occurrence rates in Examples 7 and 8 and Comparative Examples 9 to 12 of the thirteenth preferred embodiment.

FIG. 169 is a schematic sectional view of a semiconductor device according to a fourteenth preferred embodiment of the present invention.

FIG. 170 is a schematic bottom view of the semiconductor device shown in FIG. 169 .

FIG. 171 is an enlarged view of a portion surrounded by broken lines shown in FIG. 169 .

FIG. 172A is a schematic sectional view of a state in a middle of manufacture (middle of wire bonding) of the semiconductor device shown in FIG. 169 .

FIG. 172B is a schematic sectional view of a step subsequent to that of FIG. 172A .

FIG. 172C is a schematic sectional view of a step subsequent to that of FIG. 172B .

FIG. 172D is a schematic sectional view of a step subsequent to that of FIG. 172C .

FIG. 173 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad.

FIG. 174 is a graph of changes with time of diameters (ball diameters) measured in test 1.

FIG. 175 is a graph of changes with time of thicknesses (ball thicknesses) measured in test 1.

FIG. 176 is a graph of changes with time of diameters (ball diameters) measured in test 2.

FIG. 177 is a graph of changes with time of thicknesses (ball thicknesses) measured in test 2.

FIG. 178 is a graph of changes with time of diameters (ball diameters) measured in test 3.

FIG. 179 is a graph of changes with time of thicknesses (ball thicknesses) measured in test 3.

FIG. 180 is a diagram of a modification example of the semiconductor device of FIG. 169 .

FIG. 181 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Examples 1 to 3 and Comparative Examples 1 to 4 of the fourteenth preferred embodiment.

FIG. 182 is a graph of crack occurrence rates in Examples 1 to 3 and Comparative Examples 1 to 4 of the fourteenth preferred embodiment.

FIG. 183 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Examples 4 and 5 and Comparative Examples 5 to 9 of the fourteenth preferred embodiment.

FIG. 184 is a graph of crack occurrence rates in Examples 4 and 5 and Comparative Examples 5 to 9 of the fourteenth preferred embodiment.

FIG. 185 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Examples 6 to 8 and Comparative Examples 10 to 13 of the fourteenth preferred embodiment.

FIG. 186 is a graph of crack occurrence rates in Examples 6 to 8 and Comparative Examples 10 to 13 of the fourteenth preferred embodiment.

FIG. 187 is a graph of a relationship between an area of bonding of a first ball portion to a pad and a driving current of an ultrasonic transducer.

FIG. 188 is a schematic sectional view of a semiconductor device according to a fifteenth preferred embodiment of the present invention.

FIG. 189 is a schematic bottom view of the semiconductor device shown in FIG. 188 .

FIG. 190 is an enlarged view of a portion surrounded by broken lines shown in FIG. 188 .

FIG. 191A is a schematic sectional view of a state in a middle of manufacture (middle of wire bonding) of the semiconductor device shown in FIG. 188 .

FIG. 191B is a schematic sectional view of a step subsequent to that of FIG. 191A .

FIG. 191C is a schematic sectional view of a step subsequent to that of FIG. 191B .

FIG. 191D is a schematic sectional view of a step subsequent to that of FIG. 191C .

FIG. 192 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad.

FIG. 193 is a graph of changes with time of diameters (ball diameters) measured in test 1.

FIG. 194 is a graph of changes with time of thicknesses (ball thicknesses) measured in test 1.

FIG. 195 is a graph of changes with time of diameters (ball diameters) measured in test 2.

FIG. 196 is a graph of changes with time of thicknesses (ball thicknesses) measured in test 2.

FIG. 197 is a graph of changes with time of diameters (ball diameters) measured in test 3.

FIG. 198 is a graph of changes with time of thicknesses (ball thicknesses) measured in test 3.

FIG. 199 is a modification example of the semiconductor device of FIG. 188 .

FIG. 200 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Examples 1 and 2 and Comparative Examples 1 to 3 of the fifteenth preferred embodiment.

FIG. 201 is a graph of crack occurrence rates in Examples 1 and 2 and Comparative Examples 1 to 3 of the fifteenth preferred embodiment.

›BRIEF DESCRIPTION OF THE DRAWINGS · 6 of 7

FIG. 202 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Example 3 of the fifteenth preferred embodiment.

FIG. 203 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad in Example 4 of the fifteenth preferred embodiment.

FIG. 204 is an illustrative plan view of a semiconductor device.

FIG. 205 is a sectional view taken along line A-A of the semiconductor device shown in FIG. 204 .

FIG. 206 is an enlarged view of principal portions of a portion surrounded by a broken-line circle in FIG. 205 .

FIG. 207A is a schematic sectional view of a state in a middle of manufacture of the semiconductor device shown in FIG. 205 .

FIG. 207B is a schematic sectional view of a step subsequent to that of FIG. 207A .

FIG. 207C is a schematic sectional view of a step subsequent to that of FIG. 207B .

FIG. 207D is a schematic sectional view of a step subsequent to that of FIG. 207C .

FIG. 207E is a schematic sectional view of a step subsequent to that of FIG. 207D .

FIG. 207F is a schematic sectional view of a step subsequent to that of FIG. 207E .

FIG. 208 is a diagram of a modification example of the semiconductor device of FIG. 205 .

FIG. 209 is a schematic sectional view of a semiconductor device according to a seventeenth preferred embodiment of the present invention.

FIG. 210A is an enlarged view of principal portions of a portion surrounded by a broken-line circle A in FIG. 209 .

FIG. 210B is an enlarged view of principal portions of a portion surrounded by a broken-line circle B in FIG. 209 .

FIG. 211 is a diagram of a modification example of the semiconductor device of FIG. 209 .

FIG. 212 is a graph of relationships of HAST time and defect rate of an example and a comparative example of the seventeenth preferred embodiment.

FIG. 213 is a graph of relationships of PCT time and defect rate of the example and the comparative example of the seventeenth preferred embodiment.

FIG. 214 is a schematic sectional view of a semiconductor device according to an eighteenth preferred embodiment of the present invention.

FIG. 215 is a schematic sectional view of a bond portion of a pad with a copper wire (portion surrounded by broken lines shown in FIG. 214 ).

FIG. 216 is a TEM image of a bond portion of a peripheral edge portion of a first ball portion with an aluminum pad (vicinity of a bond interface) in a sample in which a resin package is made of a material without an ion capturing component added.

FIG. 217 is a diagram of analysis results of component elements at a location D 0 shown in the TEM image of FIG. 216 .

FIG. 218 is a diagram of analysis results of component elements at a location D 1 shown in the TEM image of FIG. 216 .

FIG. 219 is a diagram of analysis results of component elements at a location D 2 shown in the TEM image of FIG. 216 .

FIG. 220 is a diagram of analysis results of component elements at a location D 3 shown in the TEM image of FIG. 216 .

FIG. 221 is a TEM image of a bond portion of a central portion of a first ball portion with an aluminum pad (vicinity of a bond interface) in a sample in which the resin package is made of the material without an ion capturing component added.

FIG. 222 is a diagram of analysis results of component elements at a location C 0 shown in the TEM image of FIG. 221 .

FIG. 223 is a diagram of analysis results of component elements at a location C 1 shown in the TEM image of FIG. 221 .

FIG. 224 is a diagram of analysis results of component elements at a location C 2 shown in the TEM image of FIG. 221 .

FIG. 225 is a diagram of analysis results of component elements at a location C 3 shown in the TEM image of FIG. 221 .

FIG. 226 is a diagram of analysis results of component elements at a location C 4 shown in the TEM image of FIG. 221 .

FIG. 227A is an illustrative sectional view (part 1) of a bond portion of a copper wire with an aluminum pad in a sample in which the resin package is made of the material without an ion capturing component added.

FIG. 227B is an illustrative sectional view (part 2) of the bond portion of the copper wire with the aluminum pad in the sample in which the resin package is made of the material without an ion capturing component added.

FIG. 227C is an illustrative sectional view (part 3) of the bond portion of the copper wire with the aluminum pad in the sample in which the resin package is made of the material without an ion capturing component added.

FIG. 228 is a diagram of a modification example of the semiconductor device of FIG. 214 .

FIG. 229 is a table of results of a highly accelerated stress test performed on a semiconductor device according to the eighteenth preferred embodiment and a semiconductor device according to a comparative example.

FIG. 230 is a table of results of a pressure cooker test performed on the semiconductor device according to the eighteenth preferred embodiment and the semiconductor device according to the comparative example.

FIG. 231 is a schematic bottom view of a semiconductor device according to a nineteenth preferred embodiment of the present invention.

FIG. 232 is a schematic sectional view of the semiconductor device according to the nineteenth preferred embodiment of the present invention.

FIG. 233 is an enlarged view of a portion surrounded by a broken-line circle in FIG. 232 .

FIG. 234 is a conceptual diagram for determining a volume of a pad bond portion.

FIG. 235 is a plan view of an electrode pad shown in FIG. 233 .

FIG. 236A is a schematic sectional view for describing a method for manufacturing the semiconductor device of FIG. 232 .

FIG. 236B is a schematic sectional view of a step subsequent to that of FIG. 236A .

FIG. 236C is a schematic sectional view of a step subsequent to that of FIG. 236B .

FIG. 236D is a schematic sectional view of a step subsequent to that of FIG. 236C .

FIG. 237 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad.

›BRIEF DESCRIPTION OF THE DRAWINGS · 7 of 7

FIG. 238 is a schematic sectional view of a standard type capillary.

FIG. 239 is a schematic sectional view of a bottleneck type capillary.

FIG. 240 is a schematic bottom view of a semiconductor device according to a twentieth preferred embodiment of the present invention.

FIG. 241 is a schematic sectional view of the semiconductor device according to the twentieth preferred embodiment of the present invention.

FIG. 242 is an enlarged view of principal portions of a portion surrounded by a broken-line circle A in FIG. 241 .

FIG. 243 is an enlarged view of principal portions of a portion surrounded by a broken-line circle B in FIG. 241 .

FIG. 244 is a conceptual diagram for determining a volume of a pad bond portion.

FIG. 245 is a plan view of an electrode pad shown in FIG. 244 .

FIG. 246A is a schematic sectional view for describing a method for manufacturing the semiconductor device of FIG. 241 .

FIG. 246B is a schematic sectional view of a step subsequent to that of FIG. 246A .

FIG. 246C is a schematic sectional view of a step subsequent to that of FIG. 246B .

FIG. 246D is a schematic sectional view of a step subsequent to that of FIG. 246C .

FIG. 246E is a schematic sectional view of a step subsequent to that of FIG. 246D .

FIG. 246F is a schematic sectional view of a step subsequent to that of FIG. 246E .

FIG. 246G is a schematic sectional view of a step subsequent to that of FIG. 246F .

FIG. 246H is a schematic sectional view of a step subsequent to that of FIG. 246G .

FIG. 247 is a graph of changes with time of a load applied to an FAB and a driving current applied to an ultrasonic transducer during bonding of the FAB to a pad.

FIG. 248 is a schematic sectional view of a standard type capillary.

FIG. 249 is a schematic sectional view of a bottleneck type capillary.

›MODE(S) FOR CARRYING OUT THE INVENTION · 1 of 12

Preferred embodiments of the present invention shall now be described in detail with reference to the attached drawings.

First Preferred Embodiment FIG. 1 to FIG. 9

FIG. 1 is a schematic bottom view of a semiconductor device according to a first preferred embodiment of the present invention. FIG. 2 is a schematic sectional view of the semiconductor device according to the first preferred embodiment of the present invention. FIG. 3A is an enlarged view of principal portions of a portion surrounded by a broken-line circle A in FIG. 2 . FIG. 3B is an enlarged view of principal portions of a portion surrounded by a broken-line circle B in FIG. 2 .

The semiconductor device 1 A is a semiconductor device to which a QFN (quad flat non-leaded) configuration is applied. The semiconductor device 1 A includes a semiconductor chip 2 A, a die pad 3 A supporting the semiconductor chip 2 A, a plurality of electrode leads 4 A disposed at a periphery of the semiconductor chip 2 A, bonding wires 5 A electrically connecting the semiconductor chip 2 A and the electrode leads 4 A, and a resin package 6 A sealing the above components.

The semiconductor chip 2 A has a quadrilateral shape in plan view and has, for example, a multilayer wiring structure arranged by laminating a plurality of wiring layers via interlayer insulating films. Also, the semiconductor chip 2 A has a thickness, for example, of 220 to 240 μm (preferably, approximately 230 μm). As shown in FIG. 3A , a top surface 21 A (surface at one side in a thickness direction) of the semiconductor chip 2 A is covered by a top surface protective film 7 A.

A plurality of pad openings 8 A for exposing an uppermost wiring layer of the multilayer wiring structure are formed in the top surface protective film 7 A.

Each pad opening 8 A has a quadrilateral shape in plan view and the same number thereof are provided at each edge of the semiconductor chip 2 A. The respective pad openings 8 A are disposed at equal intervals along the respective sides of the semiconductor chip 2 A. From each pad opening 8 A, a portion of the wiring layer is exposed as an electrode pad 9 A of the semiconductor chip 2 A.

The uppermost wiring layer exposed as the electrode pads 9 A is made of a metal material that contains Al (aluminum) and is specifically made of a metal material having Al as a main component (for example, an Al—Cu alloy, etc.).

Meanwhile, a rear surface metal 10 A that contains, for example, Au, Ni, Ag, etc., is formed on a rear surface 22 A (surface at the other side in the thickness direction) of the semiconductor chip 2 A.

The die pad 3 A is made, for example, of a metal thin plate (for example, Cu or 42 alloy (an alloy containing Fe-42% Ni) and has a larger quadrilateral shape (for example, approximately 2.7 mm square in plan view) than the semiconductor chip 2 A. Also, the die pad 3 A has a thickness of 190 to 210 μm (preferably, approximately 200 μm). A pad plating layer 11 A that contains Ag, etc., is formed on a top surface 31 A (surface at one side in the thickness direction) of the die pad 3 A.

The semiconductor chip 2 A and the die pad 3 A are bonded to each other in a state where the rear surface 22 A of the semiconductor chip 2 A and the top surface 31 A of the die pad 3 A face each other as bonded surfaces with a bonding material 12 A interposed between the rear surface 22 A and the top surface 31 A. The semiconductor chip 2 A is thereby supported by the die pad 3 A in an orientation where the top surface 21 A faces upward.

The bonding material 12 A is made, for example, of solder paste or other conductive paste. As the bonding material 12 A, an insulating paste, such as a silver paste, an alumina paste, may be applied and in this case, the rear surface metal 10 A and/or the pad plating layer 11 A may be omitted. Also, in the state where the semiconductor chip 2 A and the die pad 3 A are bonded, a thickness of the bonding material 12 A is, for example, 10 to 20 μm.

A rear surface 32 A (surface at the other side in the thickness direction) of the die pad 3 A is exposed from the resin package 6 A. A solder plating layer 13 A made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed other-side surface.

The electrode leads 4 A are made of the same metal thin plate (containing, for example, Cu or 42 alloy (Fe-42% Ni, etc.) as the die pad 3 A. The electrode leads 4 A are disposed at the periphery of the semiconductor chip 2 A with the same number thereof being disposed at both sides in respective directions orthogonal to respective side surfaces of the die pad 3 A. The electrode leads 4 A that face each side surface of the die pad 3 A are disposed at equal intervals in a direction parallel to the facing side surface. A length of each electrode lead 4 A in the direction of facing the die pad 3 A is, for example, 450 to 500 μm (preferably, approximately 500 μm). A lead plating layer 14 A that contains Ag, etc., is formed on a top surface 41 A (surface at one side in the thickness direction) of each electrode lead 4 A.

Meanwhile, a rear surface 42 A (surface at the other side in the thickness direction) of each electrode lead 4 A is exposed from the resin package 6 A. A solder plating layer 15 A made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed rear surface 42 A.

Each bonding wire 5 A is made of copper (for example, a high-purity copper of no less than 99.9999% (6N) purity or no less than 99.99% (4N) purity that may contain a minute amount of impurity). Each bonding wire 5 A includes a linearly-extending, cylindrical main body portion 51 A and includes a pad bond portion 52 A and a lead bond portion 53 A formed at respective ends of the main body portion 51 A and respectively bonded to an electrode pad 9 A and an electrode lead 4 A.

The main body portion 51 A is curved parabolically upward from the one end at the electrode pad 9 A side toward an outer side of the semiconductor chip 2 A and made impingent at an acute angle at the other end on the top surface 41 A of the electrode lead 4 A. An interval I between a lower end at a topmost portion of the main body portion 51 A and the top surface 21 A of the semiconductor chip 2 A is, for example, 150 to 170 μm (preferably, approximately 160 μm).

›MODE(S) FOR CARRYING OUT THE INVENTION · 2 of 12

The pad bond portion 52 A is smaller than the electrode pad 9 A in plan view. The pad bond portion 52 A has a humped shape in sectional view that integrally includes a disk-shaped base portion 54 A, which, at its other side in the thickness direction, enters uniformly into a top layer portion of the electrode pad 9 A, and a bell-shaped projecting portion 55 A projecting from the one side of the base portion 54 A and having a tip connected to the one end of the main body portion 51 A.

The lead bond portion 53 A has a wedge-like shape in sectional view that is relatively thick at the one end side close to the main body portion 51 A and becomes relatively thinner toward the other end side away from the main body portion 51 A.

In the semiconductor device 1 A, the entire top surface 21 A and side surfaces 28 A of the semiconductor chip 2 A, the entire top surface 31 A and side surfaces of the die pad 3 A, the entire top surfaces 41 A and side surfaces inside the resin package 6 A of the electrode leads 4 A, and the entire bonding wires 5 A are covered by an integral water-impermeable metal film 16 A.

The water-impermeable insulating film 16 A is made of an insulating material capable of preventing permeation of water and is made, for example, of silicon oxide, which is used as an interlayer insulating material, or silicon nitride, which is used as a material of the top surface protective film 7 A, etc. Also, the water-impermeable insulating film 16 A is thinner than the top surface protective film 7 A and is, for example, 0.5 to 3 μm thick.

As shown in FIG. 3A , in a vicinity of the pad bond portion 52 A of each bonding wire 5 A, the water-impermeable insulating film 16 A integrally covers an entirety of the electrode pad 9 A that protrudes to an outer side of the pad bond portion 52 A in plan view and an entirety of a top surface of the pad bond portion 52 A together with a top surface of the top surface protective film 7 A. A periphery edge of a bond interface (pad bond interface 17 A) of the electrode pad 9 A and the pad bond portion 52 A and a periphery edge of a bond interface (protective film lamination interface 18 A) of the electrode pad 9 A and the top surface protective film 7 A are thereby covered by the water-impermeable insulating film 16 A without any exposure whatsoever.

Meanwhile, as shown in FIG. 3B , in a vicinity of the lead bond portion 53 A of each bonding wire 5 A, the water-impermeable insulating film 16 A integrally covers an entirety of the top surface 41 A (lead plating layer 14 A) of the electrode lead 4 A and an entirety of a top surface of the lead bond portion 53 A. A periphery edge of a bond interface (lead bond interface 19 A) of the electrode lead 4 A and the lead bond portion 53 A is thereby covered by the water-impermeable insulating film 16 A without any exposure whatsoever.

As the resin package 6 A, a known material, such as an epoxy resin, may be applied. The resin package 6 A makes up an outer shape of the semiconductor device 1 A and is formed to a substantially rectangular parallelepiped shape. In terms of size, the resin package 6 A has a planar size, for example, of approximately 4 mm square and a thickness, for example, of approximately 0.85 mm.

With the semiconductor device 1 A, an interval L 1 between the top surface 21 A of the semiconductor chip 2 A and a top surface (upper surface) 61 A of the resin package 6 A is less than a minimum distance W between a side surface 28 A of the semiconductor chip 2 A and a side surface 63 A of the resin package 6 A. Specifically, the interval L 1 is, for example, 375 to 425 μm and preferably, approximately 400 μm, and the minimum distance W is, for example, 800 to 1000 μm and preferably, approximately 900 μm.

Also, the interval L 1 is no more than a distance L 2 (for example, of 425 to 475 μm and preferably, approximately 450 μm) between the top surface 21 A of the semiconductor chip 2 A and a rear surface 62 A of the resin package 6 A (rear surface 32 A of the die pad 3 A).

By being designed so that the interval L 1 is comparatively small as described above, the semiconductor device 1 A is formed as a thin type QFN package.

FIG. 4A to FIG. 4E are schematic sectional views for describing a method for manufacturing the semiconductor device of FIG. 2 in order of process.

To manufacture the semiconductor device 1 A, for example, first, a lead frame 20 A that includes a plurality of units each integrally having a die pad 3 A and electrode leads 4 A is prepared. In FIG. 4A to FIG. 4E , an entire view of the lead frame 20 A is abbreviated and the die pad 3 A and electrode leads 4 A of just a single unit necessary for mounting a single semiconductor chip 2 A are shown.

Next, a metal plating of Ag, etc., is applied to a top surface of the lead frame 20 A by a plating method. The pad plating layer 11 A and the lead plating layer 14 A are thereby formed at the same time.

Next, as shown in FIG. 4A , the semiconductor chips 2 A are die bonded via the bonding material 12 A to all die pads 3 A on the lead frame 20 A. An FAB (free air ball) is then formed on a tip portion (one end portion) of a bonding wire 5 A, held by a capillary 23 A of a wire bonder (not shown), by application of a current to the tip portion. The capillary 23 A then moves to a position directly above an electrode pad 9 A and descends so that the FAB contacts the electrode pad 9 A. In this process, a load (open arrows in FIG. 4A ) and ultrasonic waves (zigzag lines in FIG. 4A ) are applied from the capillary 23 A to the FAB and the FAB is thereby deformed according to a shape of a chamfer 24 A of the capillary 23 A. The one end portion of the bonding wire 5 A is thereby bonded as the pad bond portion 52 A to the electrode pad 9 A and a first bond is formed.

After the first bond has been formed, the capillary 23 A rises to a fixed height and moves to a position directly above an electrode lead 4 A. Then, as shown in FIG. 4B , the capillary 23 A descends again and the bonding wire 5 A contacts the electrode lead 4 A. In this process, a load (open arrows in FIG. 4B ) and ultrasonic waves (zigzag lines in FIG. 4B ) are applied from the capillary 23 A to the bonding wire 5 A so that the bonding wire 5 A deforms according to a shape of a face 25 A of the capillary 23 A and is bonded to the electrode lead 4 A (forming of a stitch bond 26 A and a tail bond 27 A).

›MODE(S) FOR CARRYING OUT THE INVENTION · 3 of 12

The capillary 23 A then rises and in a state where a tail of a fixed length is secured from a tip of the capillary 23 A, the bonding wire 5 A is broken from a position of the tail bond 27 A. The other end of the bonding wire 5 A bonded by the stitch bond 26 remains as the lead bond portion 53 A on the electrode lead 4 A and a second bond is thereby formed.

Thereafter, as shown in FIG. 4C , the same process as that of FIG. 4B is performed so that the respective electrode pads 9 A of all semiconductor chips 2 A and the electrode leads 4 A corresponding to the respective electrode pads 9 A are connected by the bonding wires 5 A.

After all of the wire bonding ends, an insulating material (silicon oxide, silicon nitride, etc.) is deposited by a CVD method onto each semi-finished semiconductor device 1 A, including the semiconductor chip 2 A, the bonding wires 5 A, and the electrode leads 4 A, under a temperature condition, for example, of 350 to 450° C. The water-impermeable insulating film 16 A that integrally covers the entire top surface 21 A and side surfaces 28 A of the semiconductor chip 2 A, the entire top surface 31 A and side surfaces of the die pad 3 A, the entire top surfaces 41 A and side surfaces of the electrode leads 4 A, and the entire bonding wires 5 A is thereby formed.

The CVD method is not restricted in particular and, for example, a known CVD method, such as a thermal CVD method, plasma CVD method, may be applied.

Next, as shown in FIG. 4E , the lead frame 20 A is set in a forming mold and all semiconductor chips 2 A are sealed in a batch together with the lead frame 20 A by the resin package 6 A. Solder plating layers 13 A and 15 A are then formed on the rear surfaces 32 A of the die pads 3 A and the rear surfaces 42 A of the electrode leads 4 A that are exposed from the resin package 6 A. Lastly, a dicing saw is used to cut the lead frame 20 A together with the resin package 6 A to sizes of the respective semiconductor devices 1 A and the individual semiconductor devices 1 A one of which is shown in FIG. 1 and FIG. 2 are thereby obtained.

As described above, with the semiconductor device 1 A, the entire top surface 21 A of the semiconductor chip 2 A, the entire top surface 31 A of the die pad 3 A, the entire top surfaces 41 A of the electrode leads 4 A, and the entire bonding wires 5 A are covered by the integral water-impermeable insulating film 16 A.

The periphery edge of the bond interface (pad bond interface 17 A) of each electrode pad 9 A and pad bond portion 52 A and the periphery edge of the bond interface (protective film lamination interface 18 A) of each electrode pad 9 A and the top surface protective film 7 A are thereby covered by the water-impermeable insulating film 16 A without any exposure whatsoever.

Thus, even if water penetrates into an interior of the resin package 6 A, the water can be blocked by the water-impermeable insulating film 16 A and contact of the pad bond interfaces 17 A with water can be suppressed. Consequently, progress of corrosion of the electrode pads 9 A can be suppressed and occurrence of electrically open states between pads and wires (electrically open states at the first bonds) can be suppressed. Connection reliability of the semiconductor device 1 A can thus be improved.

Especially, in a thin package, such as the semiconductor device 1 A, the pad bond portions 52 A on the semiconductor chip 2 A tend to be exposed to water entering into an interior of the package from the top surface 61 A of the resin package 6 A. However, even with such a thin-package semiconductor device 1 A, the connection reliability of the semiconductor device 1 A can be improved effectively by the water-impermeable insulating film 16 A.

Specifically, an electrically open state at a first bond is considered to occur by the following process.

For example, water (water vapor) may enter into the interior of the resin package 6 A through a gap between the resin package 6 A and the die pad 3 A or an electrode lead 4 A, etc., while a PCT, HAST, or other humidity resistance evaluation test is being performed.

Meanwhile, at each pad bond interface 17 A, a difference between an ionization tendency of Al contained in the material of the electrode pad 9 A and an ionization tendency of Cu of the bonding wire 5 A causes a voltaic cell, with the electrode pad 9 A containing the Al of higher ionization tendency as an anode and the bonding wire 5 A containing the Cu of lower ionization tendency as a cathode, to be formed.

When water contacts a pad bond interface 17 A, a minute current flows between the electrode pad 9 A and the bonding wire 5 A so that a reaction in which the Al of the electrode pad 9 A ionizes and supplies an electron to the Cu of the bonding wire 5 A is promoted, thereby promoting corrosion of the electrode pad 9 A.

On the other hand, with the semiconductor device 1 A, even if water penetrates into the interior of the resin package 6 A, contact of the penetrating water with the pad bond interfaces 17 A can be suppressed reliably as described above and progress of corrosion of the electrode pad 9 A can thus be suppressed.

Also, with the semiconductor device 1 A, the periphery edge of the bond interface (lead bond interface 19 A) of each electrode lead 4 A and the lead bond portion 53 A is covered by the water-impermeable insulating film 16 A without any exposure whatsoever. Thus, even if water penetrates into the interior of the resin package 6 A, the water can be blocked by the water-impermeable insulating film 16 A and contact of the lead bond interfaces 19 A with water can be suppressed. Consequently, the reliability of lead-wire connections can be maintained.

Also, the film that prevents the permeation of water is an insulating film and thus even if a metal portion besides the electrode pads 9 A is exposed at the top surface 21 A of the semiconductor chip 2 A, the metal portion is covered by the water-impermeable insulating film 16 A that covers the entire chip top surface 21 A. Contact of the metal portion with the water penetrating into the interior of the resin package 6 A can thus be suppressed. Consequently, corrosion of the metal portion can be suppressed. Also, mutual electrical insulation among such metal members as the metal portion, the electrode pads 9 A, and the bonding wires 5 A can be secured.

›MODE(S) FOR CARRYING OUT THE INVENTION · 4 of 12

Further, in forming the water-impermeable insulating film 16 A, the CVD method, which is a conventionally proven thin film forming technique, is used. The water-impermeable insulating film 16 A can thus be formed easily.

Also, the CVD method is excellent in step covering property and thus even if the form of bonding of the electrode pad 9 A with the pad bond portion 52 A is complex, the water-impermeable insulating film 16 A can be formed uniformly by suitably controlling the film forming conditions.

Also, in a case where the water-impermeable insulating film 16 A is formed by a thermal CVD method, the low directionality of the thermal CVD method enables the water-impermeable insulating film 16 A to wrap around even to a rear surface side of the bonding wire 5 A that is hidden due to overlapping of the bonding wire 5 A and the electrode lead 4 a in plan view as shown in FIG. 3B . Consequently, entire bonding wires 5 A can be covered more easily.

Also, the film forming conditions can be controlled to easily increase the thickness of the water-impermeable insulating film 16 A. By increasing the thickness of the water-impermeable insulating film 16 A, impacts transmitted to the electrode pads 9 A and the pad bond portions 52 A can be relaxed. Consequently, occurrence of cracks at the electrode pads 9 A and the pad bond portions 52 A can be suppressed.

FIG. 5 is a schematic sectional view of a semiconductor device according to a modification example of the semiconductor device shown in FIG. 2 . FIG. 6A is an enlarged view of principal portions of a portion surrounded by a broken-line circle A in FIG. 5 . FIG. 6B is an enlarged view of principal portions of a portion surrounded by a broken-line circle B in FIG. 5 . In FIG. 5 , and FIGS. 6A and 6B , portions corresponding to respective portions shown in FIG. 1 to FIGS. 3A and 3B are provided with the same reference symbols as the respective portions. Also, detailed description concerning portions provided with the same reference symbols shall be omitted in the following description.

With the semiconductor device 50 A, entire electrode pads 9 A, entire side surfaces of the die pad 3 A, entire side surfaces of the electrode leads 4 A inside the resin package 6 A, and entire bonding wires 5 A are covered by an integral water-impermeable metal film 43 A.

The water-impermeable metal film 43 A is made of a metal material capable of preventing the permeation of water and is made, for example, of nickel or palladium, etc., and is preferably made of nickel. The water-impermeable metal film 43 A is thinner than the top surface protective film 7 A and is, for example, 0.5 to 3 μm thick.

As shown in FIG. 6A , in the vicinity of the pad bond portion 52 A of each bonding wire 5 A, the water-impermeable metal film 43 A does not cover the top surface of the top surface protective film 7 A but integrally covers the entire electrode pad 9 A that protrudes to the outer side of the pad bond portion 52 A in plan view and the entire top surface of the pad bond portion 52 A. The periphery edge of the bond interface (pad bond interface 17 A) of the electrode pad 9 A and the pad bond portion 52 A is thereby covered by the water-impermeable metal film 43 A without any exposure whatsoever.

Meanwhile, as shown in FIG. 6B , in the vicinity of the lead bond portion 53 A of each bonding wire 5 A, the water-impermeable metal film 43 A integrally covers the entire top surface 41 A (lead plating layer) of the electrode lead 4 A and the entire top surface of the lead bond portion 53 A. The periphery edge of the bond interface (lead bond interface 19 A) of the electrode lead 4 A and the lead bond portion 53 A is thereby covered by the water-impermeable metal film 43 A without any exposure whatsoever.

Arrangements besides the above are the same as those of the first preferred embodiment described above.

FIG. 7A to FIG. 7E are schematic sectional views for describing a method for manufacturing the semiconductor device of FIG. 5 in order of process.

As shown in FIG. 7A to 7C , the same processes as those of FIG. 4A to FIG. 4C are performed to die-bond the semiconductor chips 2 A to all die pads 3 A on the lead frame 20 A, and the respective electrode pads 9 A of all semiconductor chips 2 A and the electrode leads 4 A corresponding to the respective electrode pads 9 A are connected by the bonding wires 5 A.

After all of the wire bonding ends, plating of a metal material (nickel, palladium, etc.) is applied by an electroless plating method to exposed metal portions of each semi-finished semiconductor device 50 A, including the electrode pads 9 A, the bonding wires 5 A, and the electrode leads 4 A. The water-impermeable metal film 43 A that integrally covers at least the portions made of Cu and Al, such as the entire electrode pads 9 A, the entire side surfaces of the die pads 3 A, the entire side surfaces of the electrode leads 4 A inside the resin package 6 A, and the entire bonding wires 5 A is thereby formed.

Thereafter, as shown in FIG. 7E , the same process as that of FIG. 4E is performed. That is, all semiconductor chips 2 A on the lead frame 20 A are sealed in a batch by the resin package 6 A and the lead frame 20 A is cut together with the resin package 6 A. The individual semiconductor devices 50 A one of which shown in FIG. 5 are thereby obtained.

As described above, with the semiconductor device 50 A, the entire electrode pads 9 A, the entire side surfaces of the die pads 3 A, the entire side surfaces of the electrode leads 4 A inside the resin package 6 A, and the entire bonding wires 5 A are covered by the integral water-impermeable metal film 43 A.

The periphery edge of the bond interface (pad bond interface 17 A) of each electrode pad 9 A and pad bond portion 52 A is thereby covered by the water-impermeable metal film 43 A without any exposure whatsoever.

Thus, even if water penetrates into the interior of the resin package 6 A, the water can be blocked by the water-impermeable metal film 43 A and contact of the pad bond interfaces 17 A with water can be suppressed. Consequently, progress of corrosion of the electrode pads 9 A can be suppressed and occurrence of electrically open states between pads and wires (electrically open states at the first bonds) can be suppressed. Connection reliability of the semiconductor device 50 A can thus be improved.

›MODE(S) FOR CARRYING OUT THE INVENTION · 5 of 12

Also, with the semiconductor device 50 A, the periphery edge of the bond interface (lead bond interface 19 A) of each electrode lead 4 A and the lead bond portion 53 A is covered by the water-impermeable metal film 43 A without any exposure whatsoever. Thus, even if water penetrates into an interior of the resin package 6 A, the water can be blocked by the water-impermeable metal film 43 A and contact of the lead bond interfaces 19 A with water can be suppressed. Consequently, the reliability of lead-wire connections can be maintained.

Also, the film that prevents the permeation of water is a metal film, and although depending on the type of material used, an alloy can thus be formed at an interface between the electrode pad 9 A and/or bonding wire 5 A and the water-impermeable metal film 43 A. The water-impermeable metal film 43 A can be improved in covering property by the forming of the alloy. In particular, a nickel film is an effective protective material against chemical corrosion and is low in cost. Further, aluminum readily forms an alloy with copper. Thus, by using a nickel film, the water-impermeable metal film 43 A of excellent covering property can be formed at low cost.

Although the first preferred embodiment of the present invention has been described above, the first preferred embodiment may also be modified as follows.

For example, although a QFN type semiconductor device was taken up in the above description of the preferred embodiment, the present invention may also be applied, for example, to a QFP (quad flat package) type semiconductor device 80 A such as shown in FIG. 8 (in FIG. 8, 71A indicates an electrode lead 71 A that integrally includes an inner lead 72 A sealed by the resin package 6 A and an outer lead 73 A exposed from the resin package 6 A). In this case, a mask is preferably applied to a rear surface 74 A of the outer lead 73 A to prevent deposition of insulation material on the rear surface 74 A of the outer lead 73 A during execution of the CVD method. Besides this, the present invention may also be applied to semiconductor devices of other package types such as SOP (small outline package).

Also, the water-impermeable insulating film 16 A may be formed using a spin coating method or other thin film forming technique besides the CVD method mentioned above.

Also, the water-impermeable insulating film 16 A may integrally cover just the entire top surfaces of the electrode pads 9 A and the entire top surfaces of the pad bond portions 52 A. To form such a water-impermeable insulating film 16 A, for example, an insulating material is dripped onto the pad bond portions 52 A by a known potting technique or other method after all of the wire bonding is ended.

Also, although with the above-described preferred embodiment, a case where the water-impermeable metal film 43 A is formed by the electroless plating method was taken up, the water-impermeable metal film 43 A may be formed by an electroplating method instead. For example, if, in a case where the bonding material 12 A is made of a conductive paste, the water-impermeable metal film 43 A is formed by the electroplating method, side surfaces of the bonding material 12 A and the top surfaces 41 A of the electrode leads 4 A will also be covered by the water-impermeable metal film 43 A as in a semiconductor device 90 A shown in FIG. 9 .

On the other hand, in a case where the bonding material 12 A is made of an insulating paste, although the water-impermeable metal film 43 A will be formed on the top surfaces 41 A of the electrode leads 4 A, it will not be formed on the side surfaces of the bonding material 12 A.

Second Preferred Embodiment FIG. 10 to FIG. 17

By disclosure of a second preferred embodiment, a second issue concerning a second background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Second Background Art

Semiconductor devices are normally distributed in a state where a semiconductor chip is sealed (packaged) together with bonding wires by a resin. Inside the package, electrode pads of the semiconductor chip are electrically connected by the bonding wires to electrode leads that are partially exposed from the resin package. Thus, by connecting the electrode leads as external terminals to wirings on a mounting board, electrical connection of the semiconductor chip and the mounting board is achieved.

Each bonding wire is connected to each of an electrode pad and an electrode lead using, for example, a wire bonder (not shown) that includes a capillary 91 B shown in FIG. 16 . The capillary 91 B has a substantially cylindrical shape with a straight hole 94 B, through which the bonding wire 90 B is inserted, formed at a center, and during wire bonding, the bonding wire 90 B is fed out from a tip of the straight hole 94 B.

A face portion 93 B, which has an annular shape in plan view and is substantially perpendicular to a longitudinal direction of the straight hole 94 B, and a chamfer portion 95 B, which is recessed in the longitudinal direction of the straight hole 94 B from the face portion 93 B, are formed at a tip portion of the capillary 91 B. A side surface 97 B of the chamfer portion 95 B is formed to a conical surface and a cross-sectional shape thereof extends rectilinearly from an inner circumferential circle of the face portion 93 B to a circumferential surface of the straight hole 94 B.

To form each first bond, which is a bond of a bonding wire and an electrode pad, first, a current is applied to a tip portion of the bonding wire 90 B held by the capillary 91 B and the wire material is melted by the heat of the resulting spark. The molten wire material becomes an FAB (free air ball) due to surface tension.

Next, the capillary 91 B moves to a position directly above an electrode pad 92 B and thereafter descends so that the FAB contacts the electrode pad 92 B. In this process, ultrasonic waves are applied to the FAB along a Y7 direction (hereinafter, “ultrasonic wave application direction Y7”) while a load is applied to the FAB by the capillary 91 B.

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A portion of the FAB is thereby made to spread below the face portion 93 B while another portion is pushed inside the straight hole 94 B and a remaining portion remains inside the chamfer portion 95 B. A first bond portion 96 B of humped shape in sectional view is thereby formed in accordance with the shape of the tip of the capillary 91 B.

(2) Second Issue

However, in a case where the cross-sectional shape of the side surface 97 B of the chamfer portion 95 B extends rectilinearly as in the capillary 91 B shown in FIG. 16 , the side surface 97 B of the chamfer portion 95 B forms corners with the circumferential surface of the straight hole 94 B and the end surface of the face portion 93 B. Thus, during bonding of the bonding wire 90 B, stress in a direction along the ultrasonic wave application direction Y7 may concentrate at specific locations of portions of the first bond portion 96 B inside the chamfer portion 95 B (specifically, portions between planar projection curves of a hole diameter H and a chamfer diameter CD of the capillary 91 B).

Thus, in the electrode pad 92 B and an interlayer insulating film 98 B below it, stress may concentrate and cause the interlayer insulating film 98 B to crack and become damaged at portions directly below the stress concentration locations of the first bond portion 96 B. Specifically, flaws that face each other in the ultrasonic wave application direction Y7 occur at portions between the planar projection curves of the hole diameter H and the chamfer diameter CD of the capillary 91 B in the interlayer insulating film 98 B in a state where the bonding wire 90 B is removed (see figure at lower side of FIG. 16 ).

Thus, a second object of the present invention related to the second preferred embodiment is to provide a semiconductor device and a method for manufacturing the semiconductor device, with which, in connecting an electrode pad and a bonding wire, stress applied to the electrode pad is relaxed to enable suppression of occurrence of damage below the electrode pad.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 10 is a schematic sectional view of a semiconductor device according to the second preferred embodiment of the present invention. FIG. 11 is an exploded plan view of the semiconductor device of FIG. 10 with a resin package removed. FIG. 12A is an enlarged view of a vicinity of an electrode pad of FIG. 11 . FIG. 12B is a sectional view taken along the sectioning line B-B of FIG. 12A . FIG. 12C is a sectional view taken along the sectioning line C-C of FIG. 12A . In FIG. 12B and FIG. 12C , a plan view of the electrode pad in a state where a bonding wire is removed is shown as a supplementary diagram.

The semiconductor device 1 B is a semiconductor device to which an SON (small outline non-leaded) configuration is applied. The semiconductor device 1 B includes a semiconductor chip 2 B, a die pad 3 B supporting the semiconductor chip 2 B, a plurality of electrode leads 4 B disposed at a periphery of the semiconductor chip 2 B, bonding wires 5 B electrically connecting the semiconductor chip 2 B and the electrode leads 4 B, and a resin package 6 B sealing the above components.

The semiconductor chip 2 B has a quadrilateral shape in plan view and has, for example, a multilayer wiring structure arranged by laminating a plurality of wiring layers via interlayer insulating films. The semiconductor chip 2 B has a thickness, for example, of 220 to 240 μm (preferably, approximately 230 μm). As shown in FIG. 12 , a top surface 21 B (surface at one side in a thickness direction) of the semiconductor chip 2 B is covered by a top surface protective film 7 B.

A plurality of pad openings 8 B for exposing an uppermost wiring layer of the multilayer wiring structure are formed in the top surface protective film 7 B.

Each pad opening 8 B has a quadrilateral shape in plan view and the same number thereof are provided at each of a pair of mutually opposing edge portions of the semiconductor chip 2 B. The respective pad openings 8 B are disposed at equal intervals along the edge portions. A portion of the wiring layer is exposed as an electrode pad 9 B of the semiconductor chip 2 B from each pad opening 8 B.

The uppermost wiring layer exposed as the electrode pads 9 B is made, for example, of a metal material containing Al (aluminum) and is specifically made of a metal material having Al as a main component (for example, an Al—Cu alloy, etc.).

Below each electrode pad 9 B is formed an interlayer insulating film 23 B for insulating the uppermost wiring layer and a wiring layer (lower wiring layer) below the uppermost wiring layer.

Meanwhile, a rear surface metal 10 B that contains, for example, Au, Ni, Ag, etc., is formed on a rear surface 22 B (surface at the other side in the thickness direction) of the semiconductor chip 2 B.

The die pad 3 B is made, for example, of a metal thin plate (for example, Cu or 42 alloy (an alloy containing Fe-42% Ni) and has a larger quadrilateral shape (for example, approximately 2.7 mm square in plan view) than the semiconductor chip 2 B in plan view. Also, the die pad 3 B has a thickness of 190 to 210 μm (preferably, approximately 200 μm). A pad plating layer 11 B that contains Ag, etc., is formed on a top surface 31 B (surface at one side in the thickness direction) of the die pad 3 B.

The semiconductor chip 2 B and the die pad 3 B are bonded to each other in a state where the rear surface 22 B of the semiconductor chip 2 B and the top surface 31 B of the die pad 3 B face each other as bond surfaces with a bonding material 12 B interposed between the rear surface 22 B and the top surface 31 B. The semiconductor chip 2 B is thereby supported by the die pad 3 B in an orientation where the top surface 21 B faces upward.

The bonding material 12 B is made, for example, of solder paste or other conductive paste. As the bonding material 12 B, an insulating paste, such as a silver paste, an alumina paste, may be applied, and in this case, the rear surface metal 10 B and/or the pad plating layer 11 B may be omitted. Also, in the state where the semiconductor chip 2 B and the die pad 3 B are bonded, a thickness of the bonding material 12 B is, for example, 10 to 20 μm.

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A rear surface 32 B (surface at the other side in the thickness direction) of the die pad 3 B is exposed from the resin package 6 B. A solder plating layer 13 B made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed other-side surface.

The electrode leads 4 B are made of the same metal thin plate (containing, for example, Cu or 42 alloy (Fe-42% Ni, etc.) as the die pad 3 B. The electrode leads 4 B are disposed at the periphery of the semiconductor chip 2 B, with the same number thereof being disposed at each of side surfaces, which, among the four side surfaces of die pad 3 B, are disposed at both sides of a direction orthogonal to the two side surfaces at the sides at which the electrode pads 9 B are disposed. The electrode leads 4 B that face each side surface of the die pad 3 B are disposed at equal intervals in a direction parallel to the facing side surface. A length of each electrode lead 4 B in the direction of facing the die pad 3 B is, for example, 240 to 260 μm (preferably, approximately 250 μm). A lead plating layer 14 B that contains Ag, etc., is formed on a top surface 41 B (surface at one side in the thickness direction) of each electrode lead 4 B.

Meanwhile, a rear surface 42 B (surface at the other side in the thickness direction) of each electrode lead 4 B is exposed from the resin package 6 B. A solder plating layer 15 B made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed rear surface 42 B.

Each bonding wire 5 B is made, for example, of copper (for example, a high-purity copper of no less than 99.9999% (6N) purity or no less than 99.99% (4N) purity that may contain a minute amount of impurity), or gold, etc. Each bonding wire 5 B includes a linearly-extending, cylindrical main body portion 51 B and includes a pad bond portion 52 B and a lead bond portion 53 B formed at respective ends of the main body portion 51 B and respectively bonded to an electrode pad 9 B and an electrode lead 4 B.

The main body portion 51 B is curved parabolically upward from the one end at the electrode pad 9 B side toward an outer side of the semiconductor chip 2 B and made impingent at an acute angle at the other end on the top surface 41 B of the electrode lead 4 B.

The pad bond portion 52 B is smaller than the electrode pad 9 B in plan view. The pad bond portion 52 B has a humped shape that integrally includes a substantially disk-shaped base portion 54 B, which, at its other side in the thickness direction, contacts a top surface of the electrode pad 9 B, a mesa portion 55 B, which is an intermediate portion formed at the one side of the base portion 54 , and a bell-shaped projecting portion 56 B projecting from the one side of the mesa portion 55 B and having a tip connected to the one end of the main body portion 51 B.

A top surface (surface formed by an upper surface 57 B of the base portion 54 B, a side surface 58 B of the mesa portion 55 B, and a side surface 59 B of the projecting portion 56 B) of the humped-shape pad bond portion 52 B is formed to a smooth shape without corners.

Specifically, the mesa portion 55 B disposed at a middle of the pad bond portion 52 B has the side surface 58 B, which, in a section taken perpendicular to the electrode pad 9 B, has a non-rectilinear cross-sectional shape that is curved at a uniform curvature across its entire periphery so as to bulge toward an interior of the pad bond portion 52 B and thereby decrease in diameter toward one side thereof.

The projecting portion 56 B at an upper side of the mesa portion 55 B has the side surface 59 B that is curved at a uniform curvature across its entire periphery so as to bulge toward an outer side of the pad bond portion 52 B and thereby decrease in diameter toward one side thereof with a circular upper end of the mesa portion 55 B as an inflection curve with respect to the side surface 58 B of the mesa portion 55 B.

The base portion 54 B at a lower side of the mesa portion 55 B has the planar upper surface 57 B, an entire periphery of which is formed by a collection of tangents to a circular lower end of the mesa portion 55 B.

The top surface of the pad bond portion 52 that is formed as a continuation of the surfaces 57 B to 59 B is thus formed to a smooth shape without corners.

The pad bond portion 52 B of such a shape can be formed by a wire bonding method using, for example, a capillary 16 B indicated by broken lines in FIG. 12 in a manufacturing process of the semiconductor device 1 B.

In the manufacturing process of the semiconductor device 1 B, a lead frame that includes a plurality of units each integrally having a die pad 3 B and electrode leads 4 B is conveyed in a X2 direction (hereinafter, “frame conveying direction X2” (the same applies in FIG. 12 )) of FIG. 11 , and mounting of the semiconductor chip 2 B, wire bonding across the electrode pads 9 B and the electrode leads 4 B, and other processes are applied to the conveyed lead frame to manufacture the semiconductor device 1 B.

In the wire bonding process, a wire bonder (not shown) including the capillary 16 B is used.

The capillary 16 B has a substantially cylindrical shape with a straight hole 17 B, through which the bonding wire 5 B is inserted, formed at a center, and during wire bonding, the bonding wire 5 B is fed out from a tip of the straight hole 17 B.

A face portion 18 B, which is substantially perpendicular to a longitudinal direction of the straight hole 17 B and, in plan view, has an annular shape concentric to the straight hole 17 B, and a chamfer portion 19 B, which is recessed in the longitudinal direction of the straight hole 17 B from the face portion 18 B, are formed at a tip portion of the capillary 16 B.

A side surface 20 B of the chamfer portion 19 B is formed to a non-rectilinear curve in sectional view that bulges toward an interior of the straight hole 17 B at a uniform curvature across its entire circumference from an inner circumferential circle of the face portion 18 B to a circumferential surface of the straight hole 17 B.

›MODE(S) FOR CARRYING OUT THE INVENTION · 8 of 12

To form the pad bond portion 52 B using the capillary 16 B, for example, a current is first applied to the tip portion (one end portion) of the bonding wire 5 B held by the capillary 16 B to form an FAB (free air ball) at the tip portion.

Next, the capillary 16 B moves to a position directly above an electrode pad 9 B and thereafter descends while maintaining parallelism of the electrode pad 9 B and the face portion 18 B so that the FAB contacts the electrode pad 9 B. In this process, ultrasonic waves are applied to the FAB along a Y2 direction (hereinafter, “ultrasonic wave application direction Y2” (the same applies in FIG. 12 )) orthogonal to the frame conveying direction X2 while a load is applied to the FAB by the capillary 16 B, and a portion of the FAB is thereby made to spread below the face portion 18 B to form the base portion 54 B while another portion is pushed inside the straight hole 17 B to form the projecting portion 56 B. The mesa portion 55 B is formed by the remaining portion that remains inside the chamfer portion 19 B. The one end portion of the bonding wire 5 B is thereby bonded as the pad bond portion 52 B to the electrode pad 9 B and a first bond is formed.

With the pad bond portion 52 B formed using the capillary 16 B, the mesa portion 55 B is formed according to the shape of the side surface 20 B of the chamfer portion 19 B, and thus the side surface 58 B of the mesa portion 55 B is formed so that a cross-sectional shape when a section is taken along the ultrasonic wave application direction Y2 is that depicted by line-symmetrical hyperbolic curves (curves) having a normal to the electrode pad 9 B as a symmetry axis.

The lead bond portion 53 B has a wedge-like shape in sectional view that is relatively thick at the one end side close to the main body portion 51 B and becomes relatively thin toward the other end side away from the main body portion 51 B.

As in the first preferred embodiment, in the semiconductor device 1 B, the entire top surface 21 B and side surfaces 28 B of the semiconductor chip 2 B, the entire top surface 31 B and side surfaces of the die pad 3 B, the entire top surfaces 41 B and side surfaces inside the resin package 6 B of the electrode leads 4 B, and the entire bonding wires 5 B are covered by an integral water-impermeable insulating film 24 B.

As the resin package 6 B, a known material, such as an epoxy resin, may be applied. The resin package 6 B makes up an outer shape of the semiconductor device 1 B and is formed to a substantially rectangular parallelepiped shape. In terms of size, the resin package 6 B has a planar size, for example, of approximately 4 mm square and a thickness, for example, of 0.60 to 0.70 mm and preferably, approximately 0.65 mm.

As described above, with the semiconductor device 1 B, the pad bond portion 52 B of the bonding wire 5 B is formed using the capillary 16 B that has the chamfer portion 19 B having the side surface 20 B (curved surface) that bulges toward an interior of the straight hole 17 B. The side surface 58 B of the mesa portion 55 B of the pad bond portion 52 B is thereby formed so that a cross-sectional shape when a section is taken along the ultrasonic wave application direction Y2 is that depicted by line-symmetrical hyperbolic curves (curves) having a normal to the electrode pad 9 B as a symmetry axis.

For example, if in the pad bond portion 52 B, the side surface of the portion formed in accordance with the shape of the chamfer portion 19 B of the capillary 16 B is a flat surface indicated by broken line a in FIG. 12 or a curved surface indicated by broken lines b that bulges outward of the pad bond portion 52 B, stress may concentrate at specific locations of the mesa portion 55 B.

On the other hand, with a curved surface such as the side surface 58 B that bulges toward an interior of the pad bond portion 52 B, stress applied to the mesa portion 55 B of the pad bond portion 52 B during the forming of the pad bond portion 52 B can be dispersed across the entire side surface 58 B of the mesa portion 55 B and prevented from concentrating at specific locations of the mesa portion 55 B. Consequently, stress applied to the electrode pad 9 B can be relaxed and occurrence of damage in the interlayer insulating film 23 B below the electrode pad 9 B can be suppressed. That is, as shown in FIG. 12B and FIG. 12C , with the semiconductor device 1 B, notable damage does not occur at the interlayer insulating film 23 B in the state where the bonding wire 5 B is removed.

Also, the side surface 58 B of the mesa portion 55 B is formed as a curved surface that is curved at a uniform curvature across its entire circumference and thus stress applied to the mesa portion 55 B can be dispersed efficiently across the entire side surface 58 B of the mesa portion 55 B. Stress applied to the electrode pad 9 B can thus be relaxed further.

In consideration of a case where the bonding wire 5 B is made of copper, the load and ultrasonic waves applied in forming the pad bond portion 52 B must be made greater than those in a case of using a gold wire because copper is harder and more difficult to deform than gold.

Stress applied to the mesa portion 55 B of the pad bond portion 52 B is thus greater than that in the case using the gold wire and when such a large stress is applied to the electrode pad 9 B, not only may the interlayer insulating film 23 B become damaged but a crack or other large damage may occur in the semiconductor chip 2 B as well.

However, with the above-described shape of the side surface 58 B of the mesa portion 55 B, even if a large stress is applied, the stress can be relaxed effectively. Damaging of the interlayer insulating film 23 B and occurrence of crack in the semiconductor chip 2 B can thus be suppressed.

Although the second preferred embodiment of the present invention has been described above, the second preferred embodiment may also be modified as follows.

For example, although in the preferred embodiment, the side surface 20 B of the chamfer portion 19 B has a cross-sectional shape that is a non-rectilinear curve across its entire circumference, a portion may be of a curved shape and a remaining portion may be rectilinear as shown in FIG. 13A to FIG. 13C . In this case, the ultrasonic waves for the first bond are applied along a Y4 direction (hereinafter, “ultrasonic wave application direction Y4”) that intersects the curved-shape portion of the side surface 20 B. A side surface (curved surface) 43 having a curved cross-sectional shape when sectioning is performed along the ultrasonic wave application direction Y4 and a side surface (flat surface) 44 having a rectilinear cross-sectional shape when sectioning is performed along a direction (for example, the frame conveying direction X4) intersecting the ultrasonic wave application direction Y4 are thereby formed on the mesa portion 55 B.

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Also, the side surface of non-rectilinear shape in sectional view of the mesa portion 55 B is not required to have a curved shape and may, for example, be a side surface 45 B with a cross-sectional shape that is a curved waveform (for example, an arcuate waveform, sinusoidal waveform, etc.) as shown in FIG. 14 or a side surface 46 B with a cross-sectional shape that is a rectilinear waveform (for example, a triangular waveform, etc.). The side surface 45 B and the side surface 46 B can be formed by the capillary 16 B having the chamfer portion 19 B with the side surface 20 B formed in accordance with the corresponding cross-sectional shape. In FIG. 14 and FIG. 15 , Y5 and Y6 indicate ultrasonic wave application directions Y5 and Y6, respectively, and X5 and X6 indicate frame conveying directions X5 and X6, respectively.

Also, although with the preferred embodiment described above, a mode in which the bonding wires 5 B are covered by the water-impermeable insulating film 24 B was described as an example, the water-impermeable insulating film 24 B may be omitted as shown in FIG. 17 as long as at least the second object for resolving the second issue is achieved.

Also, although an SON type semiconductor device was taken up in the above description of the preferred embodiment, the present invention may also be applied to semiconductor devices of other package types, for example, QFN (quad flat non-leaded), QFP (quad flat package), SOP (small outline package), etc.

Third Preferred Embodiment FIG. 18 to FIG. 26

By disclosure of a third preferred embodiment, a third issue concerning a third background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Third Background Art

Semiconductor devices are normally distributed in a state where a semiconductor chip is sealed (packaged) together with bonding wires by a resin. Inside the package, electrode pads of the semiconductor chip are electrically connected by the bonding wires to electrode leads that are partially exposed from the resin package. Thus, by connecting the electrode leads as external terminals to wirings on a mounting board, electrical connection of the semiconductor chip and the mounting board is achieved.

Although conventionally, gold wires are mainly used as the bonding wires connecting the electrode pads and the electrode leads, recently, the use of copper wires, which are cheaper than gold wires, is being examined for reducing the use of high-priced gold.

A first bond, which is a bond of a bonding wire and an electrode pad, is formed, for example, by first applying a current to a tip portion of a bonding wire held by a capillary of a wire bonder and melting the wire material by heat of a resulting spark. The molten wire material becomes an FAB (free air ball) due to surface tension.

Next, the capillary moves to a position directly above an electrode pad and thereafter descends so that the FAB contacts the electrode pad. In this process, a load and ultrasonic waves are applied to the FAB by the capillary. The FAB is thereby deformed in accordance with a shape of the tip of the capillary and a first bond portion is formed.

(2) Third Issue

Copper excels over gold in thermal conductivity and electrical conductivity and thus by adoption of copper wires, improvement in thermal conductivity and electrical conductivity of bonding wires is anticipated in addition to reduction in cost.

However, generally in forming the first bond, a capillary made of a ceramic-based material with a thermal conductivity of 3 to 5 W/m·K is used. Thus, to prevent non-melting of the wire and form, an FAB with stability, an FAB having a diameter of approximately 2.5 times a wire diameter must be formed intentionally.

Thus, when a copper wire that is thick with respect to electrode pads of narrow pitch is used, a problem such as protrusion of the FAB from the electrode pad, occurs during bonding. The wire diameter of the copper wire used is thus calculated back from the pitch of the electrode pads and an FAB diameter suited for the pitch and must be made comparatively thin in a case of bonding to electrode pads of narrow pitch. There is thus a problem that effective use of the excellent thermal conductivity and electrical conductivity of copper wires cannot be made.

Thus, a third object of the present invention related to the third preferred embodiment is to provide a semiconductor device that is made low in cost and capable of being improved in thermal conductivity and electrical conductivity of bonding wires by use of bonding wires made of copper.

Yet another object is to provide a method for manufacturing semiconductor device with which, in bonding a bonding wire made of copper and an electrode pad, a metal ball of comparatively small diameter can be formed with stability at a tip portion of the bonding wire.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 18 is a schematic bottom view of a semiconductor device according to the third preferred embodiment of the present invention. FIG. 19 is a schematic sectional view of the semiconductor device according to the third preferred embodiment of the present invention. FIG. 20 is an enlarged view of a portion surrounded by a broken-line circle in FIG. 19 . FIG. 21 is a conceptual diagram for determining a volume of a pad bond portion.

The semiconductor device 1 C is a semiconductor device to which a QFN (quad flat non-leaded) configuration is applied. The semiconductor device 1 C includes a semiconductor chip 2 C, a die pad 3 C supporting the semiconductor chip 2 C, a plurality of electrode leads 4 C disposed at a periphery of the semiconductor chip 2 C, bonding wires 5 C electrically connecting the semiconductor chip 2 C and the electrode leads 4 C, and a resin package 6 C sealing the above components.

The semiconductor chip 2 C has a quadrilateral shape in plan view and has, for example, a multilayer wiring structure arranged by laminating a plurality of wiring layers via interlayer insulating films. Also, the semiconductor chip 2 C has a thickness, for example, of 220 to 240 μm (preferably, approximately 230 μm). As shown in FIG. 20 , a top surface 21 C (surface at one side in a thickness direction) of the semiconductor chip 2 C is covered by a top surface protective film 7 C.

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A plurality of pad openings 8 C for exposing an uppermost wiring layer of the multilayer wiring structure are formed in the top surface protective film 7 C.

Each pad opening 8 C has a quadrilateral shape in plan view and the same number thereof are provided at each edge of the semiconductor chip 2 C. The respective pad openings 8 C are disposed at equal intervals along the respective sides of the semiconductor chip 2 C. A portion of the wiring layer is exposed as an electrode pad 9 C of the semiconductor chip 2 C from each pad opening 8 C.

The uppermost wiring layer exposed as the electrode pads 9 C is made, for example, of a metal material that contains Al (aluminum) and is specifically made of a metal material having Al as a main component (for example, an Al—Cu alloy, etc.).

Meanwhile, a rear surface metal 10 C that contains, for example, Au, Ni, Ag, etc., is formed on a rear surface 22 C (surface at the other side in the thickness direction) of the semiconductor chip 2 C.

The die pad 3 C is made, for example, of a metal thin plate (for example, Cu or 42 alloy (an alloy containing Fe-42% Ni) and has a larger quadrilateral shape (for example, approximately 2.7 mm square in plan view) than the semiconductor chip 2 C in plan view. Also, the die pad 3 C has a thickness of 190 to 210 μm (preferably, approximately 200 μm). A pad plating layer 11 C that contains Ag, etc., is formed on a top surface 31 C (surface at one side in the thickness direction) of the die pad 3 C.

The semiconductor chip 2 C and the die pad 3 C are bonded to each other in a state where the rear surface 22 C of the semiconductor chip 2 C and the top surface 31 C of the die pad 3 C face each other as bond surfaces with a bonding material 12 C interposed between the rear surface 22 C and the top surface 31 C. The semiconductor chip 2 C is thereby supported by the die pad 3 C in an orientation where the top surface 21 C faces upward.

The bonding material 12 C is made, for example, of solder paste or other conductive paste. As the bonding material 12 C, an insulating paste, such as a silver paste, an alumina paste, may be applied and in this case, the rear surface metal 10 C and/or the pad plating layer 11 C may be omitted. Also, in the state where the semiconductor chip 2 C and the die pad 3 C are bonded, a thickness of the bonding material 12 C is, for example, 10 to 20 μm.

A rear surface 32 C (surface at the other side in the thickness direction) of the die pad 3 C is exposed from the resin package 6 C. A solder plating layer 13 C made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed other-side surface.

The electrode leads 4 C are made of the same metal thin plate (containing, for example, Cu or 42 alloy (Fe-42% Ni, etc.) as the die pad 3 C. The electrode leads 4 C are disposed at the periphery of the semiconductor chip 2 C with the same number thereof being disposed at both sides in respective directions orthogonal to respective side surfaces of the die pad 3 C. The electrode leads 4 C that face each side surface of the die pad 3 C are disposed at equal intervals in a direction parallel to the facing side surface. A length of each electrode lead 4 C in the direction of facing the die pad 3 C is, for example, 240 to 260 μm (preferably, approximately 250 μm). A lead plating layer 14 C that contains Ag, etc., is formed on a top surface 41 C (surface at one side in the thickness direction) of each electrode lead 4 C.

Meanwhile, a rear surface 42 C (surface at the other side in the thickness direction) of each electrode lead 4 C is exposed from the resin package 6 C. A solder plating layer 15 C made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed rear surface 42 C.

Each bonding wire 5 C is made of copper (for example, a high-purity copper of no less than 99.9999% (6N) purity or no less than 99.99% (4N) purity that may contain a minute amount of impurity). Each bonding wire 5 C includes a linearly-extending, cylindrical main body portion 51 C and includes a pad bond portion 52 C and a lead bond portion 53 C formed at respective ends of the main body portion 51 C and respectively bonded to an electrode pad 9 C and an electrode lead 4 C.

The main body portion 51 C is curved parabolically upward from the one end at the electrode pad 9 C side toward an outer side of the semiconductor chip 2 C and made impingent at an acute angle at the other end on the top surface 41 C of the electrode lead 4 C.

The pad bond portion 52 C is smaller than the electrode pad 9 C in plan view. The pad bond portion 52 C has a humped shape in sectional view that integrally includes a substantially cylindrical base portion 54 C, which, at its other side in the thickness direction, contacts a top surface of the electrode pad 9 C, and a substantially umbrella-shaped projecting portion 55 C projecting from the one side of the base portion 54 C and having a tip connected to the one end of the main body portion 51 C.

Also, with the bonding wire 5 C, ratio (V/(D w ) 3 ) of a volume V of the pad bond portion 52 C with respect to a cube of a wire diameter D w of the main body portion 51 C (diameter of the main body portion 51 C) is 1.8 to 5.6.

The volume V of the pad bond portion 52 C is determined, for example, by determining a volume V b of the substantially cylindrical base portion 54 C and a volume V p of the substantially umbrella-shaped projecting portion 55 C as approximate values and adding the approximate values.

The volume V b of the base portion 54 C can be determined as an approximate value based on a volume of a cylinder with a diameter D b and a height H b which the base portion 54 C is conceptually deemed to be as shown in FIG. 21 . That is, the volume V b of the base portion 54 C can be expressed as V b ≈π(D b /2) 2 ·H b .

Meanwhile, the projecting portion 55 C has a substantially umbrella-like shape formed by using a cone as a base and forming a top portion of the cone to a cylindrical shape having a height direction as an axis, and thus the volume Vp of the projecting portion 55 C can be determined as an approximate value based on a volume of a cone with a diameter Dp and a height Hp which the projecting portion 55 C is conceptually deemed to be as shown in FIG. 21 . That is, the volume Vp of the projecting portion 55 C can be expressed as Vb≈π(Dp/2)2·Hp/3.

›MODE(S) FOR CARRYING OUT THE INVENTION · 11 of 12

The lead bond portion 53 C has a wedge-like shape in sectional view that is relatively thick at the one end side close to the main body portion 51 C and becomes relatively thinner toward the other end side away from the main body portion 51 C.

As in the first preferred embodiment, in the semiconductor device 1 C, the entire top surface 21 C and side surfaces 28 C of the semiconductor chip 2 C, the entire top surface 31 C and side surfaces of the die pad 3 C, the entire top surfaces 41 C and side surfaces inside the resin package 6 C of the electrode leads 4 C, and the entire bonding wires 5 C are covered by an integral water-impermeable insulating film 25 C.

As the resin package 6 C, a known material, such as an epoxy resin, may be applied. The resin package 6 C makes up an outer shape of the semiconductor device 1 C and is formed to a substantially rectangular parallelepiped shape. In terms of size, the resin package 6 C has a planar size, for example, of approximately 4 mm square and a thickness, for example, of 0.60 to 0.70 mm and preferably, approximately 0.65 mm.

FIG. 22A to FIG. 22E are schematic sectional views for describing a method for manufacturing the semiconductor device shown in FIG. 19 in order of process.

To manufacture the semiconductor device 1 C, for example, first, a lead frame 20 C that includes a plurality of units each integrally having a die pad 3 C and electrode leads 4 C is prepared. In FIG. 22A to FIG. 22E , an entire view of the lead frame 20 C is abbreviated and the die pad 3 C and electrode leads 4 C of just a single unit necessary for mounting a single semiconductor chip 2 C are shown.

Next, a metal plating of Ag, etc., is applied to a top surface of the lead frame 20 C by a plating method. The pad plating layer 11 C and the lead plating layer 14 C are thereby formed at the same time.

Next, as shown in FIG. 22A , the semiconductor chips 2 C are die bonded via the bonding material 12 C to all die pads 3 C on the lead frame 20 C.

Next, bonding of each bonding wire 5 C is performed by a wire bonder (not shown) that includes a capillary 23 C.

The capillary 23 C included in the wire bonder is made of a material with a thermal conductivity of 15 to 45 W/m·K and preferably, 17 to 43 W/m·K. Specifically, the capillary is made of polycrystalline ruby (with a thermal conductivity, for example, of approximately 17 to 19 W/m·K) or monocrystalline ruby (with a thermal conductivity, for example, of approximately 41 to 43 W/m·K).

The capillary 23 C has a substantially cylindrical shape with a straight hole 17 C, through which the bonding wire 5 C is inserted, formed at a center, and during wire bonding, the bonding wire 5 C is fed out from a tip of the straight hole 17 C.

A face portion 18 C, which is substantially perpendicular to a longitudinal direction of the straight hole 17 C and, in plan view, has an annular shape concentric to the straight hole 17 C, and a chamfer portion 19 C, which is recessed in the longitudinal direction of the straight hole 17 C from the face portion 18 C, are formed at a tip portion of the capillary 23 C.

A side surface 16 C of the chamfer portion 19 C is formed to a conical surface connecting an inner circumferential circle of the face portion 18 C and a circumferential surface of the straight hole 17 C. The side surface 16 C is thus rectilinear in sectional view and in the present preferred embodiment, an apex angle (chamfer angle) thereof is set, for example, to 90°.

In the wire bonding process, first, a current is applied to a tip portion (one end portion) of the bonding wire 5 C held by the capillary 23 C to forma spherical FAB 24 C (free air ball) at the tip portion. The applied current I is set to a larger value the larger the wire diameter D w of the main body portion 51 C, and for example, I=40 mA when D w =25 μm, I=60 mA when D w =30 μm, and I=120 mA when D w =38 μm. A current application time is set to an appropriate length according to a diameter D f of the FAB 24 C.

A volume V f of the FAB 24 C thus formed may be expressed using the diameter D f of the FAB 24 C as V f =4/3·π·(D f /2) 3 .

Next, as shown in FIG. 22B , the capillary 23 C moves to a position directly above an electrode pad 9 C and thereafter descends so that the FAB 24 C contacts the electrode pad 9 C. In this process, a load (open arrows in FIG. 22B ) and ultrasonic waves (zigzag lines in FIG. 22B ) are applied from the capillary 23 C to the FAB 24 C. The applied load W is set in accordance with the wire diameter D w of the main body portion 51 C and the intended diameter D b of the base portion 54 C and, for example, W=80 g when D w =25 μm and D b =46 μm, W=130 g when D w =30 μm and D b =60 μm, and W=240 g when D w =38 μm and D b =85 μm. Also, the applied ultrasonic waves, in terms of output values of the apparatus, are of 120 kHz and 50 to 120 mA.

A portion of the FAB 24 C is thereby made to spread below the face portion 18 C to form the base portion 54 C while the remaining portion of the FAB 24 C remains inside the chamfer portion 19 C while being pushed inside the straight hole 17 C to form the projecting portion 55 C. The one end portion of the bonding wire 5 C is thereby bonded as the pad bond portion 52 C to the electrode pad 9 C and a first bond is formed.

Thereby, at the projecting portion 55 C, a conical surface with a planar shape in sectional view is formed along the side surface 16 C of the chamfer portion 19 C. Thus, in computing the volume V p of the projecting portion 55 C, a diameter (chamfer diameter) CD of the chamfer portion 19 C may be used in place of the diameter D p of the cone, and in a case where the chamfer angle is 90°, CD/2 may be used in place of the height H p .

After the first bond has been formed, the capillary 23 C rises to a fixed height and moves to a position directly above an electrode lead 4 C. Then, as shown in FIG. 22C , the capillary 23 C descends again and the bonding wire 5 C contacts the electrode lead 4 C. In this process, a load (open arrows in FIG. 22C ) and ultrasonic waves (zigzag lines in FIG. 22C ) are applied from the capillary 23 C to the bonding wire 5 C so that the bonding wire 5 C deforms according to the shape of the face portion 18 C of the capillary 23 C and is bonded to the electrode lead 4 C (forming of a stitch bond 26 C and a tail bond 27 C).

›MODE(S) FOR CARRYING OUT THE INVENTION · 12 of 12

The capillary 23 C then rises and in a state where a tail of a fixed length is secured from a tip of the capillary 23 C, the bonding wire 5 C is broken from a position of the tail bond 27 C. The other end of the bonding wire 5 C that has been stitch bonded thus remains as the lead bond portion 53 C on the electrode lead 4 C and a second bond is thereby formed.

Thereafter, as shown in FIG. 22D , the same processes as those of FIG. 22A to 22C are performed so that the respective electrode pads 9 C of all semiconductor chips 2 C and the electrode leads 4 C corresponding to the respective electrode pads 9 C are connected by the bonding wires 5 C.

After all of the wire bonding ends, the water-impermeable insulating film 25 C is formed by the same method as that of FIG. 4D . After the forming of the water-impermeable insulating film 25 C, the lead frame 20 C is set in a forming mold and all semiconductor chips 2 C are sealed in a batch together with the lead frame 20 C by the resin package 6 C as shown in FIG. 22E . Solder plating layers 13 C and 15 C are then formed on the rear surfaces 32 C of the die pads 3 C and the rear surfaces 42 C of the electrode leads 4 C that are exposed from the resin package 6 C. Lastly, a dicing saw is used to cut the lead frame 20 C together with the resin package 6 C to sizes of the respective semiconductor devices 1 C and the individual semiconductor devices 1 C one of which is shown in FIG. 19 are thereby obtained.

As described above, with the present manufacturing method, the capillary 23 C made of the material with a thermal conductivity of 15 to 45 W/m·K is used in forming the FAB 24 C of the bonding wire 5 C made of copper. The FAB 24 C of comparatively small diameter, with which a magnitude (D f /D w ) of the diameter D f with respect to the wire diameter D w of the main body portion 51 C of the bonding wire 5 C is 1.5 to 2.2 times can thereby be formed with stability. For example, in a case where the wire diameter D w =25 μm, the FAB 24 C with a D f /D w of no less than 1.5 can be formed with stability, in a case where the wire diameter D w =30 μm, the FAB 24 C with a D f /D w of no less than 1.8 can be formed with stability, and in a case where the wire diameter D w =38 μm, the FAB 24 C with a D f /D w of no less than 1.9 can be formed with stability.

The volume V f of the FAB 24 C with the diameter D f is 1.8 to 5.6 times the cube of the wire diameter D w of the main body portion 51 C (that is, V f /(D w ) 3 =1.8 to 5.6).

The pad bond portion 52 C formed by the FAB 24 C of the above-described diameter being ultrasonically vibrated while being pressed by the capillary 23 C thus has a volume V of 1.8 to 5.6 times the cube of the wire diameter D w of the main body portion 51 C. That is, the ratio (V/(D w ) 3 ) of the volume V of the pad bond portion 52 C with respect to the cube of the wire diameter D w of the main body portion 51 C is 1.8 to 5.6.

By computing the volume V f of the FAB 24 C and the volume V of the pad bond portion 52 C, for example, under the following computing conditions, it is confirmed that (Computing conditions) Diameter D f of the FAB 24 C=60 μm, chamfer diameter CD of the capillary 23 C=66 μm, chamfer angle=90°, diameter D b of the base portion 54 C of the pad bond portion 52 C=76 μm, and height H b of the base portion 54 C of the pad bond portion 52 C=18 μm.

In this case, the volume V f of the FAB 24 C is: V f =4/3·π·(D f /2) 3 =4/3·π·(30) 3 ≈113,040 μm 3 .

Meanwhile, the volume V of the pad bond portion 52 C is (volume V b of the base portion 54 C)+(volume V p of the projecting portion 55 C) and thus, V={π(D b /2) 2 ·H b }+{π(D p /2) 2 ·H p /3}. As described above, D p is CD and H p is CD/2 and thus, the volume V of the pad bond portion 52 C is: V={π(76/2) 2 ·18}+{π(66/2) 2 ·(66/2)/3}≈81,615+37614=119,229 μm 3 .

Based on (the volume V of the pad bond portion 52 C)−(the volume V f of the FAB 24 C), the error between the volumes is 6189 μm 3 , and this is approximately 5% of each of the volumes. The volume V of the pad bond portion 52 C is an approximate value. Thus, by computing the volume V of the pad bond portion 52 C, the volume V f of the FAB 24 C used in forming the pad bond portion 52 C can be determined.

Comparatively thick bonding wires can thus be used regardless of the magnitude of the pitch of the electrode pads 9 C and thus the bonding wires 5 C can be improved in thermal conductivity and electrical conductivity. Also, the cost can be reduced in comparison to a case where gold wires are used because copper wires are used.

The applied current I during forming of the FAB 24 C is set to a larger value the greater the wire diameter D w of the main body portion 51 C, and the FAB 24 C that is closer to a true sphere can thus be formed with high efficiency.

Although the third preferred embodiment of the present invention has been described above, the third preferred embodiment may also be modified as follows.

For example, although a QFN type semiconductor device was taken up in the above description of the preferred embodiment, the present invention may also be applied to semiconductor devices of other package types, for example, the QFP (quad flat package), SOP (small outline package), etc.

Also, although with the above-described preferred embodiment, a mode in which the bonding wires 5 C are covered by the water-impermeable insulating film 25 C was described as an example, the water-impermeable insulating film 25 C may be omitted as shown in FIG. 23 as long as at least the third object for resolving the third issue is achieved.

Next, experiments related to the third preferred embodiment were performed. The present invention is not restricted by the following examples.

›Examples89

›Example 1 · 1 of 5

A copper bonding wire of 38 μm wire diameter was held by a capillary (made of polycrystalline ruby; thermal conductivity: 17.7 W/m·K) and by applying a 120 mA current to a tip portion of the wire for 650 μsec, a 70 μm diameter FAB (FAB diameter/wire diameter=1.84; FAB volume/(wire diameter) 3 =3.27) was prepared. The above operation was performed on each of 200 copper bonding wires.

Electron beam scanning of the FAB of each bonding wire was then performed using a scanning electron microscope (SEM) and SEM images were obtained by image processing of information detected thereby. By observation of the SEM images obtained, the shape of each FAB was judged from among the modes indicated below SEM images of the respective shape modes are shown in FIG. 24 . In FIG. 24 , a numeral indicated at an upper left of each SEM image indicates the number of bonding wires of the corresponding mode. For example, “168/200” indicated for a true sphere mode indicates that of the 200 bonding wires, the FAB shape was of the true sphere mode with 168 bonding wires.

(Types of Shape Modes)

True sphere: The FAB is a true sphere and a center thereof is positioned along an axis of the bonding wire.

Off-center: Although the FAB is a true sphere, the position of the center thereof slightly deviates from the axis of the bonding wire.

Club: The FAB has a shape similar to a golf club head.

Unmelted: The bonding wire did not melt sufficiently and an FAB could not be formed.

Examples 2 to 9

FABs were prepared on each of three types of copper bonding wires of different wire diameters (wire diameter=38 μm, 30 μm, and 25 μm) using the same capillary as that of Example 1, with the exception of Example 5. In Example 5, a capillary made of monocrystalline ruby and having thermal conductivity of 43.0 W/m·K was used.

Thereafter, by the same method as that of Example 1, SEM images of the FABs of the respective bonding wires were observed to judge the shape of each FAB from among the modes indicated below. The SEM images obtained are shown in FIG. 24 to FIG. 26 . The wire diameters of the wires, the FAB diameters, and the current application conditions are as indicated in the respective figures.

Comparative Example 1

A copper bonding wire of 38 μm wire diameter was held by a capillary (made of ceramic; thermal conductivity: 4.2 W/m·K) and by applying a 120 mA current to a tip portion of the wire for 650 μsec, a 70 μm diameter FAB (FAB diameter/wire diameter=1.84; FAB volume/(wire diameter) 3 =3.27) was prepared. The above operation was performed on each of 200 copper bonding wires.

Comparative Examples 2 to 8

FABs were prepared on each of three types of copper bonding wires of different wire diameters (wire diameter=38 μm, 30 μm, and 25 μm) using the same capillary as that of Comparative Example 1.

Evaluation

As demonstrated by Examples 1 to 9, it was confirmed that, in the cases of using the capillaries with thermal conductivities of 17.7 W/m·K and 430 W/m·K to intentionally form FABs with the magnitudes (FAB diameter/wire diameter) of the diameter with respect to the wire diameter of the wire being 1.5 to 2.2 times, FABs of any one of the true sphere mode, off-center mode, and club mode can be formed reliably without occurrence of the failure mode in which the copper bonding wire is unmelted. It was thus confirmed that FABs of comparatively small diameter with a volume of 1.8 to 5.6 times the cube of the wire diameter of the bonding wire (FAB volume/(wire diameter) 3 =1.8 to 5.6) can be formed with stability.

Fourth Preferred Embodiment FIG. 27 to FIG. 36

By disclosure of a fourth preferred embodiment, a fourth issue concerning a fourth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Fourth Background Art

Semiconductor devices are normally distributed in a state where a semiconductor chip is sealed (packaged) together with bonding wires by a resin. Inside the package, electrode pads of the semiconductor chip are electrically connected by the bonding wires to electrode leads that are partially exposed from the resin package. Thus, by connecting the electrode leads as external terminals to wirings on a mounting board, electrical connection of the semiconductor chip and the mounting board is achieved.

Next, the capillary moves to a position directly above an electrode pad and thereafter descends so that the FAB contacts the electrode pad. In this process, a load and ultrasonic waves of fixed levels are applied to the FAB by the capillary. The FAB is thereby deformed in accordance with a shape of the tip of the capillary and a first bond portion is formed.

(2) Fourth Issue

However, copper is harder and more difficult to deform than gold and thus when a first bond is formed using a copper wire under the same bonding conditions (load, magnitude of ultrasonic waves, etc.) as those for a gold wire, the copper wire and an electrode pad may not be bonded satisfactorily and bond failure may occur.

›Example 1 · 2 of 5

Thus, a fourth object of the present invention related to the fourth preferred embodiment is to provide a wire bonding method capable of suppressing bond failures of copper bonding wires with respect to electrode pads and a semiconductor device prepared using the method.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 287 is a schematic bottom view of a semiconductor device according to the fourth preferred embodiment of the present invention. FIG. 288 is a schematic sectional view of the semiconductor device according to the fourth preferred embodiment of the present invention. FIG. 289 is an enlarged view of a portion surrounded by a broken-line circle in FIG. 288 .

The semiconductor device 1 D is a semiconductor device to which a QFN (quad flat non-leaded) configuration is applied. The semiconductor device 1 D includes a semiconductor chip 2 D, a die pad 3 D supporting the semiconductor chip 2 D, a plurality of electrode leads 4 D disposed at a periphery of the semiconductor chip 2 D, bonding wires 5 D electrically connecting the semiconductor chip 2 D and the electrode leads 4 D, and a resin package 6 D sealing the above components.

The semiconductor chip 2 D has a quadrilateral shape in plan view and has, for example, a multilayer wiring structure arranged by laminating a plurality of wiring layers via interlayer insulating films. Also, the semiconductor chip 2 D has a thickness, for example, of 220 to 240 μm (preferably, approximately 230 μm). As shown in FIG. 29 , a top surface 21 D (surface at one side in a thickness direction) of the semiconductor chip 2 D is covered by a top surface protective film 7 D.

A plurality of pad openings 8 D for exposing an uppermost wiring layer of the multilayer wiring structure are formed in the top surface protective film 7 D.

Each pad opening 8 D has a quadrilateral shape in plan view and the same number thereof are provided at each edge of the semiconductor chip 2 D. The respective pad openings 8 D are disposed at equal intervals along the respective sides of the semiconductor chip 2 D. A portion of the wiring layer is exposed as an electrode pad 9 D of the semiconductor chip 2 D from each pad opening 8 D.

The uppermost wiring layer exposed as the electrode pads 9 D is made, for example, of a metal material that contains Al (aluminum) and is specifically made of a metal material having Al as a main component (for example, an Al—Cu alloy, etc.).

Meanwhile, a rear surface metal 10 D that contains, for example, Au, Ni, Ag, etc., is formed on a rear surface 22 D (surface at the other side in the thickness direction) of the semiconductor chip 2 D.

The die pad 3 D is made, for example, of a metal thin plate (for example, Cu or 42 alloy (an alloy containing Fe-42% Ni) and has a larger quadrilateral shape (for example, approximately 2.7 mm square in plan view) than the semiconductor chip 2 D in plan view. Also, the die pad 3 D has a thickness of 190 to 210 μm (preferably, approximately 200 μm). A pad plating layer 11 D that contains Ag, etc., is formed on a top surface 31 D (surface at one side in the thickness direction) of the die pad 3 D.

The semiconductor chip 2 D and the die pad 3 D are bonded to each other in a state where the rear surface 22 D of the semiconductor chip 2 D and the top surface 31 D of the die pad 3 D face each other as bond surfaces with a bonding material 12 D interposed between the rear surface 22 D and the top surface 31 D. The semiconductor chip 2 D is thereby supported by the die pad 3 D in an orientation where the top surface 21 D faces upward.

The bonding material 12 D is made, for example, of solder paste or other conductive paste. As the bonding material 12 D, an insulating paste, such as a silver paste, an alumina paste, may be applied and in this case, the rear surface metal 10 D and/or the pad plating layer 11 D may be omitted. Also, in the state where the semiconductor chip 2 D and the die pad 3 D are bonded, a thickness of the bonding material 12 D is, for example, 10 to 20 μm.

A rear surface 32 D (surface at the other side in the thickness direction) of the die pad 3 D is exposed from the resin package 6 D. A solder plating layer 13 D made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed other-side surface.

The electrode leads 4 D are made of the same metal thin plate (containing, for example, Cu or 42 alloy (Fe-42% Ni, etc.) as the die pad 3 D. The electrode leads 4 D are disposed at the periphery of the semiconductor chip 2 D with the same number thereof being disposed at both sides in respective directions orthogonal to respective side surfaces of the die pad 3 D. The electrode leads 4 D that face each side surface of the die pad 3 D are disposed at equal intervals in a direction parallel to the facing side surface. A length of each electrode lead 4 D in the direction of facing the die pad 3 D is, for example, 390 to 410 μm (preferably, approximately 400 μm). A lead plating layer 14 D that contains Ag, etc., is formed on a top surface 41 D (surface at one side in the thickness direction) of each electrode lead 4 D.

Meanwhile, a rear surface 42 D (surface at the other side in the thickness direction) of each electrode lead 4 D is exposed from the resin package 6 D. A solder plating layer 15 D made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed rear surface 42 D.

Each bonding wire 5 D is made of copper (for example, a high-purity copper of no less than 99.9999% (6N) purity or no less than 99.99% (4N) purity that may contain a minute amount of impurity). Each bonding wire 5 D includes a linearly-extending, cylindrical main body portion 51 D and includes a pad bond portion 52 D and a lead bond portion 53 D formed at respective ends of the main body portion 51 D and respectively bonded to an electrode pad 9 D and an electrode lead 4 D.

The main body portion 51 D is curved parabolically upward from the one end at the electrode pad 9 D side toward an outer side of the semiconductor chip 2 D and made impingent at an acute angle at the other end on the top surface 41 D of the electrode lead 4 D.

›Example 1 · 3 of 5

The pad bond portion 52 D is smaller than the electrode pad 9 D in plan view. The pad bond portion 52 D has a humped shape in sectional view that integrally includes a substantially disk-shaped base portion 54 D, which, at its other side in the thickness direction, contacts a top surface of the electrode pad 9 D, and a substantially umbrella-shaped projecting portion 55 D projecting from the one side of the base portion 54 D and having a tip connected to the one end of the main body portion 51 D.

A side surface 56 D of the base portion 54 D is curved so as to bulge outward in a radial direction beyond an outer periphery of a surface at the other side (rear surface 57 D of the base portion 54 D) that has a substantially circular shape in plan view and contacts the electrode pad 9 D. Thus, in plan view, the base portion 54 D overlaps with a substantially circular bond region 91 D, which is a portion of the electrode pad 9 D that contacts the rear surface 57 D and is bonded to the base portion 54 D, and a peripheral region 92 D of substantially annular shape that surrounds the bond region 91 D and does not contact the base portion 54 D.

In the peripheral region 92 D of the electrode pad 9 D, a protruding portion 93 D is formed by a material of the electrode pad 9 D being pressingly spread and raised by an FAB 24 D (to be described below) during bonding of the bonding wire 5 D. The protruding portion 93 D is not lifted above a top surface 94 D of the electrode pad 9 D and contacts the top surface 94 D.

The lead bond portion 53 D has a wedge-like shape in sectional view that is relatively thick at the one end side close to the main body portion 51 D and becomes relatively thinner toward the other end side away from the main body portion 51 D.

As in the first preferred embodiment, in the semiconductor device 1 D, the entire top surface 21 D and side surfaces 28 D of the semiconductor chip 2 D, the entire top surface 31 D and side surfaces of the die pad 3 D, the entire top surfaces 41 D and side surfaces inside the resin package 6 D of the electrode leads 4 D, and the entire bonding wires 5 D are covered by an integral water-impermeable insulating film 25 D.

As the resin package 6 D, a known material, such as an epoxy resin, may be applied. The resin package 6 D makes up an outer shape of the semiconductor device 1 D and is formed to a substantially rectangular parallelepiped shape. In terms of size, the resin package 6 D has a planar size, for example, of approximately 4 mm square and a thickness, for example, of 0.80 to 0.90 mm and preferably, approximately 0.85 mm.

FIG. 30A to FIG. 30E are schematic sectional views for describing a method for manufacturing the semiconductor device shown in FIG. 27 and FIG. 28 in order of process.

To manufacture the semiconductor device 1 D, for example, first, a lead frame 20 D that includes a plurality of units each integrally having a die pad 3 D and electrode leads 4 D is prepared. In FIG. 30A to FIG. 30E , an entire view of the lead frame 20 D is abbreviated and the die pad 3 D and electrode leads 4 D of just a single unit necessary for mounting a single semiconductor chip 2 D are shown.

Next, a metal plating of Ag, etc., is applied to a top surface of the lead frame 20 D by a plating method. The pad plating layer 11 D and the lead plating layer 14 D are thereby formed at the same time.

Next, as shown in FIG. 30A , the semiconductor chips 2 D are die bonded via the bonding material 12 D to all die pads 3 D on the lead frame 20 D.

Next, bonding of each bonding wire 5 D is performed by a wire bonder (not shown) that includes a capillary 23 D.

The capillary 23 D included in the wire bonder has a substantially cylindrical shape with a straight hole 17 D, through which the bonding wire 5 D is inserted, formed at a center, and during wire bonding, the bonding wire 5 D is fed out from a tip of the straight hole 17 D.

A face portion 18 D, which is substantially perpendicular to a longitudinal direction of the straight hole 17 D and, in plan view, has an annular shape concentric to the straight hole 17 D, and a chamfer portion 19 D, which is recessed in the longitudinal direction of the straight hole 17 D from the face portion 18 D, are formed at a tip portion of the capillary 23 D.

A side surface 16 D of the chamfer portion 19 D is formed to a conical surface connecting an inner circumferential circle of the face portion 18 D and a circumferential surface of the straight hole 17 D. The side surface 16 D is thus rectilinear in sectional view and in the present preferred embodiment, an apex angle (chamfer angle) thereof is set, for example, to 90°.

In the wire bonding process, first, a spherical FAB 24 D (free air ball) is formed on a tip portion (one end portion) of the bonding wire 5 D held by the capillary 23 D by application of a current to the tip portion. The applied current I is set to a larger value the larger a wire diameter (diameter) D w of the main body portion 51 D, and for example, I=40 mA when D w =25 μm, I=60 mA when D w =30 μm, and I=120 mA when D w =38 μm. A current application time is set to an appropriate length according to an intended diameter D f of the FAB 24 D.

Next, as shown in FIG. 30B (i), the capillary 23 D moves to a position directly above an electrode pad 9 D and thereafter descends so that the FAB 24 D contacts the electrode pad 9 D. In this process, a load (open arrows in FIG. 30B (i)) and ultrasonic waves (zigzag lines in FIG. 30B (i)) are applied from the capillary 23 D to the FAB 24 D.

In the application of the load and the ultrasonic waves, in a first time period (for example, of 1 to 5 msec and preferably, approximately 3 msec) at an initial stage of pressing after the FAB 24 D has descended and contacted the electrode pad 9 D, a relatively large load is applied, and thereafter during a second time period (for example, of 2 to 20 msec) longer than the first time period, a relatively small load is applied as shown in FIG. 30B (ii).

The relatively large load W is set in accordance with the wire diameter D w of the main body portion 51 C and an intended diameter D b of the base portion 54 D and, for example, W=80 g when D w =25 μm and D b =58 μm, W=130 g when D w =30 μm and D b =74 μm, and W=240 g when D w =38 μm and D b =104 μm.

›Example 1 · 4 of 5

Also, in the initial stage of pressing of the FAB 24 D, the ultrasonic waves are, for example, not applied at the same time as the relatively large load but is applied immediately after (for example, 1 msec after) the application of the relatively large load and is thereafter applied continuously at a fixed magnitude until the end of application of the load (for example, 2 to 20 msec). The applied ultrasonic waves, in terms of output values of the apparatus are, for example, of 120 kHz and 50 to 120 mA. The ultrasonic waves may be applied in a period until the initial stage of pressing of the FAB 24 D (for example, during descending of the FAB 24 D).

The applications of the load and the ultrasonic waves are ended at the same time. Or, the application of the ultrasonic waves ends first and the application of the load ends thereafter. A portion of the FAB 24 D is thereby made to spread below the face portion 18 D to form the base portion 54 D while the remaining portion remains inside the chamfer portion 19 D while being pushed inside the straight hole 17 D to form the projecting portion 55 D. Consequently, the one end portion of the bonding wire 5 D is bonded as the pad bond portion 52 D to the electrode pad 9 D, and a first bond is formed.

After the first bond has been formed, the capillary 23 D rises to a fixed height and moves to a position directly above an electrode lead 4 D. Then, as shown in FIG. 30C , the capillary 23 D descends again and the bonding wire 5 D contacts the electrode lead 4 D. In this process, a load (open arrows in FIG. 30C ) and ultrasonic waves (zigzag lines in FIG. 30C ) are applied from the capillary 23 to the bonding wire 5 D so that the bonding wire 5 D deforms according to the shape of the face portion 18 D of the capillary 23 D and is bonded to the electrode lead 4 D (forming of a stitch bond 26 D and a tail bond 27 D).

The capillary 23 D then rises and in a state where a tail of a fixed length is secured from a tip of the capillary 23 D, the bonding wire 5 D is broken from a position of the tail bond 27 D. The other end of the bonding wire 5 D that has been stitch bonded thus remains as the lead bond portion 53 D on the electrode lead 4 D and a second bond is thereby formed.

Thereafter, as shown in FIG. 30D , the same processes as those of FIG. 30A to 30D are performed so that the respective electrode pads 9 D of all semiconductor chips 2 D and the electrode leads 4 D corresponding to the respective electrode pads 9 D are connected by the bonding wires 5 D.

After all of the wire bonding ends, the water-impermeable insulating film 25 D is formed by the same method as that of FIG. 4D . After the forming of the water-impermeable insulating film 25 D, the lead frame 20 D is set in a forming mold and all semiconductor chips 2 D are sealed in a batch together with the lead frame 20 D by the resin package 6 D as shown in FIG. 30E . Solder plating layers 13 D and 15 D are then formed on the rear surfaces 32 D of the die pads 3 D and the rear surfaces 42 D of the electrode leads 4 D that are exposed from the resin package 6 D. Lastly, a dicing saw is used to cut the lead frame 20 A together with the resin package 6 D to sizes of the respective semiconductor devices 1 D and the individual semiconductor devices 1 D one of which is shown in FIG. 28 are thereby obtained.

As described above, with the present method, after the FAB 24 D has been formed on the tip portion of the bonding wire 5 D made of copper, the FAB 24 D is bonded as the pad bond portion 52 D to the electrode pad 9 D by ultrasonically vibrating the FAB 24 D while pressing it against the electrode pad 9 D.

During bonding of the FAB 24 D, a fixed load and ultrasonic waves are not applied for the same time period to the FAB 24 D, but as shown in FIG. 30B (ii), in the first time period (initial stage of pressing) after the FAB 24 D has descended and contacted the electrode pad 9 D, the relatively large load is applied, and the ultrasonic waves are applied while applying the relatively large load during the first time period. Thus, during the first time period, the FAB 24 D can be deformed effectively to the shape of the pad bond portion 52 D.

Then, in a latter stage of pressing after the first time period, the relatively small load is applied for the second time period that is longer than the first time period. Thus, during the second time period, the bonding wire 5 D can be bonded with excellent strength to the electrode pad 9 D by the ultrasonic waves applied at the same time as the relatively small load.

In bonding the copper wire to the electrode pad, if the load and the ultrasonic waves are made greater than those in conditions for a gold wire and the large load and ultrasonic waves are applied at the fixed magnitudes for the same time period, so-called excessive splash, with which the material of the pad that is pressingly spread by the metal ball is lifted above the top surface of the electrode pad and protrudes greatly outward, may occur. For example, to describe using the reference symbols in FIG. 27 to FIG. 29 , an excessive splash 95 D that is lifted outward from the peripheral region 92 D of the electrode pad 9 D may occur as shown in FIG. 31 .

However, with the above-described method, the load applied to the FAB 24 D after the initial stage of pressing is made relatively small and the pressingly spreading of the electrode pad 9 D due to the FAB 24 D to which the ultrasonic waves are applied can be suppressed. Consequently, the occurrence of excessive splash at the electrode pad 9 D can be suppressed.

Also, the relatively large load is applied to the electrode pad 9 D only in the period of the initial stage and thus application of a large load to a portion directly below the electrode pad 9 D can be suppressed. Occurrence of crack in the semiconductor chip 2 D can thus be suppressed.

Thus, with the semiconductor device 1 D obtained by the above-described method, the protruding portion 93 D, with which the material of the electrode pad 9 D is pressingly spread by the FAB 24 D and protrudes upward during the bonding of the bonding wire 5 D, can be held at simply rising from the top surface 94 D of the electrode pad 9 D and be prevented from being lifted from the top surface 94 D.

›Example 1 · 5 of 5

Especially, in a semiconductor device, such as the semiconductor device 1 D, in which the electrode pad 9 D is made of a metal material that contains aluminum, excessive splash occurs readily in a case where a copper wire is used. However, even with such a semiconductor device 1 D, excessive splash can be prevented effectively by using the wire bonding method of the present preferred embodiment.

Although the fourth preferred embodiment of the present invention has been described above, the fourth preferred embodiment may also be modified as follows.

Also, although with the above-described preferred embodiment, a mode in which the bonding wires 5 D are covered by the water-impermeable insulating film 25 D was described as an example, the water-impermeable insulating film 25 D may be omitted as shown in FIG. 32 as long as at least the fourth object for resolving the fourth issue is achieved.

Next, experiments related to the fourth preferred embodiment were performed. The present invention is not restricted by the following examples.

›Example 1 · 1 of 9

A copper bonding wire of 25 μm wire diameter was held by a capillary and an FAB of 60 μm diameter was prepared at a tip portion thereof.

The capillary holding the FAB was then moved to a position directly above an electrode pad made of aluminum and then lowered at once onto the electrode pad to make the FAB collide against the electrode pad. In this process, a load of 130 g was applied instantaneously to the FAB and maintained at this magnitude for 3 msec as shown in FIG. 33 . Thereafter, the load applied to the FAB was decreased instantaneously to 30 g and maintained at this magnitude for 9 msec. Meanwhile, ultrasonic waves were not applied until the FAB contacted the electrode pad, were applied at 90 mA instantaneously 1 msec after the application of the load of 130 g, and were maintained at this magnitude for 11 msec. The applications of the load and the ultrasonic waves were ended at the same time.

The FAB was bonded as a pad bond portion to the electrode pad by the above operation.

Comparative Example 1

A copper bonding wire of 25 μm wire diameter was held by a capillary and an FAB of 60 μm diameter was prepared at a tip portion thereof.

The capillary holding the FAB was then moved to a position directly above an electrode pad made of aluminum and then lowered at once onto the electrode pad to make the FAB collide against the electrode pad. In this process, a load of 60 g was applied instantaneously to the FAB and maintained at this magnitude for 6 msec as shown in FIG. 34 . Meanwhile, ultrasonic waves were applied at 130 mA instantaneously at the same time as the application of the load of 60 g and were maintained at this magnitude for 6 msec. The applications of the load and the ultrasonic waves were ended at the same time.

The FAB was bonded as a pad bond portion to the electrode pad by the above operation.

Electron beam scanning of the pad bond portion formed in each of Example 1 and Comparative Example 1 was then performed using a scanning electron microscope (SEM) and SEM images were obtained by image processing of information detected thereby. By observation of the SEM images obtained, whether or not excessive splash occurred during bonding of each pad bond portion was confirmed. An SEM image of Example 1 is shown in FIG. 35 and an SEM image of Comparative Example 1 is shown in FIG. 36 .

As shown in FIG. 36 , with Comparative Example 1 in which the load and ultrasonic waves of fixed levels were applied for the same time period in bonding the pad bond portion, it was confirmed that excessive splash occurred in which the electrode pad was pressingly spread by the FAB and material of the pad was lifted from a top surface of the electrode pad and protruded greatly outward.

On the other hand, as shown in FIG. 35 , with Example 1 in which the relatively large load of 130 g was applied instantaneously at the initial stage of pressing of the FAB and thereafter the relatively small load of 30 g was applied instantaneously, it was confirmed that the portion of the pad material that was pressingly spread by the FAB remained at being simply raised and was not lifted from the top surface of the electrode pad.

Fifth Preferred Embodiment FIG. 37 to FIG. 43

By disclosure of a fifth preferred embodiment, a fifth issue concerning a fifth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Fifth Background Art

Semiconductor devices are normally distributed in a state where a semiconductor chip is sealed (packaged) together with bonding wires by a resin. Inside the package, electrode pads of the semiconductor chip are electrically connected by the bonding wires to electrode leads that are partially exposed from the resin package. By connecting the electrode leads as external terminals to wirings on a mounting board, electrical connection of the semiconductor chip and the mounting board is achieved.

A first bond, which is a bond of a bonding wire and an electrode pad, is formed, for example, by first applying energy to a tip portion of a bonding wire held by a capillary of a wire bonder and melting the wire material by heat of a resulting spark. The molten wire material becomes an FAB (free air ball) due to surface tension.

(2) Fifth Issue

However, normally, Al wiring covered by an interlayer insulating film is disposed directly below the electrode pad so as to face the electrode pad. Also, a Ti/TiN layer (barrier layer) that is harder than the Al wiring is interposed between the interlayer insulating film and the electrode pad.

With such a structure, when a load is applied to the FAB put in contact with the electrode pad and the barrier layer is thereby pressed toward the Al wiring side, stress tends to concentrate at the relatively hard barrier layer due to the difference in hardness between the barrier layer and the wiring. Thus, depending on the magnitude of the stress concentrating at the barrier layer, a crack may occur in the barrier layer and cause a fault, such as short-circuiting between wirings.

Thus, a fifth object of the present invention related to the fifth preferred embodiment is to provide a semiconductor device with which, during bonding of a bonding wire made of copper and an electrode pad, occurrence of crack in a barrier layer directly below the electrode pad can be prevented.

(3) Disclosure of a Specific Preferred Embodiment

›Example 1 · 2 of 9

FIG. 37 is a schematic sectional view of a semiconductor device according to the fifth preferred embodiment of the present invention.

The semiconductor device 1 E is a semiconductor device to which a QFN (quad flat non-leaded) configuration is applied. The semiconductor device 1 E includes a semiconductor chip 2 E, a die pad 3 E supporting the semiconductor chip 2 E, a plurality of electrode leads 4 E disposed at a periphery of the semiconductor chip 2 E, bonding wires 5 E electrically connecting the semiconductor chip 2 E and the electrode leads 4 E, and a resin package 6 E sealing the above components.

The semiconductor chip 2 E has a quadrilateral shape in plan view and has a multilayer wiring structure arranged by laminating a plurality of wirings via interlayer insulating films. The multilayer wiring structure of the semiconductor chip 2 E shall be described in detail later with reference to FIG. 38 and FIG. 39 . The semiconductor chip 2 E has a thickness, for example, of 220 to 240 μm (preferably, approximately 230 μm). A top surface 21 E (surface at one side in a thickness direction) of the semiconductor chip 2 E is covered by a top surface protective film 7 E (see FIG. 38 ).

At the top surface 21 E of the semiconductor chip 2 E, portions of a wiring (a third wiring 28 E to be described below) of the multilayer wiring structure are exposed as electrode pads 9 E from pad openings 8 E to be described below.

Meanwhile, a rear surface metal 10 E that contains, for example, Au, Ni, Ag, etc., is formed on a rear surface 22 E (surface at the other side in the thickness direction) of the semiconductor chip 2 E.

The die pad 3 E is made, for example, of a metal thin plate (for example, Cu or 42 alloy (an alloy containing Fe-42% Ni) and has a larger quadrilateral shape (for example, approximately 2.7 mm square in plan view) than the semiconductor chip 2 E in plan view. Also, the die pad 3 E has a thickness of 190 to 210 μm (preferably, approximately 200 μm). A pad plating layer 11 E that contains Ag, etc., is formed on a top surface 31 E (surface at one side in the thickness direction) of the die pad 3 E.

The semiconductor chip 2 E and the die pad 3 E are bonded to each other in a state where the rear surface 22 E of the semiconductor chip 2 E and the top surface 31 E of the die pad 3 E face each other as bond surfaces with a bonding material 12 E interposed between the rear surface 22 E and the top surface 31 E. The semiconductor chip 2 E is thereby supported by the die pad 3 E in an orientation where the top surface 21 E faces upward.

The bonding material 12 E is made, for example, of solder paste or other conductive paste. As the bonding material 12 E, an insulating paste, such as a silver paste, an alumina paste, may be applied and in this case, the rear surface metal 10 E and/or the pad plating layer 11 E may be omitted. Also, in the state where the semiconductor chip 2 E and the die pad 3 E are bonded, a thickness of the bonding material 12 E is, for example, 10 to 20 μm.

A rear surface 32 E (surface at the other side in the thickness direction) of the die pad 3 E is exposed from the resin package 6 E. A solder plating layer 13 E made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed other-side surface.

The electrode leads 4 E are made, for example, of the same metal thin plate (containing, for example, Cu or 42 alloy (Fe-42% Ni, etc.) as the die pad 3 E. The electrode leads 4 E are disposed at the periphery of the semiconductor chip 2 E at both sides in respective directions orthogonal to respective side surfaces of the die pad 3 E. The electrode leads 4 E that face each side surface of the die pad 3 E are disposed at equal intervals in a direction parallel to the facing side surface. A length of each electrode lead 4 E in the direction of facing the die pad 3 E is, for example, 240 to 260 μm (preferably, approximately 250 μm). A lead plating layer 14 E that contains Ag, etc., is formed on atop surface 41 E (surface at one side in the thickness direction) of each electrode lead 4 E.

Meanwhile, a rear surface 42 E (surface at the other side in the thickness direction) of each electrode lead 4 E is exposed from the resin package 6 E. A solder plating layer 15 E made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed rear surface 42 E.

Each bonding wire 5 E is made of copper (for example, a high-purity copper of no less than 99.9999% (6N) purity or no less than 99.99% (4N) purity that may contain a minute amount of impurity). Each bonding wire 5 E includes a linearly-extending, cylindrical main body portion 51 E and includes a pad bond portion 52 E and a lead bond portion 53 E formed at respective ends of the main body portion 51 E and respectively bonded to an electrode pad 9 E and an electrode lead 4 E.

The main body portion 51 E is curved parabolically upward from the one end at the electrode pad 9 E side toward an outer side of the semiconductor chip 2 E and made impingent at an acute angle at the other end on the top surface 41 E of the electrode lead 4 E.

The lead bond portion 53 E has a wedge-like shape in sectional view that is relatively thick at the one end side close to the main body portion 51 E and becomes relatively thinner toward the other end side away from the main body portion 51 E.

As in the first preferred embodiment, in the semiconductor device 1 E, the entire top surface 21 E and side surfaces 37 E of the semiconductor chip 2 E, the entire top surface 31 E and side surfaces of the die pad 3 E, the entire top surfaces 41 E and side surfaces inside the resin package 6 E of the electrode leads 4 E, and the entire bonding wires 5 E are covered by an integral water-impermeable insulating film 36 E.

As the resin package 6 E, a known material, such as an epoxy resin, may be applied. The resin package 6 E makes up an outer shape of the semiconductor device 1 E and is formed to a substantially rectangular parallelepiped shape. In terms of size, the resin package 6 E has a planar size, for example, of approximately 4 mm square and a thickness, for example, of 0.60 to 0.70 mm and preferably, approximately 0.65 mm.

›Example 1 · 3 of 9

FIG. 38 is a sectional view of principal portions of the semiconductor chip and is an enlarged view of a portion surrounded by a broken-line circle in FIG. 37 . FIG. 39 is a plan view of an electrode pad shown in FIG. 38 .

The semiconductor chip 2 E includes a semiconductor substrate 16 E, first to third interlayer insulating films 17 E to 19 E laminated successively on the semiconductor substrate 16 E, first to third barrier layers 23 E to 25 E formed on respective top surfaces of the first to third interlayer insulating films 17 E to 19 E, and the top surface protective film 7 E covering the top surface 21 E of the semiconductor chip 2 E.

The semiconductor substrate 16 E is made, for example, of silicon.

The first to third interlayer insulating films 17 E to 19 E are made, for example, of silicon oxide. A first wiring 26 E is formed via the first barrier layer 23 E on the first interlayer insulating film 17 E. Also, a second wiring 27 E is formed via the second barrier layer 24 E on the second interlayer insulating film 18 E. Also, the third wiring 28 E is formed via the third barrier layer 25 E on the third interlayer insulating film 19 E.

The first to third wirings 26 E to 28 E are made of a metal material that is softer than the material of the first to third barrier layers 23 E to 25 E, and are made specifically of a metal material that contains Al (aluminum), and made specifically of a metal material having Al as a main component (for example, an Al—Cu alloy, etc.).

By being covered by the top surface protective film 7 E, the third wiring 28 E is formed between the uppermost interlayer insulating film (third interlayer insulating film 19 E) and the top surface protective film 7 E. The third wiring 28 E has a quadrilateral shape (for example, a quadrilateral shape of 120 μm×120 μm) in plan view. Also, the third wiring 28 E has a thickness, for example, of no less than 500 Å and preferably 7000 to 28000 Å.

The pad openings 8 E for exposing the third wiring 28 E as the electrode pads 9 E are formed in the top surface protective film 7 E that covers the third wiring 28 E.

By being covered by the third interlayer insulating film 19 E, the second wiring 27 E is formed between the second interlayer insulating film 18 E and the third interlayer insulating film 19 E. The second wiring 27 E is formed in a predetermined pattern. For example, it is formed in a pattern that does not overlap with the electrode pads 9 E in plan view. The second wiring 27 E has a thickness, for example, of 3000 to 9000 Å.

By being covered by the second interlayer insulating film 18 E, the first wiring 26 E is formed between the first interlayer insulating film 17 E and the second interlayer insulating film 18 E. The first wiring 26 E is formed in a predetermined pattern. For example, directly below each electrode pad 9 E, the first wiring 26 E has a plurality of rectilinear portions 29 E that extend parallel to each other and connecting portions 30 E that connect ends at one side of adjacent rectilinear portions 29 E and alternately connect ends at the other side of adjacent rectilinear portions 29 E and is thereby formed in a meandering pattern that is bent in a substantially sinusoidal form. A single electrode pad 9 E (third wiring 28 E) thus faces a plurality of rectilinear portions 29 E and sandwiched portions 20 E of the second interlayer insulating film 18 E that are sandwiched between the rectilinear portions 29 E.

Mutual intervals between adjacent rectilinear portions 29 E (pitch W of the rectilinear portion 29 E) are, for example, all equal and are specifically 2 to 10 μm. Also, the first wiring 26 E has a thickness, for example, of 3000 to 9000 Å.

The patterns of the first to third wirings 26 E to 28 E may be changed as suited in accordance with design rules of the semiconductor chip 2 E and are not limited to the above-described patterns.

Each of the first to third barrier layers 23 E to 25 E is made, for example, titanium (TiN), titanium nitride (TiN), tungsten nitride (TiW), or a laminated structure of these, etc. Each of the first to third barrier layers 23 E to 25 E has a thickness that is less than the thickness of each of the first to third wirings 26 E to 28 E and is, for example, 500 to 2000 Å.

In plan view, the pad bond portion 52 E of the bonding wire 5 E that is bonded to the electrode pad 9 E is smaller than the electrode pad 9 E. The pad bond portion 52 E has a humped shape in sectional view that integrally includes a disk-shaped base portion 54 E, which, at its one side in the thickness direction, contacts a top surface of the electrode pad 9 E, and a bell-shaped projecting portion 55 E projecting from the other side of the base portion 54 E and having a tip connected to the one end of the main body portion 51 E.

With the semiconductor device 1 E, an area of the first wiring 26 E (area of slanted line portion in FIG. 39 ) that overlaps a bond region 33 E of the bonding wire 5 E and the electrode pad 9 E in plan view is no more than 26.8% and preferably 0 to 25% of an area S of the bond region 33 E.

The bond region 33 E is a region of circular shape in plan view in which the base portion 54 E of the pad bond portion 52 E contacts the top surface of the electrode pad 9 E, and its area S can be determined by a formula: S=n(D/2) 2 using a diameter D of the base portion 54 E.

As described above, with the semiconductor device 1 E, the area of the first wiring 26 E overlapping the bond region 33 E in plan view (overlap area of the first wiring 26 E) is no more than 26.8% of the area of the bond region 33 E, and thus an area by which each of the second and third barrier layers 24 E and 25 E directly below the electrode pad 9 E faces the first wiring 26 E is comparatively small. Thus, for example, even if the second and third barrier layers 24 E and 25 E are pressed toward the first wiring 26 E side during bonding of the bonding wire 5 E and the electrode pad 9 E, deformations of the first wiring 26 E and the second and third interlayer insulating films 18 E and 19 E due to the pressing are unlikely to occur, and concentration of stress at the second and third barrier layers 24 E and 25 E due to such deformations can be prevented. Consequently, occurrence of crack in the second and third barrier layers 24 E and 25 E can be prevented and the semiconductor device 1 E can thus be improved in reliability.

›Example 1 · 4 of 9

When, for example, the overlap area of the first wiring 26 E is 0% of the area of the bond region 33 E, the semiconductor 1 E can be made 0% in defect rate (without any cracks forming whatsoever) regardless of the thickness of the electrode pad 9 E (thickness of the third wiring 28 E).

Also, the first wiring 26 E includes the plurality of rectilinear portions 29 E that extend parallel with respect to each other and these are disposed at equal intervals. In such an arrangement, the overlap area of the plurality of rectilinear portions 29 E (first wiring 26 E) is a total of the overlap area of each rectilinear portion 29 E and this total is no more than 26.8% of the area of the bond region 33 E. The overlap areas of the respective rectilinear portions 29 E are thus all less than 26.8% of the area of the bond region 33 E.

A single electrode pad 9 E (third wiring 28 E) faces a plurality of rectilinear portions 29 E and sandwiched portions 20 E of the second interlayer insulating film 18 E that are sandwiched between the rectilinear portions 29 E. The plurality of rectilinear portions 29 E, the overlap areas of each of which is less than 26.8% of the area of the bond region 33 E, thus face the bond region 33 E of the electrode pad 9 E while being dispersed in stripe form. Thus, when the second and third barrier layers 24 E and 25 E are pressed toward the first wiring 26 E side, deformation amounts of the first wiring 26 E and the second and third interlayer insulating films 18 E and 19 E due to the pressing can be suppressed to small amounts. Stress concentration at specific locations in the second and third barrier layers 24 E and 25 E can consequently be suppressed. Occurrence of crack in the second and third barrier layers 24 E and 25 E can thus be prevented further.

Although the fifth preferred embodiment of the present invention has been described above, the fifth preferred embodiment may also be modified as follows.

For example, the patterns of the first and second wirings 26 E and 27 E below the electrode pad 9 E may be changed as suited as long as the area of the wiring overlapping with the bond region 33 E is no more than 26.8% of the area S of the bond region 33 E.

For example, as shown in a first modification example in FIG. 40 , the first wiring 26 E may be formed to a pattern that does not overlap with the electrode pad 9 E in plan view, and the second wiring 27 E may have a plurality of rectilinear portions 34 E that extend parallel to each other and connecting portions 35 E that connect ends at one side of adjacent rectilinear portions 34 E and alternately connect ends at the other side of adjacent rectilinear portions 34 E and be formed in a meandering pattern that is bent in substantially sinusoidal form.

Or, for example, as shown in a second modification example in FIG. 41 , both the first and second wirings 26 E and 27 E may be formed in meandering patterns.

Also, vias that are electrically connected to the first to third wirings 26 E to 28 E may be formed in the first to third interlayer insulating films 17 E to 19 E.

Also, although with the preferred embodiment described above, the semiconductor device 1 E with the three-layer wiring structure was taken up as an example, the wiring structure of the semiconductor device may be a two-layer structure, a four-layer structure, a five-layer structure, or a structure with no less than five layers.

Also, for example, although a QFN type semiconductor device was taken up in the above description of the preferred embodiment, the present invention may also be applied to semiconductor devices of other package types, for example, the SON (small outline non-leaded), QFP (quad flat package), SOP (small outline package), etc.

Also, although with the above-described preferred embodiment, a mode in which the bonding wires 5 E are covered by the water-impermeable insulating film 36 E was described as an example, the water-impermeable insulating film 36 E may be omitted as shown in FIG. 42 as long as at least the fifth object for resolving the fifth issue is achieved.

Next, experiments related to the fifth preferred embodiment were performed. The present invention is not restricted by the following examples.

Examples 1 to 3 and Comparative Examples 1 to 6

With the respective examples and comparative examples, multilayer wiring structures shown in FIG. 43 were formed on semiconductor substrates. In FIG. 43 , portions indicated as “first,” “second,” and “third” are interlayer insulating films, made of silicon oxide, that were successively laminated on each semiconductor substrate. Also, a Ti/TiN barrier layer was interposed between respective interlayer insulating films that are vertically adjacent to each other. Also, the electrode pads and the wirings were formed using aluminum. For all of the respective examples and comparative examples, three types, with which the electrode pad is 28000 Å, 15000 Å, and 5000 Å, respectively, were prepared.

The following tests were performed on each of the multilayer wiring structures prepared as described above.

First, a copper bonding wire of 25 μm wire diameter was held by a capillary and an FAB of 60 μm diameter was prepared at a tip portion thereof.

The capillary holding the FAB was then moved to a position directly above an electrode pad and then lowered at once onto the electrode pad to make the FAB collide against the electrode pad. In this process, a load of 130 g and ultrasonic waves (120 khz) of 210 mA were applied to the FAB. The bonding wire was thereby bonded to the electrode pad.

The test was performed on 120 electrode pads for each of the examples and comparative examples and the number of electrode pads (number of defective items) with which a crack occurred in the barrier layer during bonding was counted. The results are shown in Table 1. In Table 1, “Wiring/bond region (%)” is the proportion of the area of the wiring that overlaps the bond region with respect to the area of the bond region of the bonding wire and the electrode pad in plan view.

›Example 1 · 5 of 9

Sixth Preferred Embodiment FIG. 44 to FIG. 55

By disclosure of a sixth preferred embodiment, a sixth issue concerning a sixth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Sixth Background Art

A semiconductor device includes a semiconductor chip with a plurality of electrode pads formed thereon and a plurality of electrode leads disposed so as to surround the semiconductor chip. Each electrode pad and each electrode lead are electrically connected in a one-to-one manner by a single bonding wire. The semiconductor chip, the electrode leads, and the bonding wires are sealed (packaged) by a resin with a portion of each electrode lead being exposed.

Although conventionally, gold wires are mainly used as the bonding wires, recently, the use of copper wires, which are cheaper than gold wires, is being examined for reducing the use of high-priced gold.

To connect electrode pads and electrode leads by bonding wires, for example, a number or a positional pattern of the electrode pads on a semiconductor chip is first recognized by a wire bonder.

Next, by applying energy to a tip portion of a wire held by a capillary, the tip portion of the wire is melted by heat of a resulting spark and an FAB (free air ball) is formed.

The FAB is then made to contact an electrode pad, and by application of a load and ultrasonic waves to the FAB by the capillary, the FAB is deformed in accordance with a shape of the tip of the capillary and a first bond portion is formed.

After the forming of the first bond, the capillary moves from the electrode pad to an electrode lead and a wire loop spanning across the pad and the lead is thereby formed.

The bonding wire is then made to contact the electrode lead, and by application of a load and ultrasonic waves to the bonding wire by the capillary, the bonding wire deforms in accordance with a shape of a face of the capillary and is bonded to the electrode lead (formation of stitch bond and tail bond).

Thereafter, the capillary rises from the electrode lead, and with a tail of fixed length being secured from the tip of the capillary, the bonding wire is cut from the position of the tail bond. The other end of the bonding wire that was stitch bonded is thereby left on the electrode lead and a second bond portion is formed. By the above steps, connection of a single electrode pad and a single electrode lead is achieved.

All pad-lead combinations are connected by a cycle, made up of the above-described step of forming the FAB, step of forming of the first bond portion, and step of forming the second bond portion (step of cutting the wire), being repeated in that order continuously.

(2) Sixth Issue

While the cycles are being executed continuously (from a second cycle onwards), a size of the FAB (FAB diameter) of the copper wire is substantially fixed in all cycles because the heat received from the spark and a heater is stable in each cycle.

On the other hand, in a first cycle immediately after recognition of the electrode pads, an FAB of smaller diameter than the FABs of the second cycle onward is formed because the copper wire is cooled due to influence of forming gas (gas for suppressing oxidation of copper), etc., during recognition of the electrode pads and also because an ambient temperature environment of the copper wire is not stable due to the wire being separated from the heater.

Thus, a fault occurs in which the diameter and thickness of just the first bond portion of the bonding wire bonded in the first cycle are smaller than the diameter and thickness of the first bond portions of the other bonding wires.

For this problem, preparation of the FAB of the first cycle, not immediately after the recognition of the electrode pads, but in advance before the recognition of the electrode pads while the ambient temperature environment of the copper wire is stable may be considered. For example, in a case where wire bonding is performed continuously for a plurality of semiconductor chips, the ambient temperature environment of the copper wire is comparatively stable immediately after an end of a final cycle of the immediately prior wire bonding.

However, with the method of preparing the FAB in advance, the forming of the FAB to the bonding of the FAB are not executed as one series of steps and there is a time gap until the bonding of the FAB is performed. The FAB that has been prepared in advance may thus oxidize and a connection defect may thus occur between the electrode pad and the bonding wire.

Thus, a sixth object of the present invention related to the sixth preferred embodiment is to provide a semiconductor device that is low in cost due to use of bonding wires made of copper and enables connection defects of bonding wires with respect to a plurality of bonding objects to be suppressed while suppressing variation in sizes of metal balls, and a method for manufacturing the semiconductor device.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 44 is a schematic sectional view of a semiconductor device according to the sixth preferred embodiment of the present invention. FIG. 45 is an exploded plan view of the semiconductor device of FIG. 44 with a resin package removed.

The semiconductor device 1 F is a semiconductor device to which an SON (small outline non-leaded) configuration is applied. The semiconductor device 1 F includes a semiconductor chip 2 F, a die pad 3 F supporting the semiconductor chip 2 F, a plurality of electrode leads 4 F disposed at a periphery of the semiconductor chip 2 F, bonding wires 5 F electrically connecting the semiconductor chip 2 F and the electrode leads 4 F, and a resin package 6 F sealing the above components.

The semiconductor chip 2 F has a quadrilateral shape in plan view and has a multilayer wiring structure arranged by laminating a plurality of wiring layers via interlayer insulating films. The semiconductor chip 2 F has a thickness, for example, of 220 to 240 μm (preferably, approximately 230 μm). A top surface 21 F (surface at one side in a thickness direction) of the semiconductor chip 2 F is covered by a top surface protective film 7 F. For the sake of convenience, the present preferred embodiment shall be described below with two arbitrary mutually orthogonal directions among the plurality of directions along the top surface 21 F of the semiconductor chip 2 F being deemed to be an X direction and a Y direction, and further a direction orthogonal to both these directions (that is, a direction perpendicular to the top surface 21 F) being deemed to be a Z direction.

›Example 1 · 6 of 9

A plurality of pad openings 8 F for exposing the uppermost wiring layer of the multilayer wiring structure are formed in the top surface protective film 7 F.

Each pad opening 8 F has a quadrilateral shape in plan view and the same number thereof are provided at each of a pair of mutually opposing edge portions of the semiconductor chip 2 F. The respective pad openings 8 F are disposed at equal intervals along the edge portions. A portion of the wiring layer is exposed as an electrode pad 9 F (bonding object) of the semiconductor chip 2 F from each pad opening 8 F.

Meanwhile, a rear surface metal 10 F that contains, for example, Au, Ni, Ag, etc., is formed on a rear surface 22 F (surface at the other side in the thickness direction) of the semiconductor chip 2 F.

The die pad 3 F is made, for example, of a metal thin plate (for example, Cu or 42 alloy (an alloy containing Fe-42% Ni) and has a larger quadrilateral shape (for example, approximately 2.7 mm square in plan view) than the semiconductor chip 2 F in plan view. Also, the die pad 3 F has a thickness, for example, of 190 to 210 μm (preferably, approximately 200 μm). A pad plating layer 11 F that contains Ag, etc., is formed on a top surface 31 F (surface at one side in the thickness direction) of the die pad 3 F.

The semiconductor chip 2 F and the die pad 3 F are bonded to each other in a state where the rear surface 22 F of the semiconductor chip 2 F and the top surface 31 F of the die pad 3 F face each other as bond surfaces with a bonding material 12 F interposed between the rear surface 22 F and the top surface 31 F. The semiconductor chip 2 F is thereby supported by the die pad 3 F in an orientation where the top surface 21 F faces upward.

The bonding material 12 F is made, for example, of solder paste or other conductive paste. As the bonding material 12 F, an insulating paste, such as a silver paste, an alumina paste, may be applied and in this case, the rear surface metal 10 F and/or the pad plating layer 11 F may be omitted. Also, in the state where the semiconductor chip 2 F and the die pad 3 F are bonded, a thickness of the bonding material 12 F is, for example, 10 to 20 μm.

A rear surface 32 F (surface at the other side in the thickness direction) of the die pad 3 F is exposed from the resin package 6 F. A solder plating layer 13 F made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed other-side surface.

The electrode leads 4 F are made of the same metal thin plate (containing, for example, Cu or 42 alloy (Fe-42% Ni, etc.) as the die pad 3 F. The electrode leads 4 F are disposed at the periphery of the semiconductor chip 2 F with the same number thereof being disposed at both sides in directions orthogonal to two side surfaces, among the four side surfaces of the die pad 3 F, at which the electrode pads 9 F are disposed. The electrode leads 4 F that face each side surface of the die pad 3 F are disposed at equal intervals in a direction parallel to the facing side surface. A length of each electrode lead 4 F in the direction of facing the die pad 3 F is, for example, 450 to 550 μm (preferably, approximately 500 μm). A lead plating layer 14 F that contains Ag, etc., is formed on a top surface 41 F (surface at one side in the thickness direction) of each electrode lead 4 F.

Meanwhile, a rear surface 42 F (surface at the other side in the thickness direction) of each electrode lead 4 F is exposed from the resin package 6 F. A solder plating layer 15 F made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed rear surface 42 F.

Each bonding wire 5 F is made of copper (for example, a high-purity copper of no less than 99.9999% (6N) purity or no less than 99.99% (4N) purity that may contain a minute amount of impurity). The same number of bonding wires 5 F as the electrode pads 9 F and electrode leads 4 F are provided and the bonding wires 5 F electrically connect the respective electrode pads 9 F and the respective electrode leads 4 F in a one-to-one manner.

Each bonding wire 5 F includes a linearly-extending, cylindrical main body portion 51 F and includes a pad bond portion 52 F and a lead bond portion 53 F formed at respective ends of the main body portion 51 F and respectively bonded to an electrode pad 9 F and an electrode lead 4 F.

The main body portion 51 F is curved parabolically upward from the one end at the electrode pad 9 F side toward an outer side of the semiconductor chip 2 F and made impingent at an acute angle at the other end on the top surface 41 F of the electrode lead 4 F.

The lead bond portion 53 F has a wedge-like shape in sectional view that is relatively thick at the one end side close to the main body portion 51 F and becomes relatively thinner toward the other end side away from the main body portion 51 F.

As in the first preferred embodiment, in the semiconductor device 1 F, the entire top surface 21 F and side surfaces 28 F of the semiconductor chip 2 F, the entire top surface 31 F and side surfaces of the die pad 3 F, the entire top surfaces 41 F and side surfaces inside the resin package 6 F of the electrode leads 4 F, and the entire bonding wires 5 F are covered by an integral water-impermeable insulating film 25 F.

As the resin package 6 F, a known material, such as an epoxy resin, may be applied. The resin package 6 F makes up an outer shape of the semiconductor device 1 F and is formed to a substantially rectangular parallelepiped shape. In terms of size, the resin package 6 F has a planar size, for example, of approximately 4 mm square and a thickness, for example, of 0.80 to 0.90 mm and preferably, approximately 0.85 mm.

FIG. 46 is a sectional view of principal portions of the semiconductor chip and is an enlarged view of a portion surrounded by a broken-line circle in FIG. 44 . FIG. 47 is an enlarged plan view of an electrode pad shown in FIG. 46 .

›Example 1 · 7 of 9

The pad bond portion 52 F is smaller than the electrode pad 9 F in plan view. The pad bond portion 52 F has a humped shape in sectional view that integrally includes a substantially disk-shaped base portion 54 F, which, at its one side in the thickness direction, contacts a top surface of the electrode pad 9 F, and a bell-shaped projecting portion 55 F projecting from the other side of the base portion 54 F and having a tip connected to the one end of the main body portion 51 F.

A side surface 56 F of the base portion 54 F is curved so as to bulge outward in a radial direction beyond an outer periphery of a surface at the other side (rear surface 57 F of the base portion 54 F) that has a substantially circular shape in plan view and contacts the electrode pad 9 F. A diameter of a most outwardly bulging portion of the base portion 54 F (diameter of the base portion 54 F) as the bond portion of the bonding wire 5 F with respect to the electrode pad 9 F is substantially the same in each of the X direction and the Y direction, and a diameter D x in the X direction and a diameter D y in the Y direction are, for example, both 70 to 80 μm. Also, the base portion 54 F has a thickness T z (height in the Z direction) of, for example, 15 to 20 μm.

With the semiconductor device 1 F, when V is a volume of each base portion 54 F, a variation of the volumes V of the respective base portions 54 F with respect to an average AVE of the volumes V of all base portions 54 F is within ±15% and preferably, within ±10%. Specifically, a proportion of an absolute value of a difference between the average AVE and the volume V with respect to the average AVE (that is, (average AVE-volume V)/average AVE×100(%)) is no more than 15(%).

The volume V of the base portion 54 F is, for example, expressed by a product of the diameters D x and D y of the base portion 54 F and the thickness T z of the base portion 54 F (that is, V=D x ×D y ×T z ). The volume V of the base portion 54 F may be determined by conceptually deeming the base portion 54 F to be a cylinder with a diameter D x or D y and a height T z and determining the volume as an approximate value based on the volume of the cylinder. That is, the volume may also be expressed as V=π(D x /2) 2 ·T z .

Also, a diameter D w of the main body portion 51 F (diameter of the bonding wire 5 F) is, for example, 28 to 38 μm.

FIG. 48A to FIG. 48E are schematic sectional views for describing a method for manufacturing the semiconductor device shown in FIG. 44 in order of process.

To manufacture the semiconductor device 1 F, for example, first, a lead frame 20 F that includes a plurality of units each integrally having a die pad 3 F and electrode leads 4 F is prepared. In FIG. 48A to FIG. 48E , an entire view of the lead frame 20 F is abbreviated and the die pad 3 F and electrode leads 4 F of just a single unit necessary for mounting a single semiconductor chip 2 F are shown.

Next, a metal plating of Ag, etc., is applied to a top surface of the lead frame 20 F by a plating method. The pad plating layer 11 F and the lead plating layer 14 F are thereby formed at the same time.

Next, as shown in FIG. 48A , the semiconductor chips 2 F are die bonded via the bonding material 12 F to all die pads 3 F on the lead frame 20 F.

Next, wire bonding by a wire bonder (not shown) that includes a capillary 23 F is performed successively one chip at a time on the plurality of semiconductor chips 2 F.

The capillary 23 F included in the wire bonder has a substantially cylindrical shape with a straight hole 17 F, through which the bonding wire 5 F is inserted, formed at a center, and during wire bonding, the bonding wire 5 F is fed out from a tip of the straight hole 17 F.

A face portion 18 F, which is substantially perpendicular to a longitudinal direction of the straight hole 17 F and, in plan view, has an annular shape concentric to the straight hole 17 F in plan view, and a chamfer portion 19 F, which is recessed in the longitudinal direction of the straight hole 17 F from the face portion 18 F, are formed at a tip portion of the capillary 23 F.

A side surface 16 F of the chamfer portion 19 F is formed to a conical surface connecting an inner circumferential circle of the face portion 18 F and a circumferential surface of the straight hole 17 F. The side surface 16 F is thus rectilinear in sectional view and in the present preferred embodiment, an apex angle (chamfer angle) thereof is set, for example, to 90°.

In the wire bonding of each semiconductor chip 2 F, a step (FAB forming step) of forming an FAB (free air ball) on a tip portion (one end portion) of the bonding wire 5 F, a step (first bonding step) of bonding the FAB to an electrode pad 9 F, a step (second bonding step) of bonding the bonding wire 5 F extending from the FAB to an electrode lead 4 F, and a step (cutting step) of severing the bonding wire 5 F from the capillary 23 F are repeated in that order.

First, the number or positional pattern of the electrode pads 9 F on the semiconductor chip 2 F, on which wire bonding is performed first, is recognized by the wire bonder (recognition step).

The FAB step of the first cycle is then started. Specifically, a spherical FAB 24 F is formed on a tip portion (one end portion) of the bonding wire 5 F held by the capillary 23 F by application of a current to the tip portion. The applied current I 1 is set in accordance with an intended diameter Df of the FAB 24 F. For example, I 1 =40 mA when Dw=25 μm, I 1 =60 mA when Dw=30 μm, and I 1 =120 mA when Dw=38 μm. An application time t 1 of the current I 1 is set in accordance with the intended diameter Df of the FAB 24 F. For example, t 1 =720 μsec when Dw=25 μm, t 1 =830 μsec when Dw=30 μm, and t 1 =960 μsec when Dw=38 μm.

In the FAB step of the first cycle, an energy expressed by the applied current I 1 multiplied by the application time t 1 (I 1 ×t 1 ) is applied to the bonding wire 5 F as a first energy E 1 for forming the FAB 24 F.

A flow rate of a forming gas supplied to the wire bonder (not shown) is set to an appropriate magnitude in accordance with the intended diameter Df of the FAB 24 F. The forming gas is a gas for suppressing oxidation of the bonding wire 5 F and contains, for example, N 2 or H 2 .

›Example 1 · 8 of 9

Next, as shown in FIG. 48B , the capillary 23 F moves to a position directly above an electrode pad 9 F and thereafter descends so that the FAB 24 F contacts the electrode pad 9 F. In this process, a load (open arrows in FIG. 48B ) and ultrasonic waves (zigzag lines in FIG. 48B ) are applied from the capillary 23 F to the FAB 24 F. The applied load and the applied ultrasonic waves are set to appropriate magnitudes in accordance with the wire diameter Dw of the main body portion 51 F and the intended diameters (Dx and Dy) and thickness (Tz) of the base portion 54 F.

A portion of the FAB 24 F is thereby made to spread below the face portion 18 F to form the base portion 54 F while the remaining portion of the FAB 24 F remains inside the chamfer portion 19 F while being pushed inside the straight hole 17 F to form the projecting portion 55 F. The one end portion of the bonding wire 5 F is thereby bonded as the pad bond portion 52 F to the electrode pad 9 F, and a first bond is formed.

After the first bond has been formed, the capillary 23 F rises to a fixed height and moves to a position directly above an electrode lead 4 F. Then, as shown in FIG. 48C , the capillary 23 F descends again and the bonding wire 5 F contacts the electrode lead 4 F. In this process, a load (open arrows in FIG. 48C ) and ultrasonic waves (zigzag lines in FIG. 48C ) are applied from the capillary 23 F to the bonding wire 5 F so that the bonding wire 5 F deforms according to the shape of the face portion 18 F of the capillary 23 F and is bonded to the electrode lead 4 F (forming of a stitch bond 26 F and a tail bond 27 F), thereby forming the lead bond portion 53 F as a second bond.

Then, as shown in FIG. 48D , the capillary 23 F rises and in a state where a tail of a fixed length is secured from a tip of the capillary 23 F, the bonding wire 5 F is broken from a position of the tail bond 27 F.

Thereafter, as shown in FIG. 48E , the FAB forming step ( FIG. 48A ), the first bonding step ( FIG. 48B ), the second bonding step ( FIG. 48C ), and the cutting step ( FIG. 48D ) of the second cycle onward are repeated in that order, and all of the electrode pads 9 F and electrode leads 4 F of the first semiconductor chip 2 F are connected by the bonding wires 5 F.

In the FAB forming step of the second cycle onward, a second energy E 2 for forming the FAB 24 F is set, for example, so that the first energy E 1 of first cycle is 105 to 115% and preferably, 108 to 112% of the second energy E 2 . For example, when Dw=25 μm, the applied current I 2 =40 mA is applied to the tip portion (one end portion) of the bonding wire 5 F for the application time t 2 =792 μsec, and when Dw=30 μm, I 2 =60 mA and the application time t 2 =913 μsec, and when Dw=38 μm, I 2 =120 mA and the application time t 2 =1056 μsec.

Also, the flow rate of the forming gas supplied to the wire bonder (not shown) is set, for example, to the same magnitude as the flow rate of the forming gas in the first cycle.

After the end of the wire bonding of the first semiconductor chip 2 F, the number or positional pattern of the electrode pads 9 F of a second semiconductor chip 2 F is recognized by the wire bonder (recognition step). Then, in the same manner as in the case of the first semiconductor chip 2 F, the FAB forming step ( FIG. 48A ), the first bonding step ( FIG. 48B ), the second bonding step ( FIG. 48C ), and the cutting step ( FIG. 48D ) are repeated a plurality of times (a plurality of cycles) in that order, and all of the electrode pads 9 F and electrode leads 4 F of the second semiconductor chip 2 F are connected by the bonding wires 5 F.

Thereafter, the recognition step and the wire bonding of repeating the FAB forming step, the first bonding step, the second bonding step, and the cutting step a plurality of times are performed on each of the remaining plurality of semiconductor chips 2 F (the third semiconductor chip 2 F and onward).

After the wire bonding of all semiconductor chips 2 F on the lead frame 20 F ends, the water-impermeable insulating film 25 F is formed by the same method as that of FIG. 4D . After the forming of the water-impermeable insulating film 25 F, the lead frame 20 F is set in a forming mold and all semiconductor chips 2 F are sealed in a batch together with the lead frame 20 F by the resin package 6 F. Solder plating layers 13 F and 15 F are then formed on the rear surfaces 32 F of the die pads 3 F and the rear surfaces 42 F of the electrode leads 4 F that are exposed from the resin package 6 F. Lastly, a dicing saw is used to cut the lead frame 20 A together with the resin package 6 F to sizes of the respective semiconductor devices 1 F and the individual semiconductor devices 1 F one of which is shown in FIG. 44 are thereby obtained.

As described above, with the above method, in the wire bonding of each semiconductor chip 2 F, the first energy E 1 (applied current I 1 ×application time t 1 ) applied to the bonding wire 5 F in the FAB forming step of the first cycle is set higher than the second energy E 2 (applied current I 2 ×application time t 2 ) applied to the bonding wire 5 F in the FAB forming step of the second cycle onward. For example, t 1 is made longer than t 2 with I 2 and I 2 being set to the same value. The ambient temperature environment of the bonding wire 5 F in the first cycle can thus be stabilized. Consequently, a comparatively large FAB 24 F can be formed in the first cycle.

Thus, for example, by adjusting the output of the wire bonder so that the application time t 1 is 105 to 115% of the application time t 2 , the diameter Df of the FAB 24 F in the first cycle can be made substantially the same as the diameter Df of the FAB 24 F in the second cycle onward. Consequently, variation of the diameters Df of the FABs 24 F can be suppressed throughout all cycles.

Also, for each semiconductor chip 2 F, after the recognition step has ended, wire bonding is performed by the FAB forming step, the first bonding step, the second bonding step, and the cutting step being executed as one series of steps that is repeated a plurality of times. The FAB 24 prepared in each cycle is immediately bonded to the electrode pad 9 F without being left to stand for a while. Oxidation of the FAB 24 F can thus be suppressed and connection defects of the bonding wires with respect to electrode pads 9 F can be suppressed.

›Example 1 · 9 of 9

Although the sixth preferred embodiment of the present invention has been described above, the sixth preferred embodiment may also be modified as follows.

For example, although with the preferred embodiment described above, only cases where the bonding object of the FAB 24 F is an electrode pad 9 F were taken up, the bonding object of the FAB 24 F may, for example, be an electrode lead 4 F or may be a stud bump formed on an electrode pad 9 F or an electrode lead 4 F, etc.

Also, for example, although an SON type semiconductor device was taken up in the above description of the preferred embodiment, the present invention may also be applied to semiconductor devices of other package types, for example, the QFN (quad flat non-leaded), QFP (quad flat package), SOP (small outline package), etc.

Also, although with the above-described preferred embodiment, a mode in which the bonding wires 5 F are covered by the water-impermeable insulating film 25 F was described as an example, the water-impermeable insulating film 25 F may be omitted as shown in FIG. 49 as long as at least the sixth object for resolving the sixth issue is achieved.

Next, experiments related to the sixth preferred embodiment were performed. The present invention is not restricted by the following examples.

›Example 1

A semiconductor chip having 144 electrode pads was die bonded onto a die pad of a lead frame having 144 electrode leads.

Next, a copper bonding wire of 30 μm wire diameter was held by a capillary and while supplying a forming gas at 0.3 L/min, a current I 1 of 60 mA was applied for 913 μsec (t 1 ) to a tip portion of the wire to prepare an FAB (FAB forming step).

The capillary holding the FAB was then moved to a position directly above an electrode pad and then lowered at once onto the electrode pad to make the FAB collide against the electrode pad. In this process, a load and ultrasonic waves were applied to the FAB. The bonding wire was thereby bonded as a pad bond portion to the electrode pad (first bonding step).

Next, the capillary was raised and after moving it to a position directly above an electrode lead, the capillary was lowered at once onto the electrode lead to make the bonding wire collide against the electrode pad. In this process, a load and ultrasonic waves were applied to the bonding wire. A stitch bond and a tail bond were thereby formed on the bonding wire and the bonding wire was bonded to the electrode lead (second bonding step).

Next, the capillary was raised, and in a state where a tail of a fixed length was secured from the tip of the capillary, the bonding wire was cut from the position of the tail bond (cutting step).

Thereafter, the cycle made up of the FAB forming step, the first bonding step, the second bonding step, and the cutting step was repeated 14 times continuously to connect 15 electrode pads and 15 electrode leads in a one-to-one manner by the bonding wires.

In the FAB forming step of each of the second to 15th cycles, a current I 2 of 60 mA was applied for 830 μsec (t 2 ) to the tip portion of the bonding wire to prepare the FAB. That is, in the first cycle, by setting the application time t 1 to 110% of the application time t 2 of the second cycle (913(t 1 )=830(t 2 )×1.1), a first energy E 1 of 1.1 times a second energy E 2 of the second cycle was applied to the bonding wire to form the FAB.

Diameters Dx and Dy (diameters in the X and Y directions) of the base portion and thickness Tz (height in the Z direction) of the base portion of each pad bond portion thus formed were measured. The measured values of Dx, Dy, and Tz are shown in Table 2 below. Also, the variation of the volumes V of the respective base portions with respect to the average of the volumes V of all base portions was computed based on Dx, Dy, and Tz. The results are shown in Table 2.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 50A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 50B . The X direction and the Y direction are two arbitrary mutually orthogonal directions among the plurality of directions along a top surface of the semiconductor chip, and the Z direction is a direction orthogonal to both the X and Y directions (that is, a direction perpendicular to the top surface of the semiconductor chip). Also, in FIGS. 50A and 50B , a plot of ♦ indicates the diameter or the thickness of the base portion formed in the first cycle, and a plot of ⋄ indicates the diameters or the thicknesses of the base portions formed in the second cycle onward.

The average values of Dx, Dy, and Tz of the base portions of the second cycle onward were calculated as: diameter Dx: 73.9 μm; diameter Dy: 75.2 μm; and thickness Tz: 14.9 μm. Meanwhile, Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 74.1 μm; diameter Dy: 75.1 μm; and thickness Tz: 15.0 μm.

Comparative Example 1

Besides making the applied current I 2 in the FAB forming step of the first cycle the same as the applied current I 2 in the FAB forming step of the second cycle onward, the same semiconductor chip and lead frame as those of Example 1 were used to perform wire bonding by the same procedure and under the same conditions as Example 1.

Diameters Dx and Dy (diameters in the X and Y directions) of the base portion and thickness Tz (height in the Z direction) of the base portion of each pad bond portion thus formed were measured. The measured values of Dx, Dy, and Tz are shown in Table 5 below. Also, the variation of the volumes V of the respective base portions with respect to the average of the volumes V of all base portions was computed based on Dx, Dy, and Tz. The results are shown in Table 5.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 50A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 50B . In FIGS. 50A and 50B , a plot of ▪ indicates the diameter or the thickness of the base portion formed in the first cycle, and the diameters or the thicknesses of the base portions formed in the second cycle onward are the same as those of Example 1.

Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 71.0 μm; diameter Dy: 71.5 μm; and thickness Tz: 13.5 μm; and confirmed to be smaller than the diameters and thickness of the base portion of the first cycle in Example 1.

›Example 2

Besides using a lead frame having 48 electrode leads and a semiconductor chip having 48 electrode pads, wire bonding by the same procedure and under the same conditions as Example 1 was performed.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 51A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 51B . In FIGS. 51A and 51B , a plot of ♦ indicates the diameter or the thickness of the base portion formed in the first cycle, and a plot of ⋄ indicates the diameters or the thicknesses of the base portions formed in the second cycle onward.

The average values of Dx, Dy, and Tz of the base portions of the second cycle onward were calculated to be: diameter Dx: 75.0 μm; diameter Dy: 76.8 μm; and thickness Tz: 16.7 μm. Meanwhile, Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 75.2 μm; diameter Dy: 77.1 μm; and thickness Tz: 16.9 μm.

Comparative Example 2

Besides making the application time t 1 in the FAB forming step of the first cycle the same as the application time t 2 in the FAB forming step of the second cycle onward, the same semiconductor chip and lead frame as those of Example 2 were used to perform wire bonding by the same procedure and under the same conditions as Example 2.

Diameters Dx and Dy (diameters in the X and Y directions) of the base portion and thickness Tz (height in the Z direction) of the base portion of each pad bond portion thus formed were measured. The measured values of Dx, Dy, and Tz are shown in Table 5 below. Also, the variation of the volumes V of the respective base portions with respect to the average of the volumes V of all base portions was computed based on Dx, Dy, and Tz. The results are shown in Table 5.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 51A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 51B . In FIGS. 51A and 51B , a plot of ▪ indicates the diameter or the thickness of the base portion formed in the first cycle, and the diameters or the thicknesses of the base portions formed in the second cycle are the same as those of Example 2.

Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 72.0 μm; diameter Dy: 72.5 μm; and thickness Tz: 14.0 μm; and confirmed to be smaller than the diameters and thickness of the base portion of the first cycle in Example 2.

›Example 3

Besides using a lead frame having 44 electrode leads and a semiconductor chip having 44 electrode pads, wire bonding by the same procedure and under the same conditions as Example 1 was performed.

Diameters Dx and Dy (diameters in the X and Y directions) of the base portion and thickness Tz (height in the Z direction) of the base portion of each pad bond portion thus formed were measured. The measured values of Dx, Dy, and Tz are shown in Table 3 below. Also, the variation of the volumes V of the respective base portions with respect to the average of the volumes V of all base portions was computed based on Dx, Dy, and Tz. The results are shown in Table 3.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 52A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 52B . In FIGS. 52A and 52B , a plot of ♦ indicates the diameter or the thickness of the base portion formed in the first cycle, and a plot of ⋄ indicates the diameters or the thicknesses of the base portions formed in the second cycle onward.

The average values of Dx, Dy, and Tz of the base portions of the second cycle onward were calculated to be: diameter Dx: 74.7 μm; diameter Dy: 77.3 μm; and thickness Tz: 16.5 μm. Meanwhile, Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 74.9 μm; diameter Dy: 77.6 μm; and thickness Tz: 16.7 μm.

Comparative Example 3

Besides making the application time t 1 in the FAB forming step of the first cycle the same as the application time t 2 in the FAB forming step of the second cycle onward, the same semiconductor chip and lead frame as those of Example 3 were used to perform wire bonding by the same procedure and under the same conditions as Example 3.

Diameters Dx and Dy (diameters in the X and Y directions) of the base portion and thickness Tz (height in the Z direction) of the base portion of each pad bond portion thus formed were measured. The measured values of Dx, Dy, and Tz are shown in Table 6 below. Also, the variation of the volumes V of the respective base portions with respect to the average of the volumes V of all base portions was computed based on Dx, Dy, and Tz. The results are shown in Table 6.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 52A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 52B . In FIGS. 52A and 52B , a plot of ▪ indicates the diameter or the thickness of the base portion formed in the first cycle, and the diameters or the thicknesses of the base portions formed in the second cycle are the same as those of Example 3.

Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 71.0 μm; diameter Dy: 73.0 μm; and thickness Tz: 13.5 μm; and confirmed to be smaller than the diameters and thickness of the base portion of the first cycle in Example 3.

›Example 4

Besides using a lead frame having 20 electrode leads and a semiconductor chip having 20 electrode pads, wire bonding by the same procedure and under the same conditions as Example 1 was performed.

Diameters Dx and Dy (diameters in the X and Y directions) of the base portion and thickness Tz (height in the Z direction) of the base portion of each pad bond portion thus formed were measured. The measured values of Dx, Dy, and Tz are shown in Table 3 below. Also, the variation of the volumes V of the respective base portions with respect to the average of the volumes V of all base portions was computed based on Dx, Dy, and Tz. The results are shown in Table 3.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 53A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 53B . In FIGS. 53A and 53B , a plot of ♦ indicates the diameter or the thickness of the base portion formed in the first cycle, and a plot of ⋄ indicates the diameters or the thicknesses of the base portions formed in the second cycle onward.

The average values of Dx, Dy, and Tz of the base portions of the second cycle onward were calculated to be: diameter Dx: 75.2 μm; diameter Dy: 77.7 μm; and thickness Tz: 17.6 μm. Meanwhile, Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 75.3 μm; diameter Dy: 77.9 μm; and thickness Tz: 17.8 μm.

Comparative Example 4

Besides making the application time t 1 in the FAB forming step of the first cycle the same as the application time t 2 in the FAB forming step of the second cycle onward, the same semiconductor chip and lead frame as those of Example 4 were used to perform wire bonding by the same procedure and under the same conditions as Example 4.

Diameters Dx and Dy (diameters in the X and Y directions) of the base portion and thickness Tz (height in the Z direction) of the base portion of each pad bond portion thus formed were measured. The measured values of Dx, Dy, and Tz are shown in Table 6 below. Also, the variation of the volumes V of the respective base portions with respect to the average of the volumes V of all base portions was computed based on Dx, Dy, and Tz. The results are shown in Table 6.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 53A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 53B . In FIGS. 53A and 53B , a plot of ▪ indicates the diameter or the thickness of the base portion formed in the first cycle, and the diameters or the thicknesses of the base portions formed in the second cycle onward are the same as those of Example 4.

Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 73.5 μm; diameter Dy: 75.0 μm; and thickness Tz: 14.5 μm; and confirmed to be smaller than the diameters and thickness of the base portion of the first cycle in Example 4.

›Example 5

Besides using a lead frame having 20 electrode leads and a semiconductor chip (chip differing from that of Example 4) having 20 electrode pads, wire bonding by the same procedure and under the same conditions as Example 1 was performed.

Diameters Dx and Dy (diameters in the X and Y directions) of the base portion and thickness Tz (height in the Z direction) of the base portion of each pad bond portion thus formed were measured. The measured values of Dx, Dy, and Tz are shown in Table 4 below. Also, the variation of the volumes V of the respective base portions with respect to the average of the volumes V of all base portions was computed based on Dx, Dy, and Tz. The results are shown in Table 4.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 54A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 54B . In FIGS. 54A and 54B , a plot of ♦ indicates the diameter or the thickness of the base portion formed in the first cycle, and a plot of ⋄ indicates the diameters or the thicknesses of the base portions formed in the second cycle onward.

The average values of Dx, Dy, and Tz of the base portions of the second cycle onward were calculated to be: diameter Dx: 76.1 μm; diameter Dy: 77.8 μm; and thickness Tz: 17.7 μm. Meanwhile, Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 76.4 μm; diameter Dy: 78.0 μm; and thickness Tz: 17.9 μm.

Comparative Example 5

Besides making the application time t 1 in the FAB forming step of the first cycle the same as the application time t 2 in the FAB forming step of the second cycle onward, the same semiconductor chip and lead frame as those of Example 5 were used to perform wire bonding by the same procedure and under the same conditions as Example 5.

Diameters Dx and Dy (diameters in the X and Y directions) of the base portion and thickness Tz (height in the Z direction) of the base portion of each pad bond portion thus formed were measured. The measured values of Dx, Dy, and Tz are shown in Table 7 below. Also, the variation of the volumes of the respective base portions with respect to the average of the volumes of all base portions was computed based on Dx, Dy, and Tz. The results are shown in Table 7.

Also, a distribution of the diameters Dx and Dy of the base portions is shown in FIG. 54A . Also, a distribution of the thicknesses Tz of the base portions is shown in FIG. 54B . In FIGS. 54A and 54B , a plot of ▪ indicates the diameter or the thickness of the base portion formed in the first cycle, and the diameters or the thicknesses of the base portions formed in the second cycle are the same as those of Example 5.

Dx, Dy, and Tz of the base portion of the first cycle were: diameter Dx: 72.0 μm; diameter Dy: 74.5 μm; and thickness Tz: 15.5 μm; and confirmed to be smaller than the diameters and thickness of the base portion of the first cycle in Example 5.

Examples 6 to 9 and Comparative Example 6

Besides using a lead frame having 44 electrode leads and a semiconductor chip having 44 electrode pads, wire bonding by the same procedure and under the same conditions as Example 1 was performed. The relationships between the applied energy E 1 in the FAB forming step of the first cycle and the applied energy E 2 in the FAB forming steps of the second cycle onward in Examples 6 to 9 and Comparative Example 6 were as follows.

›Example 6

E 1 =E 2 ×104(%)/100

›Example 7

E 1 =E 2 ×108(%)/100

›Example 8

E 1 =E 2 ×112(%)/100

›Example 9

E 1 =E 2 ×116(%)/100

Comparative Example 6

E 1 =E 2 ×100(%)/100

The diameters in the X and Y directions of the base portion formed in the first cycle and the diameters in the X and Y directions of the base portions formed in the second cycle onward in Examples 6 to 9 and Comparative Example 6 are shown in FIG. 55 . In regard to the diameters of the base portions of the second cycle onward, average values are indicated.

The diameters of the base portions of Examples 6 to 9 and Comparative Example 6 were as follows.

Example 6 X-direction Dx: 73.0 μm Y-direction Dy: 75.0 μm

Example 7 X-direction Dx: 75.8 μm Y-direction Dy: 76.8 μm

Example 8 X-direction Dx: 75.4 μm Y-direction Dy: 78.0 μm

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 1 of 27

Comparative Example 6 X-direction Dx: 72.2 μm Y-direction Dy: 73.4 μm

Second cycle onward (in common to Examples 6 to 9 and Comparative Example 6)

X-direction Dx: 75.2 μm Y-direction Dy: 77.1 μm

The above shows that in Examples 6 to 9, the diameters of both X and Y directions of the base portion in the first cycle were within ranges of ±1 μm of the diameters of the base portions of the second cycle onward. On the other hand, in Comparative Example 6, the diameters of both X and Y directions of the base portion in the first cycle were no less than ±1.5 μm of the diameters of the base portions of the second cycle onward.

Seventh Preferred Embodiment FIG. 56 to FIG. 68

By disclosure of a seventh preferred embodiment, a seventh issue concerning a seventh background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Seventh Background Art

In a typical semiconductor device, a semiconductor chip is disposed on a die pad and the semiconductor chip is connected by wires made of Au (gold) to leads disposed at a periphery of the die pad. Specifically, pads made of Al (aluminum) are disposed on a top surface of the semiconductor chip. The wires made of Au are installed so as to form arch-shaped loops between top surfaces of the pads and top surfaces of the leads.

In installing each wire (in wire bonding), an FAB (free air ball) is formed on a tip of a wire held by a capillary of a wire bonder and the FAB is put in contact with a top surface of a pad. In this process, the FAB is pressed toward the pad at a predetermined load by the capillary and a predetermined drive current is supplied to an ultrasonic transducer provided in the capillary to apply ultrasonic vibration to the FAB. Consequently, the FAB is pressed while being rubbed against the top surface of the pad and bonding of the wire to the top surface of the pad is achieved. Thereafter, the capillary is moved toward a lead. The wire is then pressed against a top surface of the lead and the wire is broken while an ultrasonic vibration is applied to the wire. The wire is thereby installed between the top surface of the pad and the top surface of the lead.

Capillaries include standard type capillaries, in which an outer diameter (T dimension) of a face that is a surface that faces a pad during bonding of an FAB and the pad is relatively large and an angle formed by a side surface, connected to the face, and a central axis of the capillary is relatively large, and bottleneck type capillaries, in which an outer shape of the face is relatively small and the angle formed by a side surface, connected to the face, and the central axis of the capillary is relatively small.

(2) Seventh Issue

Recently, price competition of semiconductor devices in the market is becoming severe and further reductions in costs of semiconductor devices are being demanded. As one cost reduction measure, use of wires (copper wires) made of inexpensive Cu (copper) as an alternative to wires (gold wires) made of expensive Au is being examined.

However, an FAB formed on a tip of a copper wire is harder and more difficult to deform than an FAB formed on a tip of a gold wire, and thus in comparison to the FAB formed on the tip of the gold wire, it is difficult to set conditions by which satisfactory bonding to a pad can be achieved.

As long as the size of the FAB is the same, FABs formed on tips of gold wires are satisfactorily bonded to pads using loads of the same magnitude and the same drive current of the ultrasonic transducer regardless of whether the capillary used for wire bonding is a standard type capillary or a bottleneck type capillary. However, with FABs formed on tips of copper wires, even when the load and ultrasonic transducer drive current that enable satisfactory bonding to a pad are known for a case where the capillary used for wire bonding is a standard type capillary, when the capillary is changed to a bottleneck type, satisfactory bonding to a pad cannot be achieved with the load of the same magnitude and the same ultrasonic transducer drive current.

Thus, a seventh object of the present invention related to the seventh preferred embodiment is to provide a wire bonding method that enables magnitudes of a load applied to an FAB and a drive current of an ultrasonic transducer provided in a capillary to be set readily and satisfactory bonding of a copper wire to a pad to be achieved even when the capillary used for wire bonding is changed from a standard type capillary to a bottleneck type capillary.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 56 is a schematic sectional view of a semiconductor device according to the seventh preferred embodiment of the present invention. FIG. 57 is a schematic bottom view of the semiconductor device shown in FIG. 56 .

The semiconductor device 1 G is a semiconductor device to which a QFN (quad flat non-leaded package) configuration is applied and has a structure in which a semiconductor chip 2 G is sealed together with a die pad 3 G, leads 4 G, and copper wires 5 G by a resin package 6 G. An outer shape of the semiconductor device 1 G (resin package 6 G) is a flat, rectangular parallelepiped shape.

In the present preferred embodiment, the outer shape of the semiconductor device 1 G is a hexahedron having a square shape of 4 mm square as a planar shape and a thickness of 0.85 mm, and dimensions of respective portions of the semiconductor device 1 G cited below are an example in the case where the semiconductor device 1 G has the above outer dimensions.

The semiconductor chip 2 G has a square shape of 2.3 mm in plan view, and the semiconductor chip 2 G has a thickness of 0.23 mm. A plurality of pads 7 G are disposed at peripheral edge portions of a top surface of the semiconductor chip 2 G. Each pad 7 G is electrically connected to a circuit built into the semiconductor chip 2 G. A rear metal 8 G made of a metal layer of Au, Ni (nickel), Ag (silver), etc., is formed on a rear surface of the semiconductor chip 2 G.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 2 of 27

The die pad 3 G and the leads 4 G are formed by punching out a metal thin plate (for example, a copper thin plate). The metal thin plate (die pad 3 G or lead 4 G) has a thickness of 0.2 mm. A plating layer 9 G made of Ag is formed on top surfaces of the die pad 3 G and leads 4 G.

The die pad 3 G has a square shape of 2.7 mm in plan view and is disposed at a central portion of the semiconductor device 1 G so that its respective side surfaces are parallel to side surfaces of the semiconductor device 1 G.

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface side across an entire periphery of a peripheral edge portion of the rear surface of the die pad 3 G. The resin package 6 G enters the recess. The peripheral edge portion of the die pad 3 G is thereby sandwiched from above and below by the resin package 6 G and prevention of fall-off (retaining) of the die pad 3 G with respect to the resin package 6 G is thereby achieved.

Also, with the exception of the peripheral edge portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of the die pad 3 G is exposed from a rear surface of the resin package 6 G.

An equal number of (for example, nine) leads 4 G are disposed at each of positions facing the respective side surfaces of the die pad 3 G. At each of the positions facing the side surfaces of the die pad 3 G, the leads 4 G extend in a direction orthogonal to the facing side surface and are disposed at equal intervals in a direction parallel to the side surface. A longitudinal direction length of each lead 4 G is 0.45 mm. An interval between the die pad 3 G and the lead 4 G is 0.2 mm.

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface side at a die pad 3 G side end portion of the rear surface of each lead 4 G. The resin package 6 G enters the recess. The die pad 3 G side end portion of the lead 4 G is thereby sandwiched from above and below by the resin package 6 G and prevention of fall-off (retaining) of the lead 4 G with respect to the resin package 6 G is thereby achieved.

With the exception of the die pad 3 G side end portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of each lead 4 G is exposed from a rear surface of the resin package 6 G. Also, a side surface of the lead 4 G facing the die pad 3 G side is exposed from a side surface of the resin package 6 G.

A plating layer 10 G formed of solder is formed on portions of the rear surfaces of the die pad 3 G and leads 4 G that are exposed from the resin package 6 G.

With its top surface with the pads 7 G disposed thereon facing upward, the semiconductor chip 2 G has its rear surface bonded via a bonding material 11 G to the top surface (plating layer 10 G) of the die pad 3 G. For example, a solder paste is used as the bonding material 11 G. The bonding material 11 G has a thickness of 0.02 mm.

In a case where electrical connection of the semiconductor chip 2 G and the die pad 3 G is unnecessary, the rear metal 8 G may be omitted and the rear surface of the semiconductor chip 2 G may be bonded to the top surface of the die pad 3 G via a bonding material made of silver paste or other insulating paste. In this case, the planar size of the semiconductor chip 2 G is 2.3 mm square. Also, the plating layer 9 G on the top surface of the die pad 3 G may be omitted.

The copper wires 5 G are made, for example, of copper with a purity of no less than 99.99%. One end of each copper wire 5 G is bonded to a pad 7 G of the semiconductor chip 2 G. The other end of the copper wire 5 G is bonded to the top surface of a lead 4 G. The copper wire 5 G is installed so as to form an arch-shaped loop between the semiconductor chip 2 G and the lead 4 G. A height difference between an apex portion of the loop of the copper wire 5 G and the top surface of the semiconductor chip 2 G is 0.16 mm.

As in the first preferred embodiment, in the semiconductor device 1 G, the entire top surface of the semiconductor chip 2 G, the entire top surface and side surfaces of the die pad 3 G, the entire top surfaces of the leads 4 G, and the entire copper wires 5 G are covered by an integral water-impermeable insulating film 18 G.

FIG. 58 is an enlarged view of a portion surrounded by broken lines shown in FIG. 56 .

Each pad 7 G is made of a metal that contains aluminum and is formed on an uppermost interlayer insulating film 12 G of the semiconductor chip 2 G. A top surface protective film 13 G is formed on the interlayer insulating film 12 G. The pad 7 G has its peripheral edge portion covered by the top surface protective film 13 G and its central portion is exposed via a pad opening 14 G formed in the top surface protective film 13 G.

The copper wire 5 G is bonded to the central portion of the pad 7 G exposed from the top surface protective film 13 G. As shall be described below, the copper wire 5 G has an FAB formed at its tip and the FAB is pressed against and thereby bonded to the pad 7 G. In this process, the FAB deforms to form a first ball portion 15 G with a stepped disk shape at the portion of bonding of the copper wire 5 G with the pad 7 G. Also, at a periphery of the first ball portion 15 G, the material of the pad 7 G juts out gradually from below the first ball portion 15 G so as to form a jutting portion 16 G without it being lifted greatly from the top surface of the pad 7 G.

For example, in a case where the copper wire 5 G has a wire diameter of 25 μm, an intended diameter of the first ball portion 15 G (designed diameter of the first ball portion 15 G) is 74 to 76 μm, and an intended thickness of the first ball portion 15 G (designed thickness of the first ball portion 15 G) is 17 to 18 μm.

FIG. 59A to FIG. 59D are schematic sectional views for describing a wire bonding method related to the preferred embodiment of the present invention.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 3 of 27

The copper wires 5 G are installed across the semiconductor chip 2 G and the leads 4 G by a wire bonder in a state where the die pad 3 G and the leads 4 G are connected to a frame (not shown) that surrounds these components, that is, in a state where the die pad 3 G and leads 4 G make up a lead frame.

The wire bonder includes a capillary C. As shown in FIG. 59A , the capillary C has a substantially cylindrical shape with a wire insertion hole 41 G formed along a central axis. The copper wire 5 G is inserted through the wire insertion hole 41 G and fed out from a tip (lower end) of the wire insertion hole 41 G.

A chamfer 42 G of truncated conical shape that is in communication with the wire insertion hole 41 G is formed below the wire insertion hole 41 G at a tip portion of the capillary C. Also, the tip portion of the capillary C has a face 43 G that is continuous with a lower end edge of the chamfer 42 G and is a surface that faces a pad 7 G or a lead 4 G during bonding (during wire bonding) of the copper wire 5 G to the pad 7 G or the lead 4 G. An outer side of the face 43 G is gradually inclined upwardly with respect to a plane orthogonal to the central axis of the capillary C.

First, as shown in FIG. 59A , the capillary C is moved to a position directly above the pad 7 G. Next, in a state where a tip of the copper wire 5 G is positioned at the chamfer 42 G, a current is applied to a tip portion of the copper wire 5 G and an FAB 44 is thereby formed at the tip portion. The value of the current and the application time are set suitably in accordance with the wire diameter of the copper wire 5 G and an intended diameter of the FAB 44 (designed diameter of the FAB 44 ). A portion of the FAB 44 protrudes below the chamfer 42 G.

Thereafter, as shown in FIG. 59B , the capillary C is lowered toward the pad 7 G and the FAB 44 is pressed against the pad 7 G by the capillary C. In this process, a load is applied to the FAB 44 by the capillary C and ultrasonic vibration, emitted from an ultrasonic transducer (not shown) provided in the capillary C, is applied to the FAB 44 .

FIG. 60 is a graph of changes with time of the load applied to the FAB and a driving current applied to the ultrasonic transducer during the bonding of the FAB to the pad.

For example, as shown in FIG. 60 , a relatively large initial load P 1 is applied from the capillary C to the FAB 44 from a time T 1 at which the FAB 44 contacts the pad 7 G to a time T 2 after elapse of a predetermined time period (for example, 3 msec). From the time T 2 onward, the load applied to the FAB 44 from the capillary C is decreased and a relatively small load P 2 (for example, 30 g) is applied to the FAB 44 . The load P 2 is applied continuously until a time T 4 at which the capillary C is raised.

The initial load P 1 is set based on a value obtained by multiplying an intended bonding area of the first ball portion 15 G with respect to the pad 7 G (designed bonding area of the first ball portion 15 G with respect to the pad 7 G) by a fixed factor (for example, 28786 in a case where the unit of the initial load P 1 is g and the unit of the bonding area is mm 2 ). In the present preferred embodiment, the intended bonding area of the first ball portion 15 G with respect to the pad 7 G is set at 0.00430 mm 2 and the initial load P 1 is set to 130 g.

In a case where a standard type capillary is used as the capillary C, a drive current of a value U 1 is applied to the ultrasonic transducer from before the time T 1 at which the FAB 44 contacts the pad 7 G. The drive current value U 1 is, for example, 15 mA. Then, from the time T 1 at which the FAB 44 contacts the pad 7 G to a time T 3 , the value of the drive current applied to the ultrasonic transducer is raised at a fixed rate of change (monotonously) to a value U 2 . The drive current value U 2 is, for example, 90 mA. From the time T 3 onward until the time T 4 , the drive current of the value U 2 continues to be applied to the ultrasonic transducer.

The standard type capillary has a shape such as shown in FIG. 61 and has the following dimensions. A CD dimension, which is a diameter of a lower end edge of the chamfer 42 G, is 66 μm (0.066 mm). The T dimension, which is the outer diameter of the face 43 G, is 178 μm (0.178 mm). A chamfer angle, which two straight lines extending along the side surface of the chamfer 42 G form in a cross section of the capillary C taken along a plane that includes the central axis (cross section shown in FIG. 61 ), is 90°. A face angle FA, which is an angle that the face 43 G forms with the plane orthogonal to the central axis of the capillary C, is 8°. An angle CA, which, in the cross section of the capillary C taken along the plane that includes the central axis, a portion of the side surface of the capillary C that extends upward beyond the upper end of the face 43 G forms with the central axis, is 20°.

On the other hand, when a bottleneck type capillary is used as the capillary C, a drive current of a value 1.4 times the value U 1 is applied to the ultrasonic transducer from before the time T 1 at which the FAB 44 contacts the pad 7 G as shown in FIG. 60 . Then, from the time T 1 at which the FAB 44 contacts the pad 7 G to a time T 3 , the value of the drive current applied to the ultrasonic transducer is raised at a fixed rate of change (monotonously) from the value U 1 to a value 1.4 times the value U 2 . From the time T 3 onward until the time T 4 , the drive current of the value 1.4 times the value U 2 continues to be applied to the ultrasonic transducer.

The bottleneck type capillary has a shape such as shown in FIG. 62 and has the following dimensions. The CD dimension, which is the diameter of the lower end edge of the chamfer 42 G, is 66 μm (0.066 mm). The T dimension, which is the outer diameter of the face 43 G, is 178 μm (0.178 mm). The chamfer angle, which two straight lines extending along the side surface of the chamfer 42 G form in the cross section of the capillary C taken along a plane that includes the central axis (cross section shown in FIG. 62 ), is 90°. The face angle FA, which is the angle that the face 43 G forms with the plane orthogonal to the central axis of the capillary C, is 8°. The angle CA, which, in the cross section of the capillary C taken along the plane that includes the central axis, the portion of the side surface of the capillary C that extends upward beyond the upper end of the face 43 G forms with the central axis, is 10°.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 4 of 27

Consequently, the FAB 44 deforms along the shapes of the chamfer 42 g and the face 43 G of the capillary C, and the first ball portion 15 G with a stepped click shape is formed on the pad 7 G and the jutting portion 16 G is formed along its periphery as shown in FIG. 58 . Bonding (first bonding) of the copper wire 5 G with the pad 7 G is thereby achieved.

When the time T 4 arrives upon elapse of a bonding time determined in advance from the time T 1 , the capillary C separates upwardly from the pad 7 G. Thereafter, the capillary C is moved obliquely downward toward the top surface of the lead 4 G. Then, as shown in FIG. 59C , the drive current is applied to the ultrasonic transducer, and while ultrasonic vibration is being applied to the capillary C, the copper wire 5 G is pressed against the top surface of the lead 4 G by the capillary C and then broken. A stitch portion with a wedge shape in side view that is made up of the other end portion of the copper wire 5 G is thereby formed on the top surface of the lead 4 G and the bonding (second bonding) of the copper wire with respect to the lead 4 G is thereby achieved.

Thereafter, the processes shown in FIG. 59A to FIG. 59C are performed on another pad 7 G and the corresponding lead 4 G. By the processes shown in FIG. 59A to FIG. 59C then being repeated, copper wires 5 G are installed across all pads 7 G of the semiconductor 2 G and the leads 4 G as shown in FIG. 59D . After the end of all of the wire bonding, the water-impermeable insulating film 18 G is formed by the same method as that of FIG. 4D .

As described above, after the FAB 44 formed on the tip of the copper wire 5 G is put in contact with a pad 7 G, a load is applied to the FAB 44 by the capillary C. Also, the drive current is applied to the ultrasonic transducer provided in the capillary C. Thus, while the FAB 44 deforms due to the load, the FAB 44 is rubbed against the pad 7 G by the ultrasonic vibration propagating from the ultrasonic transducer. Consequently, bonding of the FAB 44 and the pad 7 G is achieved.

In the case where the bottleneck type capillary is used as the capillary C, the values of the drive current applied to the ultrasonic transducer are set to values that are 1.4 times the values U 1 and U 2 of the drive current in the case where the standard type capillary is used as the capillary C. The magnitudes of the load and the ultrasonic transducer drive current are thereby set simply and appropriately and satisfactory bonding of the copper wire 5 G to the pad 7 G can be achieved even when the capillary C is changed from the standard type capillary to the bottleneck type capillary.

After the FAB 44 contacts the pad 7 G, the value of the drive current applied to the ultrasonic transducer is increased gradually at the fixed rate of change. Meanwhile, the load is applied to the FAB 44 so that the FAB 44 deforms in a squeezed manner and an area of the portion of contact of the FAB 44 and the pad 7 G increases gradually. The ultrasonic vibration energy propagating from the ultrasonic transducer to the FAB 44 is thereby increased gradually and the area of the FAB 44 rubbed against the pad 7 G increases gradually. Consequently, a state of satisfactory bonding to the pad 7 G can be obtained up to a peripheral edge portion of the surface of bonding of the first ball portion 15 G to the pad 7 G while suppressing occurrence of damage in the pad 7 G and a layer below the pad 7 G due to rapid increase of the ultrasonic vibration energy propagating to the FAB 44 below a central portion of the first ball portion 15 G.

Also, the drive current is applied to the ultrasonic transducer from before the contacting of the FAB 44 with the pad 7 G. Thus, from the instant at which the FAB 44 contacts the pad 7 G, the ultrasonic vibration propagates to the portion of contact of the FAB 44 and the pad 7 G and the contact portion is rubbed against the pad 7 G. Consequently, a state where a central portion of a surface of the first ball portion 15 G that bonds with the pad 7 G (portion at which the FAB 44 and the pad 7 G first make contact) is satisfactorily bonded to the pad 7 G can be obtained.

1. Test 1

The standard type capillary shown in FIG. 61 was used as the capillary C. The capillary C was positioned above a pad 7 G, and a 62 μm FAB 44 was formed at the tip of a copper wire 5 G of 30 μm wire diameter. The capillary C was then lowered toward the pad 7 G and the FAB 44 was pressed against the pad 7 G to form a first ball portion 15 G on the pad 7 G. The intended diameter of the first ball portion 15 G was 76 μm and the intended thickness of the first ball portion 15 G was 18 μm.

In this process, an initial load of 130 g was applied to the FAB 44 by the capillary C for 3 msec after the contacting of the FAB 44 with the pad 7 G, and at the point of elapse of the 3 msec, the load applied to the FAB 44 was reduced to 30 g and a state in which the load of 30 g was applied to the FAB 44 was maintained for 9 msec. Thereafter, the capillary C was raised.

Also, from before the contacting of the FAB 44 with the pad 7 G, a drive current of 15 mA was applied to an ultrasonic transducer provided in the capillary C, and after the FAB 44 contacted the pad 7 G, the value of the drive current applied to the ultrasonic transducer was raised at a fixed rate of change from 15 mA to 90 mA in an interval of 3.6 msec and then a state in which the drive current of 90 mA was applied to the ultrasonic transducer was maintained for 8.4 msec until the capillary was raised.

An SEM image obtained by imaging a vicinity of the first ball portion 15 G by an SEM (scanning electron microscope) is shown in FIG. 63 .

2. Test 2

The bottleneck type capillary shown in FIG. 62 was used as the capillary C. The capillary C was positioned above a pad 7 G, and a 59 μm FAB 44 was formed at the tip of a copper wire 5 G of 30 μm wire diameter. The capillary C was then lowered toward the pad 7 G and the FAB 44 was pressed against the pad 7 G to form a first ball portion 15 G on the pad 7 G. The intended diameter of the first ball portion 15 G was 74 μm and the intended thickness of the first ball portion 15 G was 17 μm.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 5 of 27

Also, from before the contacting of the FAB 44 with the pad 7 G, a drive current of 18 mA (15 mA×1.2) was applied to an ultrasonic transducer provided in the capillary C, and after the FAB 44 contacted the pad 7 G, the value of the drive current applied to the ultrasonic transducer was raised at a fixed rate of change from 18 mA to 108 mA (90 mA×1.2) in an interval of 3.6 msec and then a state in which the drive current of 108 mA was applied to the ultrasonic transducer was maintained for 8.4 msec until the capillary was raised.

An SEM image of a vicinity of the first ball portion 15 G is shown in FIG. 64 .

3. Test 3

Also, from before the contacting of the FAB 44 with the pad 7 G, a drive current of 19.5 mA (15 mA×1.3) was applied to an ultrasonic transducer provided in the capillary C, and after the FAB 44 contacted the pad 7 G, the value of the drive current applied to the ultrasonic transducer was raised at a fixed rate of change from 19.5 mA to 117 mA (90 mA×1.3) in an interval of 3.6 msec and then a state in which the drive current of 117 mA was applied to the ultrasonic transducer was maintained for 8.4 msec until the capillary was raised.

An SEM image of a vicinity of the first ball portion 15 G is shown in FIG. 65 .

4. Test 4

Also, from before the contacting of the FAB 44 with the pad 7 G, a drive current of 21 mA (15 mA×1.4) was applied to an ultrasonic transducer provided in the capillary C, and after the FAB 44 contacted the pad 7 G, the value of the drive current applied to the ultrasonic transducer was raised at a fixed rate of change from 21 mA to 126 mA (90 mA×1.4) in an interval of 3.6 msec and then a state in which the drive current of 126 mA was applied to the ultrasonic transducer was maintained for 8.4 msec until the capillary was raised.

An SEM image of a vicinity of the first ball portion 15 G is shown in FIG. 66 .

5. Test 5

Also, from before the contacting of the FAB 44 with the pad 7 G, a drive current of 22.5 mA (15 mA×1.5) was applied to an ultrasonic transducer provided in the capillary C, and after the FAB 44 contacted the pad 7 G, the value of the drive current applied to the ultrasonic transducer was raised at a fixed rate of change from 22.5 mA to 135 mA (90 mA×1.5) in an interval of 3.6 msec and then a state in which the drive current of 135 mA was applied to the ultrasonic transducer was maintained for 8.4 msec until the capillary was raised.

An SEM image of a vicinity of the first ball portion 15 G is shown in FIG. 67 .

6. Comparison of Tests 1 to 5

In all of tests 1 to 5, the first ball portions 15 G with diameters and thicknesses substantially equal to the intended diameters and thicknesses were formed.

The SEM image of test 1 shows that the jutting portion 16 G, which juts out to a degree to which it is not lifted from the top surface of pad G 7 , is formed at the periphery of the first ball portion 15 G.

Comparison of the SEM image of test 1 with the SEM image of test 2 shows the size of the jutting portion 16 G of test 2 to be smaller than the size of the jutting portion 16 G of test 1.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 6 of 27

Comparison of the SEM image of test 1 with the SEM images of tests 3 to 5 shows that the size of the jutting portion 16 G of test 1 and the size of the jutting portion 16 G of each of tests 3 to 5 to be substantially the same and that the shape of the jutting portion 16 G of test 1 is especially close to the shape of the jutting portion 16 G of test 4.

From the results of tests 1 to 5, it was confirmed that in the case of using the bottleneck type capillary as the capillary C, by setting the value of the drive current applied to the ultrasonic transducer to 1.3 to 1.5 times the value of the drive current applied to the ultrasonic transducer in the case of using the standard type capillary as the capillary C, a state of bonding of the FAB 44 and the pad 7 G that is close to that in the case of using the standard type capillary as the capillary C can be obtained. It was also confirmed that in the case of using the bottleneck type capillary as the capillary C, by setting the value of the drive current applied to the ultrasonic transducer to 1.4 times the value of the drive current applied to the ultrasonic transducer in the case of using the standard type capillary as the capillary C, a state of bonding of the FAB 44 and the pad 7 G that is substantially the same as that in the case of using the standard type capillary as the capillary C can be obtained.

Although the seventh preferred embodiment of the present invention has been described above, the seventh preferred embodiment may also be modified as follows.

For example, although a QFN package type is applied to the semiconductor device 1 G, the present invention may also be applied to the manufacture of a semiconductor device to which another type of non-leaded package, such as an SON (small outlined non-leaded package), is applied.

The present invention may also be applied to the manufacture of not only semiconductor devices to which a so-called singulation type package, with end surfaces of leads being made flush with side surfaces of a resin package, is applied but also semiconductor devices to which a lead cut type non-leaded package, with leads projecting from side surfaces of a resin package, is applied.

Further, the present invention may be applied to the manufacture of not only semiconductor devices to which a non-leaded package is applied but also semiconductor devices to which a QFP (quad flat package) or other package having outer leads formed by leads projecting from a resin package is applied.

Also, although with the above-described preferred embodiment, a mode in which the copper wires 5 G are covered by the water-impermeable insulating film 18 G was described as an example, the water-impermeable insulating film 18 G may be omitted as shown in FIG. 68 as long as at least the seventh object for resolving the seventh issue is achieved.

Eighth Preferred Embodiment FIG. 69 to FIG. 73

By disclosure of an eighth preferred embodiment, an eighth issue concerning an eighth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Eighth Background Art

In a typical semiconductor device, a semiconductor chip is disposed on a die pad and the semiconductor chip is connected by wires (gold wires) made of Au (gold) to leads disposed at a periphery of the die pad. Specifically, pads made of Al (aluminum) are disposed on a top surface of the semiconductor chip. The gold wires are installed so as to form arch-shaped loops between top surfaces of the pads and top surfaces of the leads.

(2) Eighth Issue

However, presently, replacement of gold wires by copper wires is yet to be carried out actively. This is because a copper wire itself is oxidized readily, a portion (first ball portion) of a copper wire that is bonded with a pad is oxidized especially readily, and there are cases where a bond portion becomes oxidized and peeling (first open) of the bond portion from the pad occurs in a humidity resistance evaluation test (such as an HAST (highly accelerated stress test), PCT (pressure cooker test)) performed after sealing of the semiconductor chip and the copper wires in a resin package.

Thus, an eighth object of the present invention related to the eighth preferred embodiment is to provide a semiconductor device with which a portion of a copper wire bonded to a pad is unlikely to be oxidized and peeling of the bond portion from the pad due to the oxidation can be prevented.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 69 is a schematic sectional view of a semiconductor device according to the eighth preferred embodiment of the present invention.

The semiconductor device 1 H is a semiconductor device to which a QFN (quad flat non-leaded package) configuration is applied and has a structure in which a semiconductor chip 2 H is sealed together with a die pad 3 H, leads 4 H, and copper wires 5 H by a resin package 6 H. An outer shape of the semiconductor device 1 H (resin package 6 H) is a flat, rectangular parallelepiped shape.

In the present preferred embodiment, the outer shape of the semiconductor device 1 H is a hexahedron having a square shape of 4 mm square as a planar shape and a thickness of 0.85 mm, and dimensions of respective portions of the semiconductor device 1 H cited below are an example in the case where the semiconductor device 1 H has the above outer dimensions.

The semiconductor chip 2 H has a square shape of 2.3 mm in plan view, and the semiconductor chip 2 H has a thickness of 0.23 mm. A rear metal 7 H made of a metal layer of Au, Ni (nickel), Ag (silver), etc., is formed on a rear surface of the semiconductor chip 2 H.

The die pad 3 H and the leads 4 H are formed by punching out a metal thin plate (for example, a copper thin plate). The metal thin plate (die pad 3 H or lead 4 H) has a thickness of 0.2 mm. A plating layer 8 H made of Ag is formed on top surfaces of the die pad 3 H and leads 4 H.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 7 of 27

The die pad 3 H has a square shape of 2.7 mm in plan view and is disposed at a central portion of the semiconductor device 1 H so that its respective side surfaces are parallel to side surfaces of the semiconductor device 1 H.

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface side across an entire periphery of a peripheral edge portion of the rear surface of the die pad 3 H. The resin package 6 H enters the recess. The peripheral edge portion of the die pad 3 H is thereby sandwiched from above and below by the resin package 6 H and prevention of fall-off (retaining) of the die pad 3 H with respect to the resin package 6 H is thereby achieved.

Also, with the exception of the peripheral edge portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of the die pad 3 H is exposed from a rear surface of the resin package 6 H.

An equal number of (for example, nine) leads 4 H are disposed at each of positions facing the respective side surfaces of the die pad 3 H. At each of the positions facing the side surfaces of the die pad 3 H, the leads 4 H extend in a direction orthogonal to the facing side surface and are disposed at equal intervals in a direction parallel to the side surface. A longitudinal direction length of each lead 4 H is 0.45 mm. An interval between the die pad 3 H and the lead 4 H is 0.2 mm.

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface side at a die pad 3 H side end portion of the rear surface of each lead 4 H. The resin package 6 H enters the recess. The die pad 3 H side end portion of the lead 4 H is thereby sandwiched from above and below by the resin package 6 H and prevention of fall-off (retaining) of the lead 4 H with respect to the resin package 6 H is thereby achieved.

With the exception of the die pad 3 H side end portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of each lead 4 H is exposed from a rear surface of the resin package 6 H. Also, a side surface of the lead 4 H facing the die pad 3 H side is exposed from a side surface of the resin package 6 H.

A plating layer 9 H formed of solder is formed on portions of the rear surfaces of the die pad 3 H and leads 4 H that are exposed from the resin package 6 H.

The semiconductor chip 2 H has, in a state where its top surface faces upward, its rear surface bonded via a bonding material 10 H to the top surface (plating layer 9 H) of the die pad 3 H. For example, a solder paste is used as the bonding material 10 H. The bonding material 10 H has a thickness of 0.02 mm.

In a case where electrical connection of the semiconductor chip 2 H and the die pad 3 H is unnecessary, the rear metal H may be omitted and the rear surface of the semiconductor chip 2 H may be bonded to the top surface of the die pad 3 H via a bonding material made of silver paste or other insulating paste. In this case, the planar size of the semiconductor chip 2 H is 2.3 mm square. Also, the plating layer 8 H on the top surface of the die pad 3 H may be omitted.

One end of each copper wire 5 H is bonded to a top surface of the semiconductor chip 2 H. The other end of the copper wire 5 H is bonded to the top surface of a lead 4 H. The copper wire 5 H is installed so as to form an arch-shaped loop between the semiconductor chip 2 H and the lead 4 H. A height difference between an apex portion of the loop of the copper wire 5 H and the top surface of the semiconductor chip 2 H is 0.16 mm.

As in the first preferred embodiment, in the semiconductor device 1 H, the entire top surface of the semiconductor chip 2 H, the entire top surface and side surfaces of the die pad 3 H, entire top surfaces of the leads 4 H, and the entire copper wires 5 H are covered by an integral water-impermeable insulating film 18 H.

FIG. 70 is a schematic sectional view of a pad and a portion of a copper wire bonded to the pad.

The semiconductor chip 2 H includes a silicon substrate or other semiconductor substrate (not shown). A plurality of interlayer insulating films 21 H and 22 H are laminated on the semiconductor substrate. A plurality of wirings 23 H are formed between the uppermost interlayer insulating film 21 H and the interlayer insulating film 22 H therebelow. The wirings 23 H are made of a metal that contains Al.

Openings 24 H that expose portions of the respective wirings 23 H are formed in the interlayer insulating film 21 H at peripheral edge portions of the top surface of the semiconductor chip 2 H. Pads 25 H are formed at the portions of the wirings 23 H that are exposed via the openings 24 H. The pads 25 H are made of Zn and are formed by sputtering. Each pad 25 H completely fills an interior of the corresponding opening 24 H and a peripheral edge portion thereof rides on top of the interlayer insulating film 21 H. A thickness of the pad 25 H above the interlayer insulating film 21 H is 7000 to 28000 Å (0.7 to 2.8 μm).

A barrier film 26 H is formed between the wirings 23 H and the pads 25 H. The barrier film 26 H has a structure in which a Ti layer made of Ti and a TiN layer made of TiN are laminated in that order from the wiring 23 H side.

In FIG. 70 , just one each of the wirings 23 H, openings 24 H, and pads 25 H are shown.

A top surface protective film 27 H is formed on a topmost surface of the semiconductor chip 2 H. The top surface protective film 27 H is made, for example, of silicon nitride (SiN). Pad openings 28 H for exposing central portions of top surfaces of the pads 25 H are formed at positions of the top surface protective film 27 H that face the pads 25 H.

Each copper wire 5 H is made, for example, of copper with a purity of no less than 99.99%. The copper wire 5 H is bonded to the central portion of the pad 25 H exposed from the top surface protective film 27 H. The copper wire 5 H has an FAB formed at its tip and the FAB is pressed against and thereby bonded to the pad 25 H. In this process, the FAB deforms and a portion (first ball portion) 29 of the copper wire 5 H bonded to the pad 25 H thereby takes on a stepped disk shape. During thermal aging after the forming of the resin package 6 H, the Cu contained in the copper wire 5 H and the Zn contained in the pad 25 H undergo eutectic bonding and an alloy of Cu and Zn (brass) is formed at least at a lower portion of the bond portion 29 H and a portion of the pad 25 H that faces the bond portion 29 H (portion surrounded by broken lines in FIG. 70 ). Thermal aging is a process for stabilizing the resin package 6 H and is a process of letting the semiconductor device 1 H stand for a fixed time under a fixed temperature.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 8 of 27

There are cases where the entire pad 25 H and bond portion 29 H undergo Zn—Cu alloying. For example, when thermal aging is performed for 6 hours under a temperature of 175° C., the entire pad 25 H and bond portion 29 H undergo Zn—Cu alloying even when a maximum thickness (thickness above the wiring 23 H) of the pad 25 H is 10 μm.

As described above, the bond portion 29 H of the copper wire 5 H is made of the Zn—Cu alloy. The bond portion 29 H thus does not oxidize readily. Peeling of the bond portion 29 H from the pad 25 H due to oxidation can thus be prevented.

Also, the barrier film 26 H having structure in which the Ti layer made of Ti and the TiN layer made of TiN are laminated in that order from the wiring 23 H side is interposed between the wiring 23 H and the pad 25 H. By the barrier film 26 H being interposed, eutectic bonding of the Al contained in the wiring 23 H and the Zn contained in the pad 25 H can be prevented.

FIG. 71 is a schematic sectional view of a pad and a portion of a copper wire bonded to the pad according to another structure. In FIG. 71 , portions corresponding to the respective portions shown in FIG. 70 are provided with the same reference symbols as the reference symbols provided to the abovementioned respective portions. In the following description, points of difference of the structure shown in FIG. 71 with respect to the structure shown in FIG. 70 shall be described mainly and description of the portions provided with the same reference symbols as the respective portions shown in FIG. 70 shall be omitted.

A pad 31 H is formed on a portion of the wiring 23 H exposed via the opening 24 H. The pad 31 H includes a pad main body portion 32 H and a Zn layer 33 H formed on a top surface of the pad main body portion 32 H.

The pad main body portion 32 H is made of Al and is formed by electroplating. The pad main body portion 32 H completely fills the interior of the opening 24 H and a peripheral edge portion thereof rides on top of the interlayer insulating film 21 H. A thickness of the pad main body 32 H above the interlayer insulating film 21 H is 7000 to 28000 Å (0.7 to 2.8 μm). The pad main body portion 32 H contacts the wiring 23 H directly.

The Zn layer 33 H is made of Zn and is formed by electroless plating. The Zn layer 33 H is formed inside the pad opening 28 H formed in the top surface protective film 27 H so as to cover the portion of the pad main body portion 32 H that is exposed from the pad opening 28 H.

A barrier film 34 H is formed between the pad main body portion 32 H and the Zn layer 33 H. The barrier film 34 H has a structure in which a Ti layer made of Ti and a TiN layer made of TiN are laminated in that order from the pad main body portion 32 H side.

Each copper wire 5 H is made, for example, of Cu with a purity of no less than 99.99%. The copper wire 5 H is bonded to the central portion of the pad 31 H (Zn layer 33 H) exposed from the top surface protective film 27 H. The copper wire 5 H has an FAB formed at its tip and the FAB is pressed against and thereby bonded to the pad 31 H. In this process, the FAB deforms and a portion (first ball portion) 29 of the copper wire 5 H bonded to the pad 31 H thereby takes on a stepped disk shape. During thermal aging after the forming of the resin package 6 H, the Cu contained in the copper wire 5 H and the Zn contained in the Zn layer 33 H undergo eutectic bonding and an alloy of Cu and Zn (brass) is formed at least at a lower portion of the bond portion 29 H and a portion of the Zn layer 33 H of the pad 31 H that faces the bond portion 29 H (portion surrounded by broken lines in FIG. 71 ).

There are cases where the entire Zn layer 33 H and bond portion 29 H undergo Zn—Cu alloying.

The bond portion 29 H of the copper wire 5 H is made of the Zn—Cu alloy in the present structure as well. The bond portion 29 H thus does not oxidize readily. Peeling of the bond portion 29 H from the pad 31 H due to oxidation can thus be prevented.

Also, the barrier film 34 H having structure in which the Ti layer made of Ti and the TiN layer made of TiN are laminated in that order from the pad main body 32 H side is interposed between the pad main body portion 32 H and the Zn layer 33 H of the pad 31 H. By the barrier film 34 H being interposed, eutectic bonding of the Al contained in the pad main body portion 32 H and the Zn contained in the Zn layer 33 H can be prevented.

FIG. 72 is a schematic sectional view of a pad and a portion of a copper wire bonded to the pad according to yet another structure. In FIG. 72 , portions corresponding to the respective portions shown in FIG. 70 are provided with the same reference symbols as the reference symbols provided to the abovementioned respective portions. In the following description, points of difference of the structure shown in FIG. 72 with respect to the structure shown in FIG. 70 shall be described mainly and description of the portions provided with the same reference symbols as the respective portions shown in FIG. 70 shall be omitted.

Pads 41 H are formed at the portions of the wirings 23 H that are exposed via the openings 24 H. The pads 41 H are made of Al and are formed by electroplating. Each pad 41 H completely fills the interior of the corresponding opening 24 H and a peripheral edge portion thereof rides on top of the interlayer insulating film 21 H. A thickness of the pad 41 H above the interlayer insulating film 21 H is 7000 to 28000 Å (0.7 to 2.8 μm). Also, the pad 41 H contacts the wiring 23 H directly.

An entirety of each copper wire 5 H is made, for example, of an alloy of Cu and Zn (brass). The copper wire 5 H is bonded to the central portion of the pad 41 H exposed from the top surface protective film 27 H. The copper wire 5 H has an FAB formed at its tip and the FAB is pressed against and thereby bonded to the pad 41 H. In this process, the FAB deforms and a portion (first ball portion) 29 of the copper wire 5 H bonded to the pad 41 H thereby takes on a stepped disk shape.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 9 of 27

Although the eighth preferred embodiment of the present invention has been described above, the eighth preferred embodiment may also be modified as follows.

For example, with the structures shown in FIGS. 70 and 71 , arrangements in which a copper wire made of Cu of a purity of no less than 99.99% was taken up as an example of the copper wire 5 H, Cu of a lower purity may be used instead as the copper wire 5 H. Also, a copper wire with which the entirety is made of an alloy of Cu and Zn may be used as the copper wire 5 H.

Also, although with the above-described preferred embodiment, a mode in which the copper wires 5 H are covered by the water-impermeable insulating film 18 H was described as an example, the water-impermeable insulating film 18 H may be omitted as shown in FIG. 73 as long as at least the eighth object for resolving the eighth issue is achieved.

Ninth Preferred Embodiment FIG. 74 to FIG. 82

By disclosure of a ninth preferred embodiment, a ninth issue concerning a ninth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Ninth Background Art

A resin sealed type semiconductor device has a structure in which a semiconductor chip is sealed together with a lead frame by a resin package. The lead frame is formed by punching out a metal thin plate and includes a die pad and a plurality of leads disposed at a periphery of the die pad. The semiconductor chip is die bonded onto an upper surface of the die pad and is electrically connected to the respective leads by bonding wires installed between its top surface and the respective leads.

During operation of the semiconductor device, the semiconductor chip generates heat. The heat generated from the semiconductor chip is transmitted to the resin package through portions of contact of the semiconductor chip with the resin package and is also transmitted to the die pad and the leads and then transmitted to the resin package through portions of contact of the die pad and the leads with the resin package. The heat generated from the semiconductor chip that is thus transmitted to the resin package is radiated from a top surface of the resin package.

When a heat generation amount of a semiconductor chip exceeds a heat radiation amount from the resin package, the semiconductor device may enter an overheated state. Thus, from before, the material of the resin package has been modified to improve heat radiation property.

(2) Ninth Issue

However, there is a limit to improving the head radiation property by modification of the material of the resin package. Especially, with a semiconductor chip in which a power system device is built in, the heat generation amount of the semiconductor chip is high and further improvement in the heat radiation property is demanded.

Thus, a ninth object of the present invention related to the ninth preferred embodiment is to provide a semiconductor device that enables further improvement in the heat radiation property.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 74 is a schematic sectional view of a semiconductor device according to the ninth preferred embodiment of the present invention. FIG. 75 is a schematic plan view of the semiconductor device shown in FIG. 74 and shows a state where illustration of a resin package is omitted.

The semiconductor device 1 I has a structure in which a semiconductor chip 2 I is sealed together with a lead frame 31 by a resin package 4 I. The resin package 4 I is formed to a quadrilateral shape in plan view.

The lead frame 31 includes a die pad 5 I disposed at a central portion of the semiconductor device 1 I and a plurality of (ten in the present preferred embodiment) leads 6 I disposed at a periphery of the die pad 5 I. The lead frame 31 is formed, for example, by performing a punching process and a pressing process on a copper (Cu) thin plate.

The die pad 5 I integrally includes a central portion 7 I of quadrilateral shape in plan view that has its center overlapped with a center of the resin package 4 I in plan view and has four sides extending parallel to the respective sides of the resin package 4 I, and suspending portions 8 I of quadrilateral shape in plan view that extend to side surfaces of the resin package 4 I from two mutually opposite sides among the four sides of the central portion 7 I.

With respect to the central portion 7 I of the die pad 5 I, five each of the leads 6 I are disposed at equal intervals at each of both sides of a direction orthogonal to a direction of extension (hereinafter, referred to as “extension direction”) of the suspending portions 8 I.

Each lead 6 I penetrates through a side surface of the resin package 4 I and a portion that is sealed by the package 4 I makes up an inner lead portion to which a bonding wire 13 I to be described later is connected and a portion exposed from the resin package 4 I makes up an outer lead portion for connection with a circuit board on which the semiconductor device 1 I is mounted.

An upper surface of the die pad 5 I and upper surfaces of the inner lead portions of the respective leads 6 I are coated with silver thin films 9 I and 47 I by application of a silver (Ag) plating process.

With its top surface at a side with elements formed thereon facing upward, the semiconductor chip 2 I has its rear surface bonded (die bonded) to the die pad 5 I via a solder bonding material 10 I of paste form. The top surface of the semiconductor chip 2 I is covered by a top surface protective film 11 I. Also, ten pads 12 I are formed on the top surface of the semiconductor chip 2 I by selective removal of the surface protective film 11 I.

Each pad 12 I is formed to a quadrilateral shape in plan view, and in the semiconductor chip 2 I, five each is provided along an edge portion of each of two sides extending parallel to sides of the die pad 5 I that face the leads 6 I.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 10 of 27

One end of a bonding wire 13 I is bonded to each pad 12 I. The other end of each bonding wire 13 I is bonded to the upper surface of the lead 6 I corresponding to the pad 12 I. The semiconductor chip 2 I is thereby electrically connected to the leads 6 I via the bonding wires 13 I.

As in the first preferred embodiment, in the semiconductor device 1 I, the entire top surface of the semiconductor chip 2 I, entire top surface and side surfaces of the die pad 5 I, the entire top surfaces of the leads 6 I, and the entire bonding wires 13 I are covered by an integral water-impermeable insulating film 19 I.

In plan view, the semiconductor chip 2 I is smaller than the die pad 5 I and the top surface of the die pad 5 I is exposed at a periphery of the semiconductor chip 2 I. A plurality of dummy wires 15 I, 16 I, and 17 I made of copper are bonded to the top surface (silver thin films 9 I and 47 I) of the die pad 5 I exposed at the periphery of the semiconductor chip 2 I.

Specifically, as shown in FIG. 75 , the plurality of dummy wires 15 I, which extend in the extension direction and are mutually spaced at intervals in a direction orthogonal to the extension direction, and the plurality of dummy wires 16 I, which are orthogonal to the dummy wires 15 I and are mutually spaced at intervals in the extension direction, are provided between the semiconductor chip 2 I and the respective suspending portions 8 I. Each of the dummy wires 15 I and 16 I has both end portions thereof bonded to the top surface of the die pad 5 I and is formed to an arch shape that is bulged at a central portion. The central portion of a dummy wire 15 I may be in mutual contact with the central portion of a dummy wire 16 I. Such dummy wires 15 I and 16 I are obtained using a wire bonder to form the dummy wires 15 I and thereafter forming the dummy wires 16 I so as to span across the respective dummy wires 15 I.

Also, the plurality of dummy wires 17 I that extend along the extension direction are formed between the semiconductor chip 2 I and the leads 6 I. Each dummy wire 17 I has both end portions thereof bonded to the top surface of the die pad 5 I and is formed to an arch shape that is bulged at a central portion. The central portions of the dummy wires 17 I are formed to a height that does not interfere with the respective bonding wires 13 I.

Also, a plurality of dummy wires 18 I are formed as shown in FIG. 74 at a lower surface of the die pad 5 I at the side opposite the surface of bonding with the semiconductor chip 2 I. As with the dummy wires 15 I and the dummy wires 16 I, the dummy wires 18 I extend in the extension direction and the direction orthogonal thereto and are formed in a lattice.

The respective dummy wires 15 I, 16 I, 17 I, and 18 I thus do not contact the semiconductor chip 2 I or anyone of the leads 6 I and do not contribute to electrical connection of the semiconductor chip 2 I with the die pad 5 I and the leads 6 I.

As described above, the bonding wires 13 I made of copper are installed between the semiconductor chip 2 I bonded to the die pad 5 I and the leads 6 I disposed at the periphery of the die pad 5 I. The semiconductor chip 2 I and the leads 6 I are electrically connected by the bonding wires 13 I. Also, the semiconductor device 1 I is provided with the dummy wires 15 I, 16 I, 17 I, and 18 I that do not contribute to electrical connection of the semiconductor chip 2 I with the die pad 5 I and the leads 6 I. The dummy wires 15 I, 16 I, 17 I, and 18 I are made of copper.

During operation of the semiconductor device 1 I, heat generated from the semiconductor chip 2 I is transmitted to the die pad 5 I, the leads 6 I, and the dummy wires 15 I, 16 I, 17 I, and 18 I. The transmitted heat then propagates through the resin package 4 I that seals the above components together and is released (radiated) from the top surface of the resin package 4 I. Thus, by the dummy wires 15 I, 16 I, 17 I, and 18 I being provided, efficiency of heat transmission to the resin package 4 I can be improved and heat radiation property of the semiconductor device 1 I can be improved in comparison to an arrangement in which the dummy wires 15 I, 16 I, 17 I, and 18 I are not provided.

Also, the dummy wires 15 I, 16 I, 17 I, and 18 I do not contribute to electrical connection of the semiconductor chip 2 I with the die pad 5 I and the leads 6 I. Contact of the dummy wires 15 I, 16 I, 17 I, and 18 I with each other thus does not have to be considered and there are no restrictions in the positioning thereof, and thus the dummy wires 15 I, 16 I, 17 I, and 18 I can be disposed as densely as is physically possible. Consequently, further improvement in the heat radiation property of the semiconductor device 1 I can be achieved.

Also, each of the dummy wires 15 I, 16 I, 17 I, and 18 I is a looped metal wire having both end portions bonded to the die pad 5 I (silver thin film 9 I and 47 I). The dummy wires 15 I, 16 I, 17 I, and 18 I may thus be formed using a wire bonder. Addition of a device for forming the dummy wires 15 I, 16 I, 17 I, and 18 I can thus be avoided.

Also, the dummy wires 15 I, 16 I, 17 I, and 18 I are made of copper. Copper is inexpensive and the dummy wires 15 I, 16 I, 17 I, and 18 I can thus be reduced in material cost. Also, copper is high in heat transfer coefficient and can thus improve a heat radiation amount of the semiconductor device 1 I.

Also, the bonding wires 13 I are made of copper. Copper is inexpensive and the bonding wires 13 I can thus be reduced in material cost. Also, copper is high in electrical conductivity and thus enables reduction in electrical resistance between the semiconductor chip 2 I and the leads 6 I.

FIG. 76 is a schematic sectional view of a first modification example of the semiconductor device shown in FIG. 74 . In FIG. 76 , portions corresponding to the respective portions shown in FIG. 74 are provided with the same reference symbols as the reference symbols provided to the abovementioned respective portions. In the following description, points of difference of the structure shown in FIG. 76 with respect to the structure shown in FIG. 74 shall be described mainly and description of the portions provided with the same reference symbols as the respective portions shown in FIG. 74 shall be omitted.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 11 of 27

In a semiconductor device 21 I shown in FIG. 76 , a plurality of stud bumps 22 I are disposed in place of the dummy wires 15 I, 16 I, 17 I, and 18 I shown in FIG. 74 .

Each stud bump 22 I formed on the upper surface of the die pad 5 I is formed to a stepped disk shape that is narrower at an upper side and is disposed overlapplingly in a plurality of steps to a height such that contact is not made with any bonding wire 13 I. Meanwhile, each stud bump 22 I formed on the lower surface of the die pad 5 I is formed to a stepped disk shape that is narrower at a lower side and is disposed overlapplingly in a plurality of steps to a height of not being exposed from the resin package 4 I on the lower surface of the semiconductor device 21 I.

Such a semiconductor device 21 I that includes the stud bumps 22 I is obtained, for example, by forming the stud bumps 22 I at the upper side in a state where the upper surface of the die pad 5 I faces upward and then turning over the semiconductor device 21 I to form the stud bumps 22 I at the lower side in a state where the lower surface of the die pad 5 I faces upward.

The same effects as those of the semiconductor device 1 I shown in FIG. 74 can be obtained by the arrangement of the semiconductor device 21 I as well.

Also, the stud bumps 22 I may be formed using a wire bonder. Addition of a device for forming the stud bumps 22 I can thus be avoided. Also, the stud bumps 22 I can be positioned without having to consider mutual contact of the stud bumps 22 I, and thus the stud bumps 22 I can be formed at as small an interval as can be formed using the wire bonder.

Also, a plurality of stud bumps 22 I are layered overlappingly. The height of the stud bumps 22 I can thus be changed according to a dead space inside the semiconductor device 21 I and a surface area of the stud bumps 21 I can thus be made even greater. Consequently, further improvement in the heat radiation property of the semiconductor device can be achieved.

FIG. 77 is a schematic sectional view of a second modification example of the semiconductor device shown in FIG. 74 . In FIG. 77 , portions corresponding to the respective portions shown in FIG. 74 are provided with the same reference symbols as the reference symbols provided to the abovementioned respective portions. In the following description, points of difference of the structure shown in FIG. 77 with respect to the structure shown in FIG. 74 shall be described mainly and description of the portions provided with the same reference symbols as the respective portions shown in FIG. 74 shall be omitted.

With a semiconductor device 31 I shown in FIG. 77 , the dummy wires 15 I, 16 I, 17 I, and 18 I shown in FIG. 74 and the stud bumps 22 I shown in FIG. 76 are disposed in a combined state.

Specifically, stud bumps 33 I of stepped disk shape are disposed overlappingly in a plurality of steps at the upper surface and the lower surface of the die pad 5 I. Dummy wires 32 I, each having both end portions thereof connected to the silver thin film 9 I or 47 I, are disposed so as to span across the stud bumps 33 I. Each dummy wire 32 I has both end portions thereof bonded to the top surface of the die pad 5 I and is formed to an arch shape that is bulged at a central portion. In other words, at an inner side portion of the loop of each dummy wire 32 I (portion between the central portion of the dummy wire 32 I and the die pad 5 I), a plurality of stud bumps 33 I are disposed overlappingly in a plurality of steps in accordance with the height of the central portion of the dummy wire 32 I.

The same effects as those of the semiconductor device 1 I shown in FIG. 74 can be obtained by the arrangement of the semiconductor device 31 I as well.

Also, the positional density of the dummy wires 32 I and the stud bumps 33 I can be made even higher because the stud bumps 33 I are disposed at gaps of the loop portions of the dummy wires 32 I and thus further improvement in the heat radiation property of the semiconductor device 31 I can be achieved.

FIG. 78 is a schematic sectional view of a third modification example of the semiconductor device shown in FIG. 74 .

A semiconductor device 41 I is a so-called surface mounted type semiconductor device with which rear surfaces of a die pad and leads are exposed from a rear surface of a resin package.

The semiconductor device 41 I has a structure in which a semiconductor chip 42 I is sealed together with a lead frame 43 I by a resin package 44 I. An outer shape of the semiconductor device 41 I is a flat, rectangular parallelepiped shape (in the present preferred embodiment, a hexahedron having a square shape in plan view).

The lead frame 43 I includes a die pad 45 I disposed at a central portion of the semiconductor device 1 I and a plurality of leads 46 I disposed at a periphery of the die pad 45 I. The lead frame 43 I is formed, for example, by performing a punching process and a pressing process on a copper thin plate.

The die pad 45 I has a quadrilateral shape in plan view. A lower surface of the die pad 45 I is exposed at a rear surface of the resin package 44 I.

The leads 46 I are disposed at sides of the die pad 45 I in plan view. A lower surface of each lead 46 I is exposed at the rear surface of the resin package 44 I and functions as an external terminal for connection with a wiring circuit board (not shown).

An upper surface of the die pad 45 I and upper surfaces of the respective leads 46 I are coated by a silver thin film 47 I by application of a silver plating process.

With its top surface at a side with functional elements formed thereon (device forming surface) facing upward, the semiconductor chip 42 I has its rear surface bonded (die bonded) to the die pad 45 I via a conductive solder bonding material 48 I.

At the top surface of the semiconductor chip 42 I, pads 49 I are formed in correspondence to the respective leads 46 I by exposure of portions of a wiring layer from a top surface protective film. Each pad 49 I is bonded to one end of a bonding wire 50 I made of copper. The other ends of the bonding wires 50 I are bonded to the upper surfaces of the respective leads 46 I. The semiconductor chip 42 I is thereby electrically connected to the leads 46 I via the bonding wires 50 I.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 12 of 27

In plan view, the semiconductor chip 42 I is smaller than the die pad 45 I and the top surface of the die pad 45 I is exposed at a periphery of the semiconductor chip 42 I. A plurality of dummy wires 51 I made of copper are bonded to the top surface (silver thin films 47 I) of the die pad 45 I exposed at the periphery of the semiconductor chip 42 I. Each of the dummy wires 51 I has both end portions thereof bonded to the top surface of the die pad 45 I and is formed to an arch shape that is bulged at a central portion while being spaced at intervals from the die pad 45 I. Also, the respective dummy wires 51 I do not contact the semiconductor chip 42 I or any one of the leads 46 I and do not contribute to electrical connection of the semiconductor chip 42 I with the die pad 45 I and the leads 46 I.

The same effects as those of the semiconductor device 1 I shown in FIG. 74 can be obtained by the arrangement of the semiconductor device 431 I as well.

In the semiconductor device 41 I, stud bumps may be provided in place of the dummy wires 51 I in the same manner as in the semiconductor device 21 I shown in FIG. 76 , or a combination of the dummy wires 51 I and stud bumps may be adopted in the same manner as in the semiconductor device 31 I shown in FIG. 77 .

Although the ninth preferred embodiment of the present invention has been described above, the ninth preferred embodiment may also be modified as follows.

For example, with each of the semiconductor devices 1 I, 21 I, 31 I, and 41 I shown in FIG. 74 to FIG. 78 , the dummy wires 15 I, 16 I, 17 I, 18 I, or 51 I and/or the stud bumps 22 I or 33 I are formed on the die pad 5 I. However, the dummy wires 15 I, 16 I, 17 I, 18 I, or 51 I and/or the stud bumps 22 I or 33 I may instead be formed on the leads 6 I or 46 I.

In each of the semiconductor devices 1 I, 21 I, and 31 I, the silver thin films 9 I and 47 I are formed on the upper surface of the die pad 5 I and the upper surfaces of the inner lead portions of the lead 6 I to enable the bonding wires 13 I to be bonded satisfactorily to the leads 6 I and the dummy wires 15 I, 16 I, and 17 I to be bonded satisfactorily to the die pad 5 I.

Also, in the semiconductor device 41 I, the silver thin film 47 I is formed on the upper surface of the die pad 45 I and the upper surfaces of the lead 46 I to enable the bonding wires 50 I to be bonded satisfactorily to the leads 46 I and the dummy wires 51 I to be bonded satisfactorily to the die pad 45 I.

However, the silver thin films 9 I and 47 I are not required necessarily and the bonding of the bonding wires 13 I or 50 I to the leads 6 I or 46 I and the bonding of the dummy wires 15 I, 16 I, 17 I, or 51 I to the die pad 5 I or 45 I can be achieved even if the silver thin films 9 I and 47 I are omitted.

By omission of the silver thin films 9 I and 47 I, reduction in material cost can be achieved. Also, the silver plating process for forming the silver thin films 9 I and 47 I is omitted and a number of manufacturing steps of each of the semiconductor devices 1 I, 21 I, 31 I, and 41 I can be reduced.

Also, although in the preferred embodiment of FIG. 74 , the dummy wires 15 I and the dummy wires 16 I are disposed so as to be mutually orthogonal and form a lattice in plan view, the respective dummy wires 15 I, 16 I, 17 I, and 18 I do not have to form a lattice in plan view and lengths and directions thereof may be changed freely.

Also, although with the above-described preferred embodiment, a mode in which the bonding wires 13 I are covered by the water-impermeable insulating film 19 I was described as an example, the water-impermeable insulating film 19 I may be omitted as shown in each of FIG. 79 to FIG. 82 as long as at least the ninth object for resolving the ninth issue is achieved.

Tenth Preferred Embodiment FIG. 83 to FIG. 94

By disclosure of a tenth preferred embodiment, a tenth issue concerning a tenth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Tenth Background Art

A resin sealed type semiconductor device has a structure in which a semiconductor chip is sealed together with a lead frame by a resin package. The lead frame is formed by punching out a metal thin plate and includes an island and a plurality of leads disposed at a periphery of the island. The semiconductor chip is die bonded onto the island. A plurality of pads are disposed on a top surface of the semiconductor chip, and between each pad and each lead, a wire for electrical connection is installed for electrical connection thereof.

In a case where a rear surface of the semiconductor chip and the island need to be connected electrically, a conductive bonding material is interposed between the semiconductor chip and the island. A solder paste is used most widely as the conductive bonding material.

(2) Tenth Issue

As a part of measures for environmental protection, making of semiconductor device Pb (lead) free is being examined recently. Making of an outer packaging portion of a semiconductor device Pb-free has been completed, and if a highly adhesive type Ag (silver) paste or solder having Bi (bismuth) or Zn (zinc) as a main component is adopted as the bonding material interposed between the semiconductor chip and the island, making of an interior of the semiconductor device Pb-free can be realized.

A lead solder, which is generally used as a bonding material, is used, for example, for a purpose of securing electrical conductivity by an ohmic bonding. A lead solder may also be used for a purpose where a high heat radiating property is to be secured but an ohmic bonding is not necessary.

Metal (solder) bonding is essential for realizing ohmic bonding of a semiconductor chip and an island. Meanwhile, in order to achieve the second purpose, a bonding material (paste) having a high heat radiating property must be adopted. For exhibition of a high heat radiating property, an amount of metal particles (for example, Ag) contained in the bonding material is increased. However, when the amount of metal particles is increased, an amount of epoxy resin or other organic component decreases and the bonding material decreases in adhesion property.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 13 of 27

Also, in a case where a solder having Bi or Zn as a main component is used as the bonding material, the solder forms dissimilar metal films with the semiconductor chip and with the island and these need to be increased in adhesive properties, thus leading to increase of the number of manufacturing steps and increase of manufacturing cost of the semiconductor device. Solders having Bi or Zn as a main component are thus still in a stage of evaluation around the world.

Thus, a tenth object of the present invention related to the tenth preferred embodiment is to provide a semiconductor device that enables electrical connection (ohmic connection) to be achieved between a rear surface of a semiconductor chip and an island even when a bonding material other than solder is used.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 83 is a schematic sectional view of a semiconductor device according to the tenth preferred embodiment of the present invention. FIG. 84 is a schematic plan view of the semiconductor device shown in FIG. 83 as viewed from a rear surface side and shows a state where illustration of a resin package is omitted.

The semiconductor device 1 J has a structure in which a semiconductor chip 2 J is sealed together with a lead frame 3 J by a resin package 4 J. The resin package 4 J is formed to a quadrilateral shape in plan view.

The lead frame 3 J includes an island 5 J disposed at a central portion of the semiconductor device 1 J and a plurality of (ten in the present preferred embodiment) leads 6 J disposed at a periphery of the island 5 J. The lead frame 3 J is formed, for example, by performing a punching process and a pressing process on a copper (Cu) thin plate.

The island 5 J integrally includes a main body portion 7 J of quadrilateral shape in plan view that has its center overlapped with a center of the resin package 4 J in plan view and has four sides extending parallel to the respective sides of the resin package 4 J, and suspending portions 8 J of quadrilateral shape in plan view that extend from two mutually opposite sides among the four sides of the main body portion 7 J to side surfaces of the resin package 4 J. As shown in FIG. 84 , the main body portion 7 J has formed therein a through-hole 9 J passing through its thickness direction. The through-hole 9 J is formed to a quadrilateral shape smaller than the semiconductor chip 2 J in plan view.

With respect to the main body portion 7 J of the island 5 J, the same number each of the leads 6 J are disposed at equal intervals at each of both sides of a direction orthogonal to a direction of extension of the suspending portions 8 J.

Each lead 6 J penetrates through a side surface of the resin package 4 J and a portion that is sealed by the resin package 4 J makes up an inner lead portion to which a top surface wire 12 J to be described later is connected and a portion exposed from the resin package 4 J makes up an outer lead portion for connection with a circuit board on which the semiconductor device 1 J is mounted.

The semiconductor chip 2 J is formed to a quadrilateral shape in plan view. An alloy film 11 J is coated onto an entirety of a rear surface of the semiconductor chip 2 J. The alloy film 11 J has a structure in which, for example, Au (gold) and Ni (nickel) are laminated in that order from the semiconductor chip 2 J side.

The semiconductor chip 2 J is disposed facing the island 5 J so that its rear surface (alloy film 11 J) faces the island 5 J. In this state, a peripheral portion of the through-hole 9 J in the island 5 J faces a peripheral edge portion of the rear surface of the semiconductor chip 2 J. A silver paste 10 J with an insulating property is interposed between the peripheral portion of the through-hole 9 J and the peripheral edge portion of the semiconductor chip 2 J. The rear surface of the semiconductor chip 2 J is thereby bonded (die bonded) to the island 5 J via the silver paste 10 J.

Pads (not shown) of the same number as the leads 6 J are formed on the top surface of the semiconductor chip 2 J in correspondence to the respective leads 6 J. One end of a top surface wire 12 J is bonded to each pad. The other end of each top surface wire 12 J is bonded to the upper surface of the lead 6 J corresponding to the pad. The respective pads are thereby electrically connected to the leads 6 J via the top surface wires 12 J.

As in the first preferred embodiment, in the semiconductor device 1 J, the entire top surface of the semiconductor chip 2 J, entire top surface and side surfaces of the island 5 J, the entire top surfaces of the leads 6 J, and the entire top surface wires 12 J are covered by an integral water-impermeable insulating film 18 J.

A plurality of rear surface wires 14 J are installed between the rear surface (alloy film 11 J) of the semiconductor chip 2 J and the island 5 J. Specifically, one end portion of each rear surface wire 14 J is bonded to a portion of the rear surface of the semiconductor chip 2 J that faces the through-hole 9 J. Each rear surface wire 14 J is inserted through the through-hole 9 J and the other end portion thereof is bonded to a rear surface of the island 5 J. The rear surface wires 14 J are, for example, disposed at equal intervals along respective sides of the through-hole 9 J of quadrilateral shape as shown in FIG. 84 . The rear surface of the semiconductor chip 2 J and the island 5 J are thereby connected electrically by the plurality of rear surface wires 14 J.

As described above, the semiconductor chip 2 J has its rear surface bonded to the island 5 J by the silver paste 10 J with the insulating property. At the sides of the island 5 J, the leads 6 J are disposed separatedly from the island 5 J. The top surface wires 12 J are installed between the pads formed on the top surface of the semiconductor chip 2 J and the leads 6 J. The pads and the leads 6 J are thereby connected electrically.

Also, the rear surface wires 14 J that electrically connect the semiconductor chip 2 J and the island 5 J are installed between the rear surface of the semiconductor chip 2 J and the island 5 J. Thus, even if the silver paste 10 J with the insulating property is used as the bonding material, the rear surface of the semiconductor chip 2 J and the island 5 J can be connected electrically via the rear surface wires 14 J. That is, even when a bonding material other than solder that contains Pb is used, electrical connection of rear surface of the semiconductor chip 2 J and the island 5 J can be achieved regardless of the electrical characteristics of the bonding material.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 14 of 27

The rear surface wires 14 J are made of copper. Copper is inexpensive in comparison to gold, which is widely used as wire material, and thus the rear surface wires 14 J can be reduced in material cost. Also, copper is high in electrical conductivity and thus enables reduction in electrical resistance between the semiconductor chip 2 J and the island 5 J.

Both the top surface wires 12 J and the rear surface wires 14 J are made of copper. The top surface wires 12 J and the rear surface wires 14 J can thus be formed by a wire bonder without changing a material set in the wire bonder. A manufacturing process of the semiconductor device 1 J can thus be simplified.

Also, the through-hole 9 J is formed to pass through the island 5 J in its thickness direction, and the rear surface wires 14 J are installed between the rear surface of the semiconductor chip 2 J and the island 5 J through the through-hole 9 J. The rear surface (alloy film 11 J) of the semiconductor chip 2 J is thereby exposed from the through-hole 9 J and electrical connection of the rear surface of the semiconductor chip 2 J and the island 5 J can be achieved by the rear surface wires 14 J being connected to the exposed portion. In this case, an area of a portion of the island 5 J that faces the rear surface of the semiconductor chip 2 J is necessarily made smaller than an area of the rear surface of the semiconductor chip 2 J and the silver paste 10 J with the insulating property is interposed just at facing portions of the semiconductor chip 2 J and the island 5 J. The silver paste 10 J is thus not used at the facing portions of the semiconductor chip 2 J and the through-hole 9 J and thus the silver paste 10 J can be reduced in usage amount. Consequently, the semiconductor chip 1 J can be reduced in material cost.

Also, the rear surface wires 14 J are disposed in plurality. Reliability of the electrical connection of the semiconductor chip 2 J and the island 5 J can thereby be improved.

FIG. 85 is a schematic sectional view of a first modification example of the semiconductor device shown in FIG. 83 . FIG. 86 is a schematic plan view of the semiconductor device shown in FIG. 85 as viewed from a rear surface side and shows a state where illustration of a resin package is omitted. In FIGS. 85 and 86 , portions corresponding to the respective portions shown in FIGS. 83 and 84 are provided with the same reference symbols as the reference symbols provided to the abovementioned respective portions. In the following description, points of difference of the structure shown in FIGS. 85 and 86 with respect to the structure shown in FIGS. 83 and 84 shall be described mainly and description of the portions provided with the same reference symbols as the respective portions shown in FIGS. 83 and 84 shall be omitted.

The semiconductor device 21 J shown in FIG. 85 has an island 22 J that differs in structure from the island 5 J shown in FIG. 83 .

The island 22 J integrally includes a main body portion 23 J of quadrilateral shape in plan view that has four sides extending parallel to the respective sides of the resin package 4 J, and suspending portions 24 J of quadrilateral shape in plan view that extend from two mutually opposite sides among the four sides of the main body portion 23 J to side surfaces of the resin package 4 J.

As shown in FIG. 86 , the main body portion 23 J has formed therein four through-holes 25 J that penetrate through its thickness direction. The four through-holes 25 J are disposed at equiangular intervals about a center of the island 22 J.

The semiconductor chip 2 J is disposed facing the island 22 J so that its rear surface (alloy film 11 J) faces the island 22 J. In this state, peripheral portions of the respective through-holes 25 J in the island 22 J face peripheral edge portions of the rear surface of the semiconductor chip 2 J. The silver paste 10 J with the insulating property is interposed between the peripheral portions of the through-holes 25 J and the peripheral edge portions of the semiconductor chip 2 J. The rear surface of the semiconductor chip 2 J is thereby bonded (die bonded) to the island 22 J via the silver paste 10 J.

A plurality of rear surface wires 14 J are installed between the rear surface (alloy film 11 J) of the semiconductor chip 2 J and the island 22 J. Specifically, one end portion of each rear surface wire 14 J is bonded to a portion of the rear surface of the semiconductor chip 2 J that faces a through-hole 25 J. Each rear surface wire 14 J is inserted through the through-hole 25 J and the other end thereof is bonded to a rear surface of the island 22 J. The rear surface wires 14 J are, for example, disposed at equal intervals along respective sides of each through-hole 25 J. The rear surface of the semiconductor chip 2 J and the island 22 J are thereby connected electrically via the plurality of rear surface wires 14 J.

The same effects as those of the semiconductor device 1 J shown in FIG. 83 can be obtained by the arrangement of the semiconductor device 21 J as well.

FIG. 87 is a schematic sectional view of a second modification example of the semiconductor device shown in FIG. 83 . FIG. 88 is a schematic plan view of the semiconductor device shown in FIG. 87 as viewed from a rear surface side and shows a state where illustration of a resin package is omitted. In FIGS. 87 and 88 , portions corresponding to the respective portions shown in FIGS. 83 and 84 are provided with the same reference symbols as the reference symbols provided to the abovementioned respective portions. In the following description, points of difference of the structure shown in FIGS. 87 and 88 with respect to the structure shown in FIGS. 83 and 84 shall be described mainly and description of the portions provided with the same reference symbols as the respective portions shown in FIGS. 83 and 84 shall be omitted.

The semiconductor device 31 J shown in FIG. 87 has an island 32 J that differs in structure from the island 5 J shown in FIG. 83 . Also, the semiconductor device 31 J and the semiconductor device 1 J differ in the structure for electrically connecting the rear surface of the semiconductor chip 2 J and the island 5 J or 32 J.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 15 of 27

The island 32 J integrally includes a main body portion 33 J of quadrilateral shape that has four sides extending parallel to the respective sides of the resin package 4 J and is formed to a smaller size than the semiconductor chip 2 J in plan view, and suspending portions 34 J of quadrilateral shape in plan view that extend from two mutually opposite sides among the four sides of the main body portion 33 J to side surfaces of the resin package 4 J.

The semiconductor chip 2 J is disposed facing the island 32 J so that its rear surface (alloy film 11 J) faces the island 32 J. In plan view, the island 32 J is smaller than the semiconductor chip 2 J and a rear surface 36 J of the semiconductor chip 2 J is exposed from a periphery of the island 32 J. That is, an area of an upper surface 35 J of the island 32 J that faces the semiconductor chip 2 J is smaller than an area of the rear surface 36 J of the semiconductor chip 2 J.

In this state, the silver paste 10 J with the insulating property is interposed between the upper surface 35 J of the island and the rear surface 36 J of the semiconductor chip 2 J. The rear surface 36 J of the semiconductor chip 2 J is thereby bonded (die bonded) to the upper surface 35 J of the island 32 J via the silver paste 10 J.

The plurality of rear surface wires 14 J are installed between the rear surface 36 J of the semiconductor chip 2 J and the island 32 J. Specifically, one end portion of each rear surface wire 14 J is bonded to the rear surface 36 J (alloy film 11 J) of the semiconductor chip 2 J that is exposed at the periphery of the island 32 J. Each rear surface wire 14 J loops around a side of the island 32 J, extends to a rear surface side of the island 32 J, and the other end portion thereof is bonded to the rear surface of the island 32 J. The rear surface wires 14 J are disposed at equal intervals along respective sides of the island 32 J. The rear surface 36 J of the semiconductor chip 2 J and the island 32 J are thereby connected electrically via the plurality of rear surface wires 14 J.

The same effects as those of the semiconductor device 1 J shown in FIG. 83 can be obtained by the arrangement of the semiconductor device 31 J as well.

FIG. 89 is a schematic sectional view of a third modification example of the semiconductor device shown in FIG. 83 . FIG. 90 is a schematic plan view of the semiconductor device shown in FIG. 89 as viewed from a rear surface side and shows a state where illustration of a resin package is omitted.

The semiconductor device 41 J is a so-called surface mounted type semiconductor device with which rear surfaces of an island and leads are exposed from a rear surface of a resin package. The semiconductor device 41 J has a structure in which a semiconductor chip 42 J is sealed together with a lead frame 43 J by a resin package 44 J. An outer shape of the semiconductor device 41 J is a flat, rectangular parallelepiped shape (in the present preferred embodiment, a hexahedron having a square shape in plan view).

The lead frame 43 J includes an island 45 J disposed at a central portion of the semiconductor device 1 J and a plurality of leads 46 J disposed at a periphery of the island 45 J. The lead frame 43 J is formed, for example, by performing a punching process and a pressing process on a copper thin plate.

The island 45 J integrally includes a main body portion 47 J of quadrilateral shape in plan view that has its center overlapped with a center of the resin package 44 J in plan view and has four sides extending parallel to the respective sides of the resin package 44 J, and suspending portions 48 J of quadrilateral shape in plan view that extend from two mutually opposite sides among the four sides of the main body portion 47 J to side surfaces of the resin package 44 J. The main body portion 47 J is formed to a smaller size than the semiconductor chip 42 J in plan view. Also, end surfaces of the respective suspending portions 48 J are flush with the side surfaces of the resin package 44 J and are exposed at the side surfaces.

Across an entire periphery of a peripheral edge portion of a rear surface of the island 45 J, a recess portion 49 J with a shape such that the island 45 J is dug in from its rear surface side is formed by performing a squeezing process from the rear surface side. The recess portion 49 J of such a shape may be formed, for example, by selectively etching the peripheral edge portion of the island 45 J from the rear surface side instead of squeezing.

Also, with the exception of the peripheral edge portion (recess portion 49 J), the rear surface of the island 45 J is exposed as a rear surface connection terminal at the rear surface of the resin package 44 J. For example, in a case where a central portion (portion exposed from the resin package 44 J) of the island 45 J has a thickness of 200 μm, the peripheral edge portion of the island 45 J has a thickness of 100 μm.

An equal number of the leads 46 J are disposed at each of positions facing the respective side surfaces of the island 45 J. At each of the positions facing the side surfaces of the island 45 J, the leads 46 J extend in a direction orthogonal to the facing side surface and are disposed at equal intervals in a direction parallel to the side surface.

At an end portion at the island 45 J side of a rear surface of each lead 46 J, a recess portion 50 J with a shape such that the lead 46 J is dug in from its rear surface side is formed by performing a squeezing process from the rear surface side.

With the exception of the edge portion (recess portion 50 J), the rear surface of the lead 46 J is exposed from the rear surface of the resin package 44 J. Also, aside surface of the lead 46 J opposite the island 45 J side is exposed from a side surface of the resin package 44 J. For example, in a case where a portion of the lead 46 J that is exposed from rear surface of the resin package 44 J has a thickness of 200 μm, the end portion at the island 45 J side of the lead 46 J (portion at which the recess portion 50 J is formed) has a thickness of 100 μm.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 16 of 27

The semiconductor chip 42 J is formed to a quadrilateral shape in plan view. An alloy film 52 J is coated onto the entire rear surface of the semiconductor chip 42 J. The alloy film 52 J has, for example, the same laminated structure as that of the alloy film 11 J shown in FIG. 83 .

The semiconductor chip 42 J is disposed facing the island 45 J so that its rear surface (alloy film 52 J) faces the island 45 J. In plan view, the island 45 J is smaller than the semiconductor chip 42 J and the rear surface (alloy film 52 J) of the semiconductor chip 2 J is exposed at a periphery of the island 45 J.

In this state, a silver paste 51 J with an insulating property is interposed between the entire upper surface of the island 45 J and the rear surface of the semiconductor chip 42 J. The rear surface of the semiconductor chip 42 J is thereby bonded (die bonded) to the upper surface of the island 45 J via the silver paste 51 J.

Pads (not shown) of the same number as the leads 46 J are formed on the top surface of the semiconductor chip 42 J in correspondence to the respective leads 46 J. One end of a top surface wire 54 J made of copper is bonded to each pad. The other end of each top surface wire 54 J is bonded to the upper surface of a lead 46 J. The respective pads are thereby electrically connected to the leads 46 J via the top surface wires 54 J.

A plurality of rear surface wires 55 J made of copper are installed between the semiconductor chip 42 J and the island 45 J. Specifically, one end portion of each rear surface wire 55 J is bonded to the rear surface (alloy film 52 J) of the semiconductor chip 42 J that is exposed at the periphery of the island 45 J. Each rear surface wire 55 J loops around a side of the island 45 J, extends to the rear surface side of the island 45 J, and the other end thereof is directed upward so as to form an arc and is bonded to a lower surface of the main body portion 47 J of the island 45 J inside the recess portion 49 J. The rear surface of the semiconductor chip 42 J and the island 45 J are thereby connected electrically by the plurality of rear surface wires 55 J. Also, the other end portion of each rear surface wire 55 J is formed so that a height of an apex portion (width in the thickness direction of the island 45 J) thereof with respect to the lower surface of the main body portion 47 J of the island 45 J inside the recess portion 49 J is, for example, 70 μm. Exposure of the rear surface wires 55 J to the rear surface side of the semiconductor device 41 J from the resin package 44 J can thereby be prevented.

The same effects as those of the semiconductor device 1 J shown in FIG. 83 can be obtained by the arrangement of the semiconductor device 41 J as well.

Although the tenth preferred embodiment of the present invention has been described above, the tenth preferred embodiment may also be modified as follows.

For example, although each of the alloy films 11 J and 52 J was described having the structure where Au and Ni are laminated in that order from the semiconductor chip 2 J or 42 J side, a laminated film having structure where Au, Ti (titanium), and Ni are laminated in that order from the semiconductor chip 2 J or 42 J side may be adopted instead or a laminated film having structure where Au, Ti, Ni, and Au are laminated in that order from the semiconductor chip 2 J or 42 J side may be adopted instead as the alloy film 11 J or 52 J.

Also, although with the above-described preferred embodiment, a mode in which the surface wires 12 J are covered by the water-impermeable insulating film 18 J was described as an example, the water-impermeable insulating film 18 J may be omitted as shown in each of FIG. 91 to FIG. 94 as long as at least the tenth object for resolving the tenth issue is achieved.

Eleventh Preferred Embodiment FIG. 95 to FIG. 105

By disclosure of an eleventh preferred embodiment, an eleventh issue concerning an eleventh background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Eleventh Background Art

From before, reduction in usage amounts of lead in semiconductor devices has been demanded from a standpoint of environmental impact.

With a semiconductor device, lead is used in external component materials used at an exterior of the device, such as an outer plating of outer leads in an SOP (small outline package) or a QFP (quad flat package), solder balls in a BGA (ball grid array), as well as in internal component materials used in an interior of the device, such as a bonding material between a semiconductor chip and a lead frame in an interior of a package.

In regard to external component materials, lead free conditions of a lead content of no more than a certain fixed proportion have been substantially attained through research on alternative materials. In contrast, for internal component materials, there are no materials that are suited as alternatives. Thus, a metal containing lead, for example, Pb-xSn-yAg (where x and y are positive numbers), etc., is used.

(2) Eleventh Issue

In a process of evaluating metal materials of various compositions as alternative materials for internal component materials, Bi, which is low in environmental impact, came to be noted as a choice for an alternative material. Bi meets, for example, melting point and bonding properties required of a bonding material used in the interior of a device and further meets various environmental impact characteristics.

However, a thermal expansion coefficient of Bi (approximately 13.4×10 −6 /° C.) is low in comparison to a thermal expansion coefficient (for example, approximately 28.5×10 −6 /° C.) of a generally used Pb-xSn-yAg. Thus, when performing reflow for mounting a semiconductor device, etc., a lead frame undergoes thermal expansion and becomes warped, a stress generated in a bonding material due to the warping of the lead frame may not be relaxed sufficiently by the bonding material. In this case, the stress that could not be relaxed may be applied to a semiconductor chip to cause the semiconductor chip to warp and when an amount of the warp is large, a crack (for example, a horizontal crack, vertical crack, etc.) may occur in the semiconductor chip.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 17 of 27

It may be possible to alleviate the warp amount of the semiconductor chip by increasing a thickness of the semiconductor chip or the lead frame. However, there is a problem in that a package main body becomes large when the thickness of the semiconductor chip or the lead frame is increased.

Also, it may be possible to alleviate the warp amount of the semiconductor chip by increasing a thickness of the bonding material. However, even if a usage amount of the bonding material is increased, the thickness of the bonding material decreases when the bonding material is pressed by a weight of the semiconductor chip. It is thus difficult to control the thickness of the bonding material to a desired thickness.

Further, a thermal conductivity (approximately 9 W/m·K) of Bi is low in comparison to a thermal conductivity (for example, approximately 35 W/m·K) of Pb-xSn-yAg. Thus, with a bonding material using Bi, a problem that heat generated by the semiconductor chip is not readily radiated arises.

Thus, an eleventh object of the present invention related to the eleventh preferred embodiment is to provide a semiconductor device with which a Bi-based material is used in a bonding material between a semiconductor chip and a lead frame to enable achievement of lead free conditions and yet a heat radiation property of the semiconductor chip can be secured while reducing a warp amount of the semiconductor chip due to thermal expansion of the lead frame.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 95 is a schematic bottom view of a semiconductor device according to the eleventh preferred embodiment of the present invention. FIG. 96 is a schematic sectional view of the semiconductor device according to the eleventh preferred embodiment of the present invention. FIG. 97 is an enlarged view of principal portions of a portion surrounded by a broken-line circle in FIG. 96 .

The semiconductor device 1 K is a semiconductor device to which a QFN (quad flat non-leaded) configuration is applied. The semiconductor device 1 K includes a semiconductor chip 2 K, a die pad 3 K on which the semiconductor chip 2 K is mounted, a plurality of electrode leads 4 K disposed at a periphery of the die pad 3 K, bonding wires 5 K electrically connecting the semiconductor chip 2 K and the electrode leads 4 K, and a resin package 6 K sealing the above components.

In the following description, the present preferred embodiment shall be described with a direction in which the semiconductor chip 2 K faces the die pad 3 K being a Z direction and a direction orthogonal to the Z direction being an X direction.

The semiconductor chip 2 K includes an Si substrate 7 K of quadrilateral shape in plan view.

The Si substrate 7 K has a thickness, for example, of 220 to 240 μm (preferably, approximately 230 μm). A multilayer wiring structure (not shown) arranged by laminating a plurality of wiring layers via interlayer insulating films is formed on a top surface 71 K of the Si substrate 7 K, and a topmost surface of the multilayer wiring structure is covered by a top surface protective film (not shown). A plurality of pad openings for exposing an uppermost wiring layer of the multilayer wiring structure are formed in the top surface protective film. A portion of the wiring layer is thereby exposed from each pad opening as an electrode pad 8 K of the semiconductor chip 2 K.

The uppermost wiring layer exposed as the electrode pads 8 K is made, for example, of a metal material containing Al (aluminum) and is specifically made of a metal material having Al as a main component (for example, an Al—Cu alloy, etc.).

Meanwhile, a rear metal 9 K is formed on a rear surface 72 K (surface facing the die pad 3 K) of the Si substrate 7 K.

As shown in FIG. 97 , the rear metal 9 K has a three-layer structure in which an Au layer 91 K, a Ni layer 92 K, and a Cu layer 93 K are laminated in that order from the Si substrate 7 K side. The Au layer 91 K can be put in ohmic contact enabling conduction of electricity with an Si semiconductor and contacts the rear surface 72 K of the Si substrate 7 K. The Ni layer 92 K is formed at the Si substrate 7 K side relative to the Cu layer 93 K, which makes up a topmost surface of the rear metal 9 K, and is a layer for preventing Si nodules, by which the Si in the Si substrate 7 K precipitates at the topmost surface of the rear metal 9 K.

The die pad 3 K and the plurality of electrode leads 4 K are formed of the same metal thin plate and are formed as a lead frame 10 K. The metal thin plate making up the lead frame 10 K is made of a Cu-based material that mainly contains Cu and is specifically made, for example, of a high-purity copper of no less than 99.9999% (6N) purity or no less than 99.99% (4N) purity or an alloy of Cu and a dissimilar metal (for example, a Cu—Fe—P alloy, etc.). The metal thin plate may also be made of an Fe-based material, such as 42 alloy (Fe-42% Ni). Also, the lead frame 10 K (metal thin plate) has a thickness, for example, of 190 to 210 μm (preferably, approximately 200 μm).

The die pad 3 K has a larger quadrilateral shape (for example, of 2.7 mm square in plan view) than the semiconductor chip 2 K in plan view. A top surface 31 K (surface facing the semiconductor chip 2 K) of the die pad 3 K is an uncovered surface that is not covered by a metal thin film by plating, sputtering, or other process and the Cu-based material that makes up lead frame 10 K is exposed across the entire top surface 31 K.

A plurality of Cu stud bumps 18 K are provided on the top surface 31 K of the die pad 31 K. In plan view, one Cu stud bump 18 K is disposed at each corner of the die pad 3 K and a total of four thereof are provided. Each Cu stud bump 18 K is formed by a known wire bonding method and has a humped shape in sectional view that integrally includes a base portion 181 K of relatively large diameter that contacts the top surface 31 K and a tip portion 182 K of relatively small diameter that projects from the base portion 181 K toward the semiconductor chip 2 K side.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 18 of 27

The semiconductor chip 2 K, in a state of being supported by the Cu stud bumps 18 K in a manner such that the rear metal 9 K contacts the tip portions 182 K of the Cu stud bumps 18 K, is bonded to the die pad 3 K by a bonding layer 11 K being interposed between the rear surface 72 K of the Si substrate 7 K and the top surface 31 K of the die pad 3 K.

The bonding layer 11 K includes a Bi-based material layer 111 K as a relatively thick main layer and Cu—Sn alloy layers 112 K, 113 K, and 114 K as relatively thin sub layers.

The Bi-based material layer 111 K contains Bi as a main component and may contain Sn, Zn, etc., of amounts that do not influence physical properties of Bi as sub components.

Each of the Cu—Sn alloy layers 112 K, 113 K, and 114 K is made of an alloy of Cu and Sn, which is a dissimilar metal differing from Cu, and contains Cu as a main component.

The Cu—Sn alloy layer 112 K at the semiconductor chip 2 K side is formed near and across an entire range of an interface of the bonding layer 11 K with the Cu layer 93 K of the rear metal 9 K. The Cu—Sn alloy layer 112 K thus contacts the Cu layer 93 K of the rear metal 9 K. The Cu—Sn alloy layer 112 K has, for example, in the Z direction, a laminated structure expressed as Cu6Sn5/Cu3Sn from the Bi-based material layer 111 K side toward the semiconductor chip 2 K side.

Meanwhile, the Cu—Sn alloy layer 113 K at the die pad 3 K side is formed near and across an entire range of an interface of the bonding layer 11 K with the top surface 31 K of the die pad 3 K. The Cu—Sn alloy layer 113 K thus contacts the top surface 31 K of the die pad 31 K. The Cu—Sn alloy layer 113 K has, for example, in the Z direction, a laminated structure expressed as Cu6Sn5/Cu3Sn from the Bi-based material layer 111 K side toward the die pad 3 K side.

Near the interface of the bonding layer 11 K with the top surface 31 K of the die pad 3 K and near the interface of the bonding layer 11 K with the Cu layer 93 K of the rear metal 9 K, the Cu—Sn alloy layers 112 K and 113 K may be formed across partial ranges of the respective interfaces.

The Cu—Sn alloy layer 114 K is formed so as to cover the Cu stud bumps 18 K.

The Bi-based material layer 111 K and the Cu—Sn alloy layers 112 K and 113 K form, between the top surface 31 K of the die pad 3 K and the Cu layer 93 K of the rear metal 9 K, a three-layer structure (Cu—Sn alloy layer 112 K/Bi-based material layer 111 K/Cu—Sn alloy layer 113 K) in which the Bi-based material layer 111 K is sandwiched by the Cu—Sn alloy layers 112 K and 113 K from respective sides in Z direction.

The above-described bonding layer 11 K has a melting point, for example, of 260 to 280° C. and preferably 265 to 275° C. Also, in a state where the semiconductor chip 2 K and the die pad 3 K are bonded, a total thickness T of the bonding layer 11 K (total of a thickness of the Bi-based material layer 111 K and thicknesses of the Cu—Sn alloy layers 112 K and 113 K) is, for example, 30.5 to 50 μm. In regard to the thicknesses of the respective layers, for example, the thickness of the Bi-based material layer 111 K is 30 to 50 μm and the thickness of Cu—Sn alloy layers 112 K and 113 K is 0.5 to 3 μm.

A rear surface 32 K (surface of mounting onto a wiring circuit board) of the die pad 3 K is exposed from the resin package 6 K. The exposed rear surface 32 K has formed thereon a rear surface plating layer 12 K made of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag).

The electrode leads 4 K are disposed at the periphery of the die pad 3 K with the same number thereof being disposed at both sides in respective directions orthogonal to respective side surfaces of the die pad 3 K. The electrode leads 4 K that face each side surface of the die pad 3 K are disposed at equal intervals in a direction parallel to the facing side surface. A length of each electrode lead 4 A in the direction of facing the die pad 3 K is, for example, 440 to 460 μm (preferably, approximately 450 μm). Atop surface 41 K (surface to which the bonding wire 5 K is connected) of each electrode lead 4 K is an uncovered surface that is not covered by a metal thin film by plating, sputtering, or other process and the Cu-based material that makes up lead frame 10 K is exposed across the entire top surface 41 K.

Meanwhile, a rear surface 42 K (surface of mounting onto a wiring circuit board) of each electrode lead 4 K is exposed from the resin package 6 K. A rear surface plating layer 13 K made, for example, of a metal material, such as tin (Sn), tin-silver alloy (Sn—Ag), is formed on the exposed rear surface 42 K.

Each bonding wire 5 K is made of copper (for example, a high-purity copper of no less than 99.9999% (6N) purity or no less than 99.99% (4N) purity that may contain a minute amount of impurity). Each bonding wire 5 K connects a single electrode pad 8 K and a single electrode lead 4 K in a one-to-one manner.

As in the first preferred embodiment, in the semiconductor device 1 K, the entire top surface and side surfaces of the semiconductor chip 2 K, the entire top surface 31 K and side surfaces of the die pad 3 K, the entire top surfaces 41 K and side surfaces inside the resin package 6 K of the electrode leads 4 K, and the entire bonding wires 5 K are covered by an integral water-impermeable insulating film 25 K.

As the resin package 6 K, a known material, such as an epoxy resin, may be applied. The resin package 6 K makes up an outer shape of the semiconductor device 1 K and is formed to a substantially rectangular parallelepiped shape. In terms of size, the resin package 6 K has a planar size, for example, of approximately 4 mm square and a thickness, for example, of 0.80 to 0.90 mm and preferably, approximately 0.85 mm.

FIG. 98A to FIG. 98D are schematic sectional views for describing a method for manufacturing the semiconductor device shown in FIG. 2 in order of process.

To manufacture the semiconductor device 1 K, the rear metal 9 K is formed by successively laminating the Au layer 91 K, the Ni layer 92 K, and the Cu layer 93 K on the rear surface 72 K of the Si substrate 7 K of the semiconductor chip 2 K by a plating method, sputter method, etc., for example, as shown in FIG. 98A .

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 19 of 27

Meanwhile, as shown in FIG. 98A , the lead frame 10 K that includes a plurality of units each integrally having a die pad 3 K and electrode leads 4 F is prepared. In FIG. 98A to FIG. 98E , an entire view of the lead frame 10 K is abbreviated and the die pad 3 K and electrode leads 4 K of just a single unit necessary for mounting a single semiconductor chip 2 K are shown.

Next, as shown in FIG. 98B , the plurality of Cu stud bumps 18 K are formed on the top surface 31 K of the die pad 3 K by a known wire bonding method. In succession, the bonding paste 14 K made of the Bi-based material that contains Sn is coated onto the top surface 31 K of the die pad 3 K.

An Sn content of the bonding paste 14 K is, for example, preferably an amount such that the entire amount diffuses among the Cu in the Cu layer 93 K of the rear metal 9 K and the top surface 31 K of the die pad 3 K and is, for example, no more than 4 wt %, preferably, 1 to 3 wt %, and more preferably, 1.5 to 2.5 wt %.

After coating of the bonding paste 14 K, the bonding paste 14 K is sandwiched by the semiconductor chip 2 K and the die pad 3 K so that the Cu layer 93 K of the rear metal 9 K contacts the tip portions 182 K of the Cu stud bumps 18 K and the bonding paste 14 K as shown in FIG. 98C . In succession, reflow (heat treatment) is executed, for example, at 250 to 260° C.

The Sn in the bonding paste 14 K is thereby made to react respectively with the Cu in the Cu layer 93 K of the rear metal 9 K, the Cu in the top surface 31 K of the die pad 3 K, and the Cu in the Cu stud bumps 18 K to form the Cu—Sn alloy layers 112 K and 113 K near the Cu layer 93 K and the top surface 31 K as shown in FIG. 98D . Also, the Cu stud bumps 18 K are covered by the Cu—Sn alloy layer 114 K. Meanwhile, the Bi in the bonding paste 14 K hardly reacts with Cu and thus remains as the Bi-based material layer 111 K sandwiched between the Cu—Sn alloy layers 112 K and 113 K.

Thereafter, the respective electrode pads 8 K of all semiconductor chips 2 K and the electrode leads 4 K corresponding to the respective electrode pads 8 K are connected by the bonding wires 5 K.

After all of the wire bonding ends, the water-impermeable insulating film 25 K is formed by the same method as that of FIG. 4D . After the forming of the water-impermeable insulating film 25 K, the lead frame 10 K is set in a forming mold and all semiconductor chips 2 K are sealed in a batch together with the lead frame 10 K by the resin package 6 K. Rear surface plating layers 12 K and 13 K are then formed on the rear surfaces 32 K of the die pads 3 K and the rear surfaces 42 K of the electrode leads 4 K that are exposed from the resin package 6 K. Lastly, a dicing saw is used to cut the lead frame 10 K together with the resin package 6 K to sizes of the respective semiconductor devices 1 K and the individual semiconductor devices 1 K one of which is shown in FIG. 96 are thereby obtained.

As described above, with the semiconductor device 1 K, the Si substrate 7 K is supported by the Cu stud bumps 18 K and thus a distance between the die pad 3 K and the semiconductor chip 2 K can be maintained at least at the height of the Cu stud bumps 18 K. Thus, by suitable adjustment of the height of the stud bumps 18 K, the bonding layer 11 K having the total thickness T can be interposed between the die pad 3 K and the semiconductor chip 2 K. Consequently, stress due to differences in the linear expansion coefficients among the Si substrate 7 K, the bonding layer 11 K, and the lead frame 10 K can be relaxed adequately. A warping amount of the Si substrate 7 K (semiconductor chip 2 K) can thus be reduced. Also, occurrence of crack in the Si substrate 7 K can be prevented. Also, there is no need to make the thicknesses of the Si substrate 7 K and the lead frame 10 K large and thus a package main body of the semiconductor device 1 K does not become large.

Further, a thermal conductive property between the lead frame 10 K and the Si substrate 7 K can be improved because the Cu stud bumps 18 K make up a spacer that supports the Si substrate 7 K and thermal conductivity (approximately 398 W/m·K) of Cu is extremely large in comparison to thermal conductivity (approximately 9 W/m·K) of Bi. Heat generated at the semiconductor chip 2 K can thus be released to the lead frame 10 K via the Cu stud bumps 18 K. An adequate heat radiation property can thus be secured for the semiconductor chip 2 K.

Also, four Cu stud bumps 18 K are provided and the Si substrate 7 K can thus be supported at four points. The semiconductor chip 2 K can thus be stabilized on the Cu stud bumps 18 K so as not to tilt with respect to the top surface 31 K of the die pad 3 K. A distance between the lead frame 10 K and the semiconductor chip 2 K can thus be made substantially uniform in magnitude. Consequently, the bonding layer 11 K is made uniform in linear expansion coefficient in the Z direction so that biasing of stress in the bonding layer 11 K can be suppressed and stress can be relaxed as a whole. Also, the heat generated at the semiconductor chip 2 K can be released using the four Cu stud bumps 18 K and the heat radiation property of the semiconductor chip 2 K can thus be improved further.

Also, when the lead frame 10 K undergoes thermal expansion, the heat of the lead frame 10 K is transmitted to the Si substrate 7 K via the Cu stud bumps 18 K. Thus, during reflow performed in mounting of the semiconductor device 1 K, the Si substrate 7 K can be made to undergo thermal expansion by the heat transmitted from the lead frame 10 K. Consequently, a difference between a thermal expansion amount of the lead frame 10 K and a thermal expansion amount of the Si substrate 7 K can be made small and the Si substrate 7 K can thus be reduced in warp amount.

Also, as the material of a lead frame, for example, an Fe-based material, such as 42 alloy (Fe-42% Ni), is known besides Cu of the lead frame 10 K. A thermal expansion coefficient of 42 alloy is approximately 4.4 to 7.0×10 −6 /° C. With a lead frame made from 42 alloy, the thermal expansion amount is less than the lead frame 10 K made of Cu (with a thermal expansion coefficient of approximately 16.7×10 −6 /° C.) and a warp amount of the lead frame can thereby be made small. However, in a case where 42 alloy is used, the cost is higher and the heat radiation property decreases in comparison to a case where Cu is used.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 20 of 27

In contrast, with the semiconductor device 1 K, the stress due to warping of the lead frame 10 K can be relaxed adequately by the bonding layer 11 K even in the case of the lead frame 10 K made of Cu. Cu can thus be used without any problem as the material of the lead frame 10 K to maintain the cost and the heat radiation property.

Also, in the manufacturing process described above, the bonding paste 14 K coated onto the top surface 31 K of the die pad 3 K is sandwiched by the semiconductor chip 2 K and the die pad 3 K so as to contact the Cu layer 93 K of the rear metal 9 K. Thereafter, the bonding layer 11 K, having the Bi-based material layer 111 K and the Cu—Sn alloy layers 112 K, 113 K, and 114 K, is formed by execution of reflow (heat treatment).

In forming the bonding layer 11 K, the components (Bi-based material and Sn) in the bonding paste 14 K do not come in contact with metal elements other than Cu and further, the Cu—Sn alloy layers 112 K and 113 K are formed at respective sides of the Bi-based material layer 111 K in the directions of facing the semiconductor chip 2 K and the die pad 3 K.

Diffusion of an inhibitory metal element, such as the Au in the Au layer 91 K of the rear metal 9 K, the Ni in the Ni layer 92 K, that may degrade the characteristics of the Bi-based material layer 111 K, into the Bi-based material layer 111 K can thus be prevented. Consequently, forming of an intermetallic compound of Bi and an abovementioned inhibitory metal element or forming of a eutectic composition of Bi and an abovementioned inhibitory metal element can be prevented. A temperature cycle resistance of the bonding layer 11 K can thus be improved and a melting point of the bonding layer 11 K can be maintained at a high level.

Meanwhile, although the Bi-based material layer 111 K contacts the Cu—Sn alloy layers 112 K, 113 K, and 114 K, Cu hardly reacts with Bi and there is hardly any possibility of lowering of the melting point and degradation of the temperature cycle resistance of the bonding layer 11 K due to mutual contact of these layers. Also, the contact of the Si substrate 7 K and the Cu stud bumps 18 K is contact of the same metal species of the Cu layer 93 K and the Cu stud bumps 18 K, and influences (for example, increased resistance of the Cu stud bumps 18 K, erosion of the Cu stud bumps 18 K, etc.) due to contact of the Si substrate 7 K and the Cu stud bumps 18 K can be reduced.

Also, the making of the bonding layer 111 K lead free can be achieved because the bonding layer 11 K is made of the Bi-based material layer 111 K and the Cu—Sn alloy layers 112 K, 113 K, and 114 K.

Also, the Cu—Sn alloy is not a hard, brittle metal such as a Bi—Au alloy, Bi—Ag alloy, but is a high-strength metal. The semiconductor chip 2 K and the lead frame 10 K can thus be improved in strength of bonding with the bonding layer 11 K by the Cu—Sn alloy layers 12 K and 113 K.

Also, the thermal conductivity of Sn is approximately 73 W/m·K and high in comparison to the thermal conductivity of Bi (approximately 90 W/m·K). The thermal conductivity of the bonding layer 11 K can thus be improved in comparison to a case where the bonding layer 11 K is made of only Bi. Consequently, the heat radiation property of the semiconductor chip 2 K can be improved further.

Also, the Au layer 91 K is in contact with the rear surface 72 K of the Si substrate 7 K and the Cu layer 93 K and the Si substrate 7 K can thus be made electrically continuous via the Au layer 91 K. The Si substrate 7 K and the die pad 3 K can thereby be connected electrically.

Also, both the top surface 31 K of the die pad 3 K and the top surfaces 41 K of the electrode leads 4 K are uncovered surfaces that are not covered by a metal thin film by plating, sputtering, or other process, and thus there is no need to perform plating, sputtering or other process on the lead frame 10 K in manufacturing the semiconductor device 1 K and the cost can thus be reduced.

Although the eleventh preferred embodiment of the present invention has been described above, the eleventh preferred embodiment may also be modified as follows.

For example, although a QFN type semiconductor device was taken up in the preferred embodiment, the present invention may also be applied to semiconductor devices of other package types, such as the QFP (quad flat package), SOP (small outline package).

Also, the number of Cu stud bumps 18 K may be one to three or may be no less than five. A larger number of stud bumps enables the usage amount of the bonding paste 14 K to be reduced further, thereby enabling reduction in cost and further improvement in the heat radiation property.

Also, for example, the Cu spacer that supports the Si substrate 7 K may be Cu wirings 19 K, each being formed by forming a ball bond (first bond) of a Cu wire on the top surface 31 K of the die pad 3 K by a wire bonding method, then leading the Cu wire to form a ring, bonding the side opposite the ball bond to the top surface 31 K (second bond), and breaking the Cu wire from the position of the second bond.

Also, for example, the sub layers of the bonding layer 11 K do not have to be the Cu—Sn alloy layers 112 K, 113 K, and 114 K and may, for example, be Cu—Zn alloy layers made of an alloy of Cu and Zn (with a thermal conductivity of 120 W/m·K), which is a dissimilar metal that differs from Cu, and containing Cu as a main component.

Also, for example, the top surface of the lead frame 10 K (the top surface 31 K of the die pad 3 K and the top surfaces 41 K of the electrode leads 4 K) do not need to be uncovered surfaces and a cover layer 15 K may be formed by a plating or sputtering process as shown in FIG. 100 .

In this case, the Cu must be exposed at the topmost surface of the lead frame 10 K as at the rear surface 72 K of the Si substrate 7 K.

For example, on the top surface 31 K of the die pad 3 K, the cover layer 15 K has a two-layer structure in which an Ag layer 16 K and a Cu layer 17 K are laminated successively from the die pad 3 K side as shown in FIG. 101A . By laminating the Cu layer 17 K above the Ag layer 16 K, Cu can be exposed over the entire surface (top surface 31 K) of the lead frame 10 K facing the semiconductor chip 2 K.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 21 of 27

Meanwhile, on the top surfaces 41 K of the electrode leads 4 K, the cover layer 15 K has a single-layer structure with which only an Ag layer 16 K is formed as shown in FIG. 101B . Ag can thereby be exposed over the entire surfaces of connection with the bonding wires 5 K. Thus, not only Cu wires but Au wires and other various wires may be used as the bonding wires 5 K to be connected to the electrode leads 4 K.

Also, although the rear metal 9 K was described as having the three-layer structure in which one layer each of the Au layer 91 K, the Ni layer 92 K, and the Cu layer 93 K are laminated, it is not limited thereto, and at least one type among the above layers may be laminated in plurality. In this case, the plurality of layers may be laminated continuously or a layer of another type may be interposed between the plurality of layers.

Also, the rear metal 9 K may include layers differing from an Au layer, Ni layer, or Cu layer. For example, an Ag layer or a Ti layer may be included. A Ti layer can be put in ohmic contact with a Si semiconductor and may thus be applied in place of the Au layer 91 K.

Also, for example, the rear metal 19 K and the tip portions 182 K of the Cu stud bumps 18 K may be separated as shown in FIG. 102 . In this case, the total thickness of the bonding layer 11 K is greater than the height of the Cu stud bumps 18 K in the state where the semiconductor chip 2 K and the die pad 3 K are bonded. The linear expansion of the bonding layer 11 K in the Z direction can thus be increased and the linear expansion of the bonding layer 11 K in the X direction can be suppressed. The stress applied to the semiconductor chip 2 K can thus be relaxed effectively.

Also, although with the above-described preferred embodiment, a mode in which the bonding wires 5 K are covered by the water-impermeable insulating film 25 K was described as an example, the water-impermeable insulating film 25 K may be omitted as shown in each of FIGS. 103 to 105 as long as at least the eleventh object for resolving the eleventh issue is achieved.

Twelfth Preferred Embodiment FIG. 106 to FIG. 156

By disclosure of a twelfth preferred embodiment, a twelfth issue concerning a twelfth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Twelfth Background Art

(2) Twelfth Issue

However, an FAB formed on a tip of a copper wire is harder than an FAB formed on a tip of a gold wire, and thus if a copper wire is bonded to a pad under the same conditions (magnitudes of load and ultrasonic transducer drive current, etc.) as those for a gold wire, satisfactory bonding of the copper wire and the pad cannot be obtained. Presently, conditions that enable satisfactory bonding of a copper wire and a pad to be achieved are not clear and replacement of gold wires by copper wires is yet to take place.

Thus, a twelfth object of the present invention related to the twelfth preferred embodiment is to provide a wire bonding method that enables satisfactory bonding of a copper wire to a pad to be achieved.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 106 is a schematic sectional view of a semiconductor device according to the twelfth preferred embodiment of the present invention. FIG. 107 is a schematic bottom view of the semiconductor device shown in FIG. 106 .

The semiconductor device 1 L is a semiconductor device to which a QFN (quad flat non-leaded package) configuration is applied and has a structure in which a semiconductor chip 2 L is sealed together with a die pad 3 L, leads 4 L, and copper wires 5 L by a resin package 6 L. An outer shape of the semiconductor device 1 L (resin package 6 L) is a flat, rectangular parallelepiped shape.

In the present preferred embodiment, the outer shape of the semiconductor device 1 L is a hexahedron having a square shape of 4 mm square as a planar shape and a thickness of 0.85 mm, and dimensions of respective portions of the semiconductor device 1 L cited below make up an example in the case where the semiconductor device 1 L has the above outer dimensions.

The semiconductor chip 2 L has a square shape of 2.3 mm in plan view. The semiconductor chip 2 L has a thickness of 0.23 mm. A plurality of pads 7 L are disposed at peripheral edge portions of a top surface of the semiconductor chip 2 L. Each pad 7 L is electrically connected to a circuit built into the semiconductor chip 2 L. A rear metal 8 L made of a metal layer of Au, Ni (nickel), Ag (silver), etc., is formed on a rear surface of the semiconductor chip 2 L.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 22 of 27

The die pad 3 L and the leads 4 L are formed by punching out a metal thin plate (for example, a copper thin plate). The metal thin plate (die pad 3 or lead 4 L) has a thickness of 0.2 mm. A plating layer 9 L made of Ag is formed on top surfaces of the die pad 3 L and leads 4 L.

The die pad 3 L has a square shape of 2.7 mm in plan view and is disposed at a central portion of the semiconductor device 1 L so that its respective side surfaces are parallel to side surfaces of the semiconductor device 1 L.

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface side across an entire periphery of a peripheral edge portion of the rear surface of the die pad 3 L. The resin package 6 L enters the recess. The peripheral edge portion of the die pad 3 L is thereby sandwiched from above and below by the resin package 6 L and prevention of fall-off (retaining) of the die pad 3 L with respect to the resin package 6 L is thereby achieved.

Also, with the exception of the peripheral edge portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of the die pad 3 L is exposed from a rear surface of the resin package 6 L.

An equal number of (for example, nine) leads 4 L are disposed at each of positions facing the respective side surfaces of the die pad 3 L. At each of the positions facing the side surfaces of the die pad 3 L, the leads 4 L extend in a direction orthogonal to the facing side surface and are disposed at equal intervals in a direction parallel to the side surface. A longitudinal direction length of each lead 4 L is 0.45 mm. Also, an interval between the die pad 3 L and the lead 4 L is 0.2 mm.

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface side at a die pad 3 L side end portion of the rear surface of each lead 4 L. The resin package 6 L enters the recess. The die pad 3 L side end portion of the lead 4 L is thereby sandwiched from above and below by the resin package 6 L and prevention of fall-off (retaining) of the lead 4 L with respect to the resin package 6 L is thereby achieved.

With the exception of the die pad 3 L side end portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of each lead 4 L is exposed from a rear surface of the resin package 6 L. Also, a side surface of the lead 4 L facing the die pad 3 L side is exposed from a side surface of the resin package 6 L.

A plating layer 10 L formed of solder is formed on portions of the rear surfaces of the die pad 3 L and leads 4 L that are exposed from the resin package 6 L.

With its top surface with the pads 7 L disposed thereon facing upward, the semiconductor chip 2 L has its rear surface bonded via a bonding material 11 L to the top surface (plating layer 10 L) of the die pad 3 L. For example, a solder paste is used as the bonding material 11 L. The bonding material 11 L has a thickness of 0.02 mm.

In a case where electrical connection of the semiconductor chip 2 L and the die pad 3 L is unnecessary, the rear metal 8 L may be omitted and the rear surface of the semiconductor chip 2 L may be bonded to the top surface of the die pad 3 L via a bonding material made of silver paste or other insulating paste. In this case, the planar size of the semiconductor chip 2 L is 2.3 mm square. Also, the plating layer 9 L on the top surface of the die pad 3 L may be omitted.

The copper wires 5 L are made, for example, of copper with a purity of no less than 99.99%. One end of each copper wire 5 L is bonded to a pad 7 L of the semiconductor chip 2 L. The other end of the copper wire 5 L is bonded to the top surface of a lead 4 L. The copper wire 5 L is installed so as to form an arch-shaped loop between the semiconductor chip 2 L and the lead 4 L. A height difference between an apex portion of the loop of the copper wire 5 L and the top surface of the semiconductor chip 2 L is 0.16 mm.

As in the first preferred embodiment, in the semiconductor device 1 L, the entire top surface and side surfaces of the semiconductor chip 2 L, the entire top surface and side surfaces of the die pad 3 L, entire top surfaces of the leads 4 L, and the entire copper wires 5 L are covered by an integral water-impermeable insulating film 25 L.

FIG. 108 is an enlarged view of a portion surrounded by broken lines shown in FIG. 106 .

Each pad 7 L is made of a metal that contains Al and is formed on an uppermost interlayer insulating film 12 L of the semiconductor chip 2 L. A top surface protective film 13 L is formed on the interlayer insulating film 12 L. The pad 7 L has its peripheral edge portion covered by the top surface protective film 13 L and its central portion is exposed via a pad opening 14 L formed in the top surface protective film 13 L.

The copper wire 5 L is bonded to the central portion of the pad 7 L exposed from the top surface protective film 13 L. As shall be described below, the copper wire 5 L has an FAB formed at its tip and the FAB is pressed against and thereby bonded to the pad 7 L. In this process, the FAB deforms to form a first ball portion 15 L with a stepped disk shape at the portion of bonding of the copper wire 5 L with the pad 7 L. Also, at a periphery of the first ball portion 15 L, the material of the pad 7 L juts out gradually from below the first ball portion 15 L so as to form a jutting portion 16 L without it being lifted greatly from the top surface of the pad 7 L.

For example, in a case where the copper wire 5 L has a wire diameter of 25 μm, an intended diameter of the first ball portion 15 L (designed diameter of the first ball portion 15 L) is 74 to 76 μm and an intended thickness of the first ball portion 15 L (designed thickness of the first ball portion 15 L) is 17 to 18 μm.

FIG. 109A to FIG. 109D are schematic sectional views of states in a middle of manufacture (middle of wire bonding) of the semiconductor device shown in FIG. 106 .

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 23 of 27

The copper wires 5 L are installed across the semiconductor chip 2 L and the leads 4 L by a wire bonder in a state where the die pad 3 L and the leads 4 L are connected to a frame (not shown) that surrounds these components, that is, in a state where the die pad 3 L and leads 4 L make up a lead frame.

The wire bonder includes a capillary C. As shown in FIG. 109A , the capillary C has a substantially cylindrical shape with a wire insertion hole 41 L formed along a central axis. The copper wire 5 L is inserted through the wire insertion hole 41 L and fed out from a tip (lower end) of the wire insertion hole 41 L.

A chamfer 42 L of truncated conical shape that is in communication with the wire insertion hole 41 L is formed below the wire insertion hole 41 L at a tip portion of the capillary C. Also, the tip portion of the capillary C has a face 43 L that is continuous with a lower end edge of the chamfer 42 L and is a surface that faces a pad 7 L and a lead 4 L during bonding (during wire bonding) of the copper wire 5 L to these components. An outer side of the face 43 L is gradually inclined upwardly with respect to a plane orthogonal to the central axis of the capillary C.

First, as shown in FIG. 109A , the capillary C is moved to a position directly above the pad 7 L. Next, in a state where a tip of the copper wire 5 L is positioned at the chamfer 42 L, a current is applied to a tip portion of the copper wire 5 L and an FAB 44 is thereby formed at the tip portion. The value and application time of the current are set suitably in accordance with the wire diameter of the copper wire 5 L and an intended diameter of the FAB 44 (designed diameter of the FAB 44 ). A portion of the FAB 44 protrudes below the chamfer 42 L.

Thereafter, as shown in FIG. 109B , the capillary C is lowered toward the pad 7 L and the FAB 44 is pressed against the pad 7 L by the capillary C. In this process, a load is applied to the FAB 44 by the capillary C and ultrasonic vibration, emitted from an ultrasonic transducer (not shown) provided in the capillary C, is applied to the FAB 44 .

FIG. 110 is a graph of changes with time of the load applied to the FAB and a driving current applied to the ultrasonic transducer during the bonding of the FAB to the pad.

Specifically, as shown in FIG. 110 , a relatively large initial load P 1 is applied from the capillary C to the FAB 44 from a time T 1 at which the FAB 44 contacts the pad 7 L to a time T 2 after elapse of a predetermined time period. The predetermined time period is set to 3 msec. Also, the initial load P 1 is set based on a value obtained by multiplying an intended bonding area of the first ball portion 15 L with respect to the pad 7 L (designed bonding area of the first ball portion 15 L with respect to the pad 7 L) by a fixed factor (for example, 28786 in a case where the unit of the initial load P 1 is g and the unit of the bonding area is mm 2 ). From the time T 2 onward, the load applied to the FAB 44 from the capillary C is lowered and a relatively small load P 2 is applied to the FAB 44 . The load P 2 is applied continuously until a time T 4 at which the capillary C is raised.

Meanwhile, a drive current of a relatively small value U 1 is applied to the ultrasonic transducer from before the time T 1 at which the FAB 44 contacts the pad 7 L. The drive current value U 1 is set to less than 30 mA.

Then, from the time T 1 at which the FAB 44 contacts the pad 7 L to a time T 3 , the value of the drive current applied to the ultrasonic transducer is raised at a fixed rate of change (monotonously) from the value U 1 to a relatively large value U 2 . The rate of change is set to no more than 21 mA/msec. Also, the value U 2 of the drive current that is applied to the ultrasonic transducer in a final stage is set so that a value obtained by dividing the value U 2 by the intended bonding area of the first ball portion 15 L is no more than 0.0197 mA/μm 2 . Further, the drive current values U 1 and U 2 are set so that an integrated value of the drive current applied to the ultrasonic transducer during the predetermined time period in which the initial load is applied to the FAB 44 is no more than 146 mA·msec. From the time T 3 onward until the time T 4 , the drive current of the value U 2 continues to be applied to the ultrasonic transducer.

Consequently, the FAB 44 deforms along the shapes of the chamfer 42 L and the face 43 L of the capillary C, and the first ball portion 15 L with a stepped disk shape is formed on the pad 7 L with the jutting portion 16 L being formed along its periphery as shown in FIG. 108 . Bonding (first bonding) of the copper wire 5 L with the pad 7 L is thereby achieved.

When the time T 4 arrives upon elapse of a bonding time determined in advance from the time T 1 , the capillary C separates upwardly from the pad 7 L. Thereafter, the capillary C is moved obliquely downward toward the top surface of the lead 4 L. Then, as shown in FIG. 109C , the drive current is applied to the ultrasonic transducer, and while ultrasonic vibration is being applied to the capillary C, the copper wire 5 L is pressed against the top surface of the lead 4 L by the capillary C and then broken. A stitch portion with a wedge shape in side view that is made up of the other end portion of the copper wire 5 L is thereby formed on the top surface of the lead 4 L and the bonding (second bonding) of the copper wire with respect to the lead 4 L is thereby achieved.

Thereafter, the processes shown in FIG. 109A to FIG. 109C are performed on another pad 7 L and the corresponding lead 4 L. By the processes shown in FIG. 109A to FIG. 109C then being repeated, copper wires 5 L are installed across all pads 7 L of the semiconductor chip 2 L and the leads 4 L as shown in FIG. 109D . After the end of all of the wire bonding, the water-impermeable insulating film 25 L is formed by the same method as that of FIG. 4D .

FIG. 111 is a graph of a relationship between the area of bonding of a first ball portion to a pad and the initial load.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 24 of 27

The following tests 1 to 4 were performed to examine relationships between the area of bonding of a first ball portion 15 L to a pad 7 L and the initial load.

(1) Test 1

A 45 μm FAB 44 was formed at a tip of a copper wire 5 L of 25 μm wire diameter, a capillary C was lowered toward a pad 7 L, and the FAB 44 was pressed against the pad 7 L to form a first ball portion 15 L on the pad 7 L by deformation of the FAB 44 . The magnitude of the load applied to the FAB 44 after contacting of the FAB 44 with the pad 7 L was changed variously. The intended diameter of the first ball portion 15 L was 58 μm and the intended area of bonding of the first ball portion to the pad was 0.00264 mm 2 .

The load at which a first ball portion 15 L close to the intended diameter and the intended bonding area was obtained was 80 g. Also, this load was divided by the bonding area that was actually obtained to determine a load per unit area (unit area load) necessary for forming the first ball portion 15 L with the shape close to the intended shape, and the unit area load thus determined was 30295 g/mm 2 .

(2) Test 2

A 59 μm FAB 44 was formed at a tip of a copper wire 5 L of 25 μm wire diameter, the capillary C was lowered toward a pad 7 L, and the FAB 44 was pressed against the pad 7 L to form a first ball portion 15 L on the pad 7 L by deformation of the FAB 44 . The magnitude of the load applied to the FAB 44 after contacting of the FAB 44 with the pad 7 L was changed variously. The intended diameter of the first ball portion 15 L was 74 μm and the intended bonding area of the first ball portion with respect to the pad was 0.0043 mm 2 .

The load at which a first ball portion 15 L close to the intended diameter and the intended bonding area was obtained was 130 g. Also, this load was divided by the bonding area that was actually obtained to determine the load per unit area (unit area load) necessary for forming the first ball portion 15 L with the shape close to the intended shape, and the unit area load thus determined was 30242 g/mm 2 .

(3) Test 3

A 59 μm FAB 44 was formed at a tip of a copper wire 5 L of 30 μm wire diameter, the capillary C was lowered toward a pad 7 L, and the FAB 44 was pressed against the pad 7 L to form a first ball portion 15 L on the pad 7 L by deformation of the FAB 44 . The magnitude of the load applied to the FAB 44 after contacting of the FAB 44 with the pad 7 L was changed variously. The intended diameter of the first ball portion 15 L was 74 μm and the intended area of bonding of the first ball portion to the pad was 0.0043 mm 2 .

The load with which the first ball portion 15 L close to the intended diameter and the intended bonding area was obtained was 130 g. Also, this load was divided by the bonding area that was actually obtained to determine the load per unit area (unit area load) necessary for forming the first ball portion 15 L with the shape close to the intended shape, and the unit area load thus determined was 30242 g/mm 2 .

(4) Test 4

An 84 μm FAB 44 was formed at a tip of a copper wire 5 L of 38 μm wire diameter, the capillary C was lowered toward a pad 7 L, and the FAB 44 was pressed against the pad 7 L to form a first ball portion 15 L on the pad 7 L by deformation of the FAB 44 . The magnitude of the load applied to the FAB 44 after contacting of the FAB 44 with the pad 7 L was changed variously. The intended diameter of the first ball portion 15 L was 104 μm and the intended area of bonding of the first ball portion to the pad was 0.00849 mm 2 .

The load at which a first ball portion 15 L close to the intended diameter and the intended bonding area was obtained was 240 g. Also, this load was divided by the bonding area that was actually obtained to determine the load per unit area (unit area load) necessary for forming the first ball portion 15 L with the shape close to the intended shape, and the unit area load thus determined was 28267 g/mm 2 .

From the results of tests 1 to 4, it was confirmed that the load per unit area (unit area load) necessary for forming the first ball portion 15 L with the shape close to the intended shape was substantially the same regardless of the wire diameter of the copper wire 5 L and the intended diameter and intended bonding area of the first ball portion 15 L.

Also, FIG. 111 shows a plot of the values, determined as the loads at which the first ball portion 15 L close to the intended diameter and the intended bonding area was obtained in the respective tests 1 to 4, as initial loads P 1 on a graph area having the intended bonding area as an X axis and the initial load as a Y axis. As shown in FIG. 111 , it was confirmed that there is a substantially proportional relationship between the initial load P 1 and the area of bonding the first ball portion 15 L to the pad 7 L.

The following tests 1 to 3 were performed to appropriately set the predetermined time period during which the initial load P 1 is applied to an FAB.

(1) Test 1

An FAB 44 was formed at a tip of a copper wire 5 L of 25 μm wire diameter, the capillary C was lowered toward a pad 7 L, the FAB 44 was pressed against the pad 7 L, and a fixed load was applied to the FAB 44 to form a first ball portion 15 L on the pad 7 L by deformation of the FAB 44 . The intended diameter of the first ball portion 15 L was 58 μm and the intended thickness thereof was 10 μm. For each of cases where the magnitude of the load applied to the FAB 44 was set to 50 g, 80 g, and 110 g, changes of the diameter and the thickness of the first ball portion 15 L with time elapsed from the contacting of the FAB 44 with the pad 7 L were examined. Changes with time of the diameter (ball diameter) are shown in FIG. 112 , and changes with time of the thickness (ball thicknesses) are shown in FIG. 113 .

(2) Test 2

An FAB 44 was formed at a tip of a copper wire 5 L of 25 μm wire diameter, the capillary C was lowered toward a pad 7 L, the FAB 44 was pressed against the pad 7 L, and a fixed load was applied to the FAB 44 to form a first ball portion 15 L on the pad 7 L by deformation of the FAB 44 . The intended diameter of the first ball portion 15 L was 76 μm and the intended thickness thereof was 18 μm. For each of cases where the magnitude of the load applied to the FAB 44 was set to 70 g, 90 g, 110 g, 130 g, 150 g, and 200 g, changes of the diameter and the thickness of the first ball portion 15 L with time elapsed from the contacting of the FAB 44 with the pad 7 L were examined. Changes with time of the diameter (ball diameter) are shown in FIG. 114 , and changes with time of the thickness (ball thicknesses) are shown in FIG. 115 .

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 25 of 27

(3) Test 3

An FAB 44 was formed at a tip of a copper wire 5 L of 38 μm wire diameter, the capillary C was lowered toward a pad 7 L, the FAB 44 was pressed against the pad 7 L, and a fixed load was applied to the FAB 44 to form a first ball portion 15 L on the pad 7 L by deformation of the FAB 44 . The intended diameter of the first ball portion 15 L was 104 μm and the intended thickness thereof was 25 μm. For each of cases where the magnitude of the load applied to the FAB 44 was set to 200 g, 230 g, 250 g, 300 g, 400 g, and 500 g, changes of the diameter and the thickness of the first ball portion 15 L with time elapsed from the contacting of the FAB 44 with the pad 7 L were examined. Changes with time of the diameter (ball diameter) are shown in FIG. 116 , and changes with time of the thickness (ball thicknesses) are shown in FIG. 117 .

As can be understood from reference to FIG. 112 to FIG. 117 , regardless of the wire diameter of the copper wire 5 L, the magnitude of the load, and the intended diameter and intended thickness of the first ball portion 15 L, the deformation of the FAB 44 is not completed in less than 2 msec from contact with the pad 7 L. On the other hand, it is considered that, after 4 msec from the contacting of the FAB 44 with the pad 7 L, the diameter and thickness of the FAB 44 are substantially unchanged and the deformation of the FAB 44 is reliably completed. To be more detailed, it is considered that, regardless of the wire diameter of the copper wire 5 L, the magnitude of the load, and the intended diameter and intended thickness of the first ball portion 15 L, the changes of the diameter and thickness of the FAB 44 are ended and the deformation of the FAB 44 is completed at a point of elapse of substantially 3 msec from the contacting of the FAB 44 with the pad 7 L.

It is thus considered that the predetermined time period during which the initial load P 1 is applied to an FAB is appropriately in a range of 2 to 4 msec and is more appropriately 3 msec.

As described above, after the FAB 44 formed on the tip of the copper wire 5 L is put in contact with a pad, a relatively large initial load P 1 is applied to the FAB 44 by the capillary C. The FAB 44 , which is made of Cu that is a harder metal than Au, is thereby deformed satisfactorily and thus the initial load P 1 applied to the FAB 44 can be made to contribute to the bonding of the FAB 44 and the pad 7 L while it is suitably attenuated by the deformation of the FAB 44 .

Also, the ultrasonic transducer vibrates from before the contacting of the FAB 44 with the pad 7 L. Thus, from the instant at which the FAB 44 contacts the pad 7 L, the ultrasonic vibration propagates to the portion of contact of the FAB 44 and the pad 7 L and the contact portion is rubbed against the pad 7 L. Consequently, a state can be realized where the FAB 44 after completion of bonding (first ball portion 15 L) has its central portion of surface of bonding with the pad 7 L (portion at which the FAB 44 and the pad 7 L first make contact) satisfactorily bonded to the pad 7 L.

After the FAB 44 contacts the pad 7 L, the value of the drive current applied to the ultrasonic transducer is increased gradually from the value U 1 to the value U 2 . Meanwhile, the FAB 44 deforms in a squeezed manner and an area of the portion of contact of the FAB 44 and the pad 7 L increases gradually. The ultrasonic vibration energy propagating from the ultrasonic transducer to the FAB 44 is thereby increased gradually and the area of the FAB 44 rubbed against the pad 7 L increases gradually. Consequently, a state of satisfactory bonding to the pad 7 L can be obtained up to a peripheral edge portion of the surface of bonding of the first ball portion 15 L with the pad 7 L while suppressing occurrence of crack or other damage in the pad 7 L and the interlayer insulating film 12 L below the pad 7 L due to rapid increase of the ultrasonic vibration energy propagating to the FAB 44 below the central portion of the first ball portion 15 L.

The deformation of the FAB 44 due to the pressing of the FAB 44 against the pad 7 L ends when the predetermined time period elapses from the contacting of the FAB 44 , made of Cu, with the pad 7 L. That is, the shape of the first ball portion 15 L is completed when the predetermined time period elapses from the contacting of the FAB 44 , made of Cu, with the pad 7 L. Thus, if the large initial load P 1 continues to be applied to the FAB 44 thereafter, the ultrasonic vibration will not propagate satisfactorily to the portion of contact of the FAB 44 and the pad 7 L. The load applied to the FAB 44 is thus decreased to the load P 2 after the elapse of the predetermined time period from the contacting of the FAB 44 with the pad 7 L. The ultrasonic vibration can thereby be made to propagate satisfactorily to the portion of contact of the FAB 44 and the pad 7 L.

Thus, by the wire bonding method according to the present preferred embodiment, satisfactory bonding of the copper wire 5 L to a pad 7 L, that is, a state where the entire surface of bonding of the first ball portion 15 L with the pad 7 L is bonded satisfactorily to the pad 7 L can be realized while preventing occurrence of damage in the pad 7 L and the interlayer insulating film 12 L below the pad 7 L.

After the contacting of the FAB 44 with the pad 7 L, the value of the drive current applied to the ultrasonic transducer is increased at the fixed rate of change from the value U 1 to the value U 2 . The rate of change is set to no more than 21 mA/msec. Occurrence of damage in the pad 7 L and the interlayer insulating film 12 L due to rapid increase of the ultrasonic vibration energy propagating to the FAB 44 can thereby be prevented effectively.

As a method for bonding the FAB 44 to a pad 7 L, continued application of a fixed load to the FAB 44 and continued application of a fixed drive current to the ultrasonic transducer after the contacting of the FAB 44 with the pad 7 L may be considered. However, with this method, no matter what magnitude the load applied to the FAB 44 and value of the drive current applied to the ultrasonic transducer are set to, the FAB 44 is not adequately bonded to the pad 7 L or so-called splash, in which the material of the pad 7 L protrudes greatly outward in a form of a thin collar to sides of the FAB 44 (first ball portion 15 L), occurs.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 26 of 27

With the wire bonding method according to the present preferred embodiment, the occurrence of splash is prevented by the value of the drive current applied to the ultrasonic transducer from before the contacting of the FAB 44 with the pad 7 L and the magnitude of the initial load being set appropriately.

That is, the value U 1 of the drive current applied to the ultrasonic transducer from before the contacting of the FAB 44 with the pad 7 L is set to less than 30 mA. The ultrasonic vibration energy that propagates to the FAB 44 immediately after the FAB 44 contacts the pad 7 L can thereby be prevented from being excessive. Consequently, occurrence of splash and occurrence of damage in the pad 7 L and the interlayer insulating film 12 L below the central portion of the first ball portion 15 L can be prevented satisfactorily.

Also, the initial load P 1 and the bonding area of the first ball portion 15 L with respect to the pad 7 L are in a substantially proportional relationship regardless of the wire diameter of the copper wire 5 L, and thus the magnitude of the initial load P 1 is set based on a value obtained by multiplying the intended bonding area of the first ball portion 15 L with respect to the pad 7 L by a fixed factor. The magnitude of the initial load P 1 can thus be set appropriately regardless of the wire diameter of the copper wire 5 L. Consequently, satisfactory deformation of the FAB 44 can be achieved and the state where the central portion of the surface of bonding of the first ball portion 15 L to the pad 7 L is bonded satisfactorily to the pad 7 L can be realized while satisfactorily preventing the occurrence of splash and occurrence of damage in the pad 7 L and the layer below the pad 7 L below the central portion of the first ball portion 15 L.

The deformation of the FAB 44 is completed in substantially 3 msec from the contacting of the FAB 44 with the pad 7 L regardless of the magnitude of the initial load P 1 and the intended diameter and thickness of the first ball portion 15 L, and thus after the elapse of 3 msec from the contacting of the FAB 44 with the pad 7 L, the load applied to the FAB 44 is decreased from the initial load P 1 to the load P 2 .

Also, the predetermined time period and the drive current values U 1 and U 2 are set so that the integrated value of the drive current applied to the ultrasonic transducer during the predetermined time period is no more than 146 mA·msec. Ultrasonic vibration of the appropriate energy amount is thereby made to propagate to the FAB 44 within the predetermined time period from the contacting of the FAB 44 with the pad 7 L, and thus a state where satisfactory bonding to the pad 7 L is achieved up to the peripheral edge portion of the surface of bonding of the first ball portion 15 L with the pad 7 L can be realized while preventing the occurrence of damage in the pad 7 L and the interlayer insulating film 12 L below the central portion of the first ball portion 15 L.

The value U 2 of the drive current that is applied to the ultrasonic transducer in the final stage is set so that the value obtained by dividing the value U 2 by the intended bonding area of the first ball portion 15 L is no more than 0.0197 mA/μm 2 . The ultrasonic vibration energy that propagates to the FAB 44 after the end of deformation of the FAB 44 can thereby be prevented from being excessive and occurrence of damage in the pad 7 L and the interlayer insulating film 12 L below the peripheral edge portion of the first ball portion 15 L can be prevented satisfactorily.

In the present preferred embodiment, the initial load P 1 that is greater than the load P 2 is applied for the predetermined time period from the contacting of the FAB 44 with the pad 7 L. However, the load applied to the FAB 44 at the instant and immediately after the FAB 44 contacts the pad 7 L is increased in an apparent manner and the same action and effect as those in the case where the initial load P 1 is applied to the FAB 44 are also obtained by increasing a movement speed of the capillary C when the FAB 44 is made to approach the pad 7 L and applying a fixed load to the FAB over the entire bonding time.

An FAB 44 was formed at a tip of a copper wire 5 L, the capillary C was lowered toward a pad 7 L at a fixed speed of 0.4 mil/msec (approximately 10.2 μm/msec) to press the FAB 44 against the pad 7 L, a load of 130 g was applied as the initial load P 1 to the FAB 44 for 3 msec, and thereafter, the load P 2 was applied to the FAB 44 for 9 msec to form a first ball portion 15 L on the pad 7 L by deformation of the FAB 44 . An SEM image obtained by imaging a vicinity of the first ball portion in this process by SEM (scanning electron microscope) is shown in FIG. 118 .

Also, an FAB 44 was formed at a tip of a copper wire 5 L, the capillary C was lowered toward a pad 7 L at a fixed speed of 1.00 mil/msec (approximately 2.45 m/msec) to press the FAB 44 against the pad 7 L, and a load of 45 g was applied to the FAB 44 for 12 msec from the contacting of the FAB 44 with the pad 7 L to forma first ball portion 15 L on the pad 7 L by deformation of the FAB 44 . An SEM image of the first ball portion in this process is shown in FIG. 119 .

From a comparison of FIG. 118 and FIG. 119 , it can be understood that the shapes of the first ball portions 15 L and the shapes of the jutting portions 16 L are substantially the same.

Although the twelfth preferred embodiment of the present invention has been described above, the twelfth preferred embodiment may also be modified as follows.

For example, although a QFN is applied to the semiconductor device 1 L, the present invention may also be applied to the manufacture of a semiconductor device to which another type of non-leaded package, such as an SON (small outlined non-leaded package), is applied.

›Example 9 X-direction Dx: 76.5 μm Y-direction Dy: 79.1 μm · 27 of 27

Also, although with the above-described preferred embodiment, a mode in which the copper wires 5 L are covered by the water-impermeable insulating film 25 L was described as an example, the water-impermeable insulating film 25 L may be omitted as shown in FIG. 120 as long as at least the twelfth object for resolving the twelfth issue is achieved.

Experiments related to the present twelfth preferred embodiment were performed. The present invention is not restricted to the examples described below.

1. Evaluation Test 1

A capillary made by Micro-Swiss was used. The capillary has the following dimensions. ACD dimension that is a diameter of a lower end edge of a chamfer is 66 μm (0.066 mm). A T dimension that is an outer diameter of a face is 178 μm (0.178 mm). A chamfer angle, which two straight lines extending along a side surface of the chamfer form in a cross section of the capillary taken along a plane that includes a central axis (see cross section shown in FIG. 109A ), is 90°. A face angle FA that is an angle that the face forms with a plane orthogonal to the central axis of the capillary is 8°. An angle, which, in the cross section of the capillary taken along the plane that includes the central axis, a portion of the side surface of the capillary that extends upward beyond the upper end of the face forms with the central axis, is 20°. An upper end portion of the face is arcuate and an OR dimension that is a radius of curvature of this portion is 20 μm (0.020 mm).

The capillary was positioned at a position of 7 mil (approximately 178 μm) height from a top surface of a pad made of an Al—Cu-based alloy and an FAB of 2.33 mil (approximately 60 μm) diameter was formed on a tip of a copper wire with a wire diameter of 25 μm. The capillary was then lowered toward the pad at a speed of 0.4 mil/msec (approximately 10.2 μm/msec) to press the FAB against the pad and form a first ball portion on the pad by deformation of the FAB. The intended diameter of the first ball portion was 74 μm and the intended bonding area of the first ball portion with respect to the pad was 0.0043 mm 2 .

›Example 1 · 1 of 2

As shown in FIG. 121 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, from before the contacting of the FAB with the pad, a drive current of 15 mA was applied to an ultrasonic transducer provided in the capillary, and after the FAB contacted the pad, the value of the drive current applied to the ultrasonic transducer was raised in a period of 3.6 msec from 15 mA to 90 mA at a fixed rate of change (approximately 20.83 mA/msec) and the state of applying the drive current of 90 mA to the ultrasonic transducer was maintained for 8.4 msec until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary). The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 138.75 mA·msec. Also, a value obtained by dividing the value of the drive current applied at the final stage to the ultrasonic transducer by a square of the intended diameter of the first ball portion was approximately 0.0164 mA/μm 2 and less than 0.0197 mA/μm 2 .

Comparative Example 1

As shown in FIG. 122 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, before the contacting of the FAB with the pad, a drive current was not applied to the ultrasonic transducer provided in the capillary, and after the FAB contacted the pad, the value of the drive current applied to the ultrasonic transducer was raised in a period of 3.6 msec from 0 mA to 90 mA at a fixed rate of change (25 mA/msec) and the state of applying the drive current of 90 mA to the ultrasonic transducer was maintained for 8.4 msec until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary). In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 112.5 mA·msec.

Comparative Example 2

As shown in FIG. 123 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, from before the contacting of the FAB with the pad, a drive current of 15 mA was applied to the ultrasonic transducer provided in the capillary, and at the point of elapse of 3.6 msec after the FAB contacted the pad, the value of the drive current applied to the ultrasonic transducer was raised instantaneously from 15 mA to 90 mA and the state of applying the drive current of 90 mA to the ultrasonic transducer was maintained for 8.4 msec until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary). In this case, the drive current is not applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB.

Comparative Example 3

As shown in FIG. 124 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, before the contacting of the FAB with the pad, a drive current was not applied to the ultrasonic transducer provided in the capillary, and at the point of elapse of 3.6 msec after the FAB contacted the pad, the value of the drive current applied to the ultrasonic transducer was raised instantaneously from 0 mA to 90 mA and the state of applying the drive current of 90 mA to the ultrasonic transducer was maintained for 8.4 msec until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary). In this case, the drive current is not applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB.

(1) Splash Evaluation (Appearance Evaluation)

With each of Example 1 and Comparative Examples 1 to 3, a vicinity of the first ball portion was observed using SEM. An SEM image of the vicinity of the first ball portion of Example 1 is shown in FIG. 125 . SEM images of the vicinities of the first ball portions of Comparative Example 1 to 3 are respectively shown in FIG. 126 to FIG. 128 .

As shown in FIG. 126 to FIG. 128 , with all of Example 1 and Comparative Examples 1 to 3, it was confirmed that the material of the pad jutted out slightly to the side of the first ball portion and splash did not occur.

(2) Evaluation of Rear Side of the Ball

The first ball portions of Example 1 and Comparative Examples 1 to 3 were peeled from the pads and the surface of bonding of the first ball portion with the pad was observed using SEM. An SEM image of the bond surface of the first ball portion of Example 1 is shown in FIG. 129 . SEM images of the bond surfaces of the first ball portions of Comparative Examples 1 to 3 are shown in FIG. 130 to FIG. 132 .

As shown in FIG. 129 , it was confirmed that, with the first ball portion of Example 1, fine scars due to ultrasonic vibration were made over substantially the entire bond surface. This confirms that the ultrasonic vibration propagates satisfactorily to the FAB over the entire period from the instant the FAB contacts the pad to the completion of the shape of the first ball portion and that the entire contact portion of the FAB with respect to the pad is rubbed against the pad by the ultrasonic vibration.

›Example 1 · 2 of 2

As shown in FIG. 130 , it was confirmed that, with the first ball portion of Comparative Example 1, a portion Po 1 that is not scarred by ultrasonic vibration is present at a portion of a central portion of the bond surface. It is considered that such a portion Po 1 is present because the ultrasonic vibration does not propagate to the FAB immediately after the FAB contacts the pad and the contact portion of the FAB with respect to the pad is not rubbed.

As shown in FIG. 131 , it was confirmed that, with the first ball portion of Comparative Example 2, a portion Po 2 that is not scarred by ultrasonic vibration is present between a central portion and a peripheral edge portion of the bond surface. It is considered that such a portion Po 2 is present because although the ultrasonic vibration propagates to the FAB from the instant the FAB contacts the pad, the ultrasonic vibration is inadequate in the process of deformation of the FAB to the first ball portion.

As shown in FIG. 132 , it was confirmed that, with the first ball portion of Comparative Example 3, fine scars due to ultrasonic vibration were made only at a peripheral edge portion of the bonding portion and a portion Po 3 that is not scarred is present at a central portion. It is considered that such a portion Po 3 is present because the ultrasonic vibration propagates to the FAB only after the FAB has deformed to the first ball portion.

(3) Evaluation of Upper Side of the Pad

The copper wires, including the first ball portions, of Example 1 and Comparative Examples 1 to 3 were dissolved with fuming nitric acid and the surfaces of bonding of the pads with the first ball portions were observed using an optical microscope. An image of the pad of Example 1 is shown in FIG. 133 . Images of the pads of Comparative Examples 1 to 3 are shown in FIG. 134 to FIG. 136 .

Before the present evaluation test, EDS (electric die sort) for inspecting whether or not a semiconductor chip is non-defective was performed and before the bonding of the FAB, needle marks due to pressing of an EDS inspection probe were made on the top surfaces of the respective pads.

As shown in FIG. 133 , it was confirmed that the needle marks have disappeared from the pad of Example 1. This confirms that the FAB was pressed against the pad to a degree such that the needle marks disappeared from the pad and the FAB (first ball portion) was bonded firmly to the pad.

On the other hand, as shown in FIG. 134 to FIG. 136 , it was confirmed that the needle marks remained on the pads of Comparative Examples 1 to 3.

(4) Evaluation of Portion below the Pad

The copper wires, including the first ball portions, of Example 1 and Comparative Examples 1 to 3 were dissolved with fuming nitric acid, the pads were further removed, and the exposed top surfaces of the interlayer insulating films were observed using an optical microscope. An image of the top surface of the interlayer insulating film of Example 1 is shown in FIG. 137 . Images of the top surfaces of the interlayer insulating films of Comparative Examples 1 to 3 are shown in FIG. 138 to FIG. 140 .

As shown in FIG. 137 to FIG. 140 , it was confirmed that crack or other damage did not occur in the interlayer insulating film of any one of Example 1 and Comparative Examples 1 to 3.

2. Evaluation Test 2

A capillary made by Micro-Swiss was used. The capillary has the following dimensions. The CD dimension that is the diameter of the lower end edge of the chamfer is 66 μm (0.066 mm). The T dimension that is the outer diameter of the face is 178 μm (0.178 mm). The chamfer angle, which two straight lines extending along the side surface of the chamfer form in the cross section of the capillary taken along the plane that includes the central axis (see cross section shown in FIG. 109A ), is 90°. The face angle FA that is the angle that the face forms with the plane orthogonal to the central axis of the capillary is 8°. The angle, which, in the cross section of the capillary taken along the plane that includes the central axis, the portion of the side surface of the capillary that extends upward beyond the upper end of the face forms with the central axis, is 20°. The upper end portion of the face is arcuate and the OR dimension that is the radius of curvature of this portion is 20 μm (0.020 mm).

The capillary was positioned at a position of 7 mil (approximately 178 μm) height from the top surface of a pad made of an Al—Cu-based alloy and an FAB of 2.33 mil (approximately 60 μm) diameter was formed on the tip of a copper wire with a wire diameter of 25 μm. The capillary was then lowered toward the pad at a speed of 0.4 mil/msec (approximately 10.2 μm/msec) to press the FAB against the pad and form a first ball portion on the pad by deformation of the FAB. The intended diameter of the first ball portion was 74 μm and the intended bonding area of the first ball portion with respect to the pad was 0.00430 mm 2 .

As shown in FIG. 141 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, from before the contacting of the FAB with the pad, a drive current of 20 mA was applied to the ultrasonic transducer provided in the capillary, and after the FAB contacted the pad, the value of the drive current applied to the ultrasonic transducer was raised from 20 mA to 90 mA at a fixed rate of change and the state of applying the drive current of 90 mA to the ultrasonic transducer was maintained until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary). Example 2 and Comparative Examples 4 to 8 differ in a time (ramp-up time) taken for the value of the drive current applied to the ultrasonic transducer to reach 90 mA from 20 mA. In all of Example 2 and Comparative Examples 4 to 8, the value obtained by dividing the value of the drive current applied at the final stage to the ultrasonic transducer by the intended bonding area of the first ball portion was approximately 0.0164 mA/μm 2 and less than 0.0197 mA/μm 2 .

›Example 2

In Example 2, the ramp-up time was set to 3.6 msec. In other words, 30% of the time period from the contacting of the FAB with the pad to the raising of the capillary (12 msec, hereinafter referred to as the “bonding time”) was set as the ramp-up time. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 20 mA to 90 mA at a rate of change of approximately 19.44 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 147.5 mA·msec.

Comparative Example 4

In Comparative Example 4, the ramp-up time was set to 3.0 msec. In other words, 25% of the bonding time was set as the ramp-up time. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 20 mA to 90 mA at a rate of change of approximately 23.33 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 165 mA·msec.

Comparative Example 5

In Comparative Example 5, the ramp-up time was set to 2.4 msec. In other words, 20% of the bonding time was set as the ramp-up time. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 20 mA to 90 mA at a rate of change of approximately 29.17 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 207 mA·msec.

Comparative Example 6

In Comparative Example 6, the ramp-up time was set to 1.8 msec. In other words, 15% of the bonding time was set as the ramp-up time. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 20 mA to 90 mA at a rate of change of approximately 38.89 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 228 mA·msec.

Comparative Example 7

In Comparative Example 7, the ramp-up time was set to 1.2 msec. In other words, 10% of the bonding time was set as the ramp-up time. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 20 mA to 90 mA at a rate of change of approximately 58.33 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 249 mA·msec.

Comparative Example 8

In Comparative Example 8, the ramp-up time was set to 0 msec. In other words, 0% of the bonding time was set as the ramp-up time.

(1) Crack Evaluation

With each of Example 2 and Comparative Examples 4 to 8, FABs were bonded to 48 pads, whether or not a crack formed in the interlayer insulating film at the lower layer of each pad was examined, and a crack occurrence rate (number of pads with which a crack formed in the interlayer insulating film at the lower layer/48×100) was computed. The computation results are shown in FIG. 142 .

As shown in FIG. 142 , with Example 1, with which the ramp-up time was 30% of the bonding time and the rate of change of the drive current was approximately 19.44 mA/msec, it was confirmed that a crack did not occur in the interlayer insulating film.

On the other hand, with each of Comparative Examples 4 to 8, with which the ramp-up time was no more than 25% of the bonding time and the rate of change of the drive current was no less than approximately 23.33 mA/msec, it was confirmed that a crack occurred in the interlayer insulating film.

3. Evaluation Test 3

A capillary made by Micro-Swiss was used. The capillary has the following dimensions. The CD dimension that is the diameter of the lower end edge of the chamfer is 66 μm (0.066 mm). The T dimension that is the outer diameter of the face is 178 μm (0.178 mm). The chamfer angle, which two straight lines extending along the side surface of the chamfer form in the cross section of the capillary taken along the plane that includes the central axis (see cross section shown in FIG. 109A ), is 90°. The face angle that is the angle that the face forms with the plane orthogonal to the central axis of the capillary is 8°. The angle, which, in the cross section of the capillary taken along the plane that includes the central axis, the portion of the side surface of the capillary that extends upward beyond the upper end of the face forms with the central axis, is 20°. The upper end portion of the face is arcuate and the OR dimension that is the radius of curvature of this portion is 20 μm (0.020 mm).

As shown in FIG. 143 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, from before the contacting of the FAB with the pad, a drive current was applied to the ultrasonic transducer provided in the capillary, and after the FAB contacted the pad, the value of the drive current applied to the ultrasonic transducer was raised to 90 mA at a fixed rate of change in the period of 3.6 msec and the state of applying the drive current of 90 mA to the ultrasonic transducer was maintained until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary). Examples 3 to 7 and Comparative Examples 9 to 11 differ in the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad. In all of Examples 3 to 7 and Comparative Examples 4 to 8, the value obtained by dividing the value of the drive current applied at the final stage to the ultrasonic transducer by the intended bonding area of the first ball portion was approximately 0.0164 mA/μm 2 and less than 0.0197 mA/μm 2 .

›Example 3

In Example 3, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 0 mA. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 0 mA to 90 mA at a rate of change of 25 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 112.5 mA·msec.

›Example 4

In Example 4, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 10 mA. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 10 mA to 90 mA at a rate of change of approximately 22.22 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 130 mA·msec.

›Example 5

In Example 5, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 15 mA. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 15 mA to 90 mA at a rate of change of approximately 20.83 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 138.75 mA·msec.

›Example 6

In Example 6, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 20 mA. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 20 mA to 90 mA at a rate of change of approximately 19.44 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 147.5 mA·msec.

›Example 7

In Example 7, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 25 mA. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 25 mA to 90 mA at a rate of change of approximately 18.04 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 156.25 mA·msec.

Comparative Example 9

In Comparative Example 9, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 30 mA. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 30 mA to 90 mA at a rate of change of approximately 16.67 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 165 mA·msec.

Comparative Example 10

In Comparative Example 10, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 60 mA. The drive current applied to the ultrasonic transducer after the contacting of the FAB with the pad was thereby raised from 60 mA to 90 mA at a rate of change of approximately 8.34 mA/msec. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 255 mA·msec.

Comparative Example 11

In Comparative Example 11, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 90 mA. The drive current applied to the ultrasonic transducer thus does not change before and after the contacting of the FAB with the pad. The integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 270 mA·msec.

(1) Crack Evaluation

With each of Examples 3 to 7 and Comparative Examples 9 to 11, FABs were bonded to 48 pads, whether or not a crack formed in the interlayer insulating film at the lower layer of each pad was examined, and a crack occurrence rate (number of pads with which a crack formed in the interlayer insulating film at the lower layer/48×100) was computed.

The computation results are shown in FIG. 144 .

As shown in FIG. 144 , it was confirmed that, with each of Examples 3 to 7, with which the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was no more than 25 mA, a crack did not occur in the interlayer insulating film.

On the other hand, it was confirmed that, with each of Comparative Examples 9 to 11, with which the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was no less than 30 mA, a crack occurred in the interlayer insulating film.

4. Evaluation Test 4

The capillary was positioned at a position of 7 mil (approximately 178 μm) height from the top surface of a pad made of an Al—Cu-based alloy and an FAB of 2.33 mil (approximately 60 μm) diameter was formed on the tip of a copper wire with a wire diameter of 25 μm. The capillary was then lowered toward the pad at a speed of 0.4 mil/msec (approximately 10.2 μm/msec) to press the FAB against the pad and form a first ball portion on the pad by deformation of the FAB. The intended diameter of the first ball portion was 76 μm and the intended thickness of the first ball portion was 18 μm.

›Example 8 · 1 of 6

For 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, a state of applying a drive current of 90 mA to the ultrasonic transducer was maintained from the FAB contacted the pad until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary). The value obtained by dividing the value of the drive current applied to the ultrasonic transducer by the intended bonding area of the first ball portion was approximately 0.0164 mA/μm 2 and less than 0.0197 mA/μm 2 .

Comparative Example 12

A state of applying a load of 30 g to the FAB was maintained from the contacting of the FAB with the pad until the raising of the capillary.

Also, a state of applying a drive current of 130 mA to the ultrasonic transducer was maintained from the FAB contacted the pad until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary).

Comparative Example 13

A state of applying a load of 90 g to the FAB was maintained from the contacting of the FAB with the pad until the raising of the capillary.

Comparative Example 14

Also, a state of applying a drive current of 70 mA to the ultrasonic transducer was maintained from the FAB contacted the pad until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary).

(1) Splash Evaluation (Appearance Evaluation 1)

With each of Example 8 and Comparative Examples 12 to 14, a vicinity of the first ball portion was observed using SEM. An SEM image of the vicinity of the first ball portion of Example 8 is shown in FIG. 145 . SEM images of the vicinities of the first ball portions of Comparative Example 12 to 14 are respectively shown in FIG. 146 to FIG. 148 .

As shown in FIGS. 145 and 148 , with each of Example 8 and Comparative Example 14 with which the initial load is applied to the FAB after contacting of the FAB with the pad, it was confirmed that the material of the pad jutted out slightly to the side of the first ball portion and splash did not occur.

On the other hand, as shown in FIGS. 146 and 147 , with each of Comparative Examples 12 and 13, with which an initial load is not applied to the FAB, it was confirmed that the material of the pad protruded greatly outward in a form of a thin collar to sides of the first ball portion and splash occurred.

(2) Shear Test Evaluation 1

With each of Example 8 and Comparative Examples 12 to 14, a shear tester (bonding strength tester) was used and the bonding portion of the first ball portion and the pad was broken by pushing the bonding portion from a side thereof in a direction parallel to the top surface of the pad in a shearing manner by a tool of the shear tester. An image observed by an optical microscope of the pad after breakage of Example 8 is shown in FIG. 149 . An image observed by the optical microscope of the pad after breakage of Comparative Example 12 is shown in FIG. 150 . An image observed by the optical microscope of the pad after breakage of Comparative Example 13 is shown in FIG. 151 , and an image observed by the optical microscope of a bottom surface of the first ball portion (surface joined to the pad) after breakage is shown in FIG. 152 . An image observed by the optical microscope of the pad after breakage of Comparative Example 14 is shown in FIG. 153 .

As can be understood from comparing FIGS. 149 and 153 with FIGS. 150 and 151 , with each of Comparative Example 12 in which a large load is applied to the FAB over the entire bonding time and Comparative Example 13 in which a drive current of a large value is applied to the ultrasonic transducer, the first ball portion strongly penetrates into the pad in comparison to the first ball portions of Example 8 and Comparative Example 14. It was thus visually confirmed that the bonding strength of the first ball portion and the pad is large in each of Comparative Examples 12 and 13 in comparison to Example 8 and Comparative Example 14.

However, as can be understood from FIG. 152 , with Comparative Example 13, the energy of the ultrasonic vibration propagating to the first ball portion is too large and thus the first ball portion penetrates into the pad excessively and a portion of the first ball portion close to the copper wire is cut. It is thus considered that the bonding strength only appears to be high and the actual bonding strength is not that high.

(3) Appearance Evaluation 2

With each of Example 8 and Comparative Examples 12 to 14, FABs were bonded to 80 pads and the diameters and thicknesses of the first ball portions formed thereby were measured. Each first ball portion is not a complete circle in plan view and thus the diameter thereof was measured for the two directions of the X direction and Y direction parallel to the top surface of the pad. The diameter measurement results are shown in FIG. 154 . The thickness measurement results are shown in FIG. 155 .

As shown in FIGS. 154 and 155 , it was confirmed that although with all of Example 8 and Comparative Examples 12 to 14, first ball portions of the intended diameter and intended thickness can be formed, with the first ball portions of Comparative Examples 12 and 13, the diameter and thickness were both high in variation in comparison to the first ball portions of Example 8 and Comparative Example 14.

›Example 8 · 2 of 6

(4) Shear Test Evaluation 2

A force (shear strength) required for breaking by pushing the bonding portion of the first ball portion and the pad from the side in shear test evaluation 1 was measured. The measurement results are shown in FIG. 156 .

As shown in FIG. 156 , it was confirmed that, with Comparative Examples 12 and 13, although the shear strengths are high in comparison to those of Example 8 and Comparative Example 14, the variations thereof are also large.

It was also confirmed that with Example 8, the shear strength is higher than that of Comparative Example 14.

Thirteenth Preferred Embodiment FIG. 157 to FIG. 168

By disclosure of a thirteenth preferred embodiment, a thirteenth issue concerning a thirteenth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Thirteenth Background Art

In a typical semiconductor device, a semiconductor chip is disposed on a die pad and leads disposed in peripheries of the semiconductor chip and the die pad are connected by wires made of Au (gold). Specifically, pads made of Al (aluminum) are disposed on a top surface of the semiconductor chip. The wires made of Au are installed so as to form arch-shaped loops between top surfaces of the pads and top surfaces of the leads.

(2) Thirteenth Issue

However, an FAB formed on a tip of a copper wire is harder than an FAB formed on a tip of a gold wire, and thus, if a copper wire is bonded to a pad under the same conditions (magnitudes of load and ultrasonic transducer drive current, etc.) as those for a gold wire, satisfactory bonding of the copper wire and the pad cannot be obtained. Presently, conditions that enable satisfactory bonding of a copper wire and a pad to be achieved are not clear and active replacement of gold wires by copper wires is yet to take place.

Thus, a thirteenth object of the present invention related to the thirteenth preferred embodiment is to provide a wire bonding method that enables satisfactory bonding of a copper wire to a pad to be achieved.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 157 is a schematic sectional view of a semiconductor device according to the thirteenth preferred embodiment of the present invention. FIG. 158 is a schematic bottom view of the semiconductor device shown in FIG. 157 .

The semiconductor device 1 M is a semiconductor device to which a QFN (quad flat non-leaded package) configuration is applied and has a structure in which a semiconductor chip 2 M is sealed together with a die pad 3 M, leads 4 M, and copper wires 5 M by a resin package 6 M. An outer shape of the semiconductor device 1 M (resin package 6 M) is a flat, rectangular parallelepiped shape.

In the present preferred embodiment, the outer shape of the semiconductor device 1 M is a hexahedron having a square shape of 4 mm square as a planar shape and a thickness of 0.85 mm, and dimensions of respective portions of the semiconductor device 1 M cited below make up an example in the case where the semiconductor device 1 M has the above outer dimensions.

The semiconductor chip 2 M has a square shape of 2.3 mm in plan view, and the semiconductor chip 2 M has a thickness of 0.23 mm. A plurality of pads 7 M are disposed at peripheral edge portions of a top surface of the semiconductor chip 2 M. Each pad 7 M is electrically connected to a circuit built into the semiconductor chip 2 M. A rear metal 8 M made of a metal layer of Au, Ni (nickel), Ag (silver), etc., is formed on a rear surface of the semiconductor chip 2 M.

The die pad 3 M and the leads 4 M are formed by punching out a metal thin plate (for example, a copper thin plate). The metal thin plate (die pad 3 or lead 4 M) has a thickness of 0.2 mm. A plating layer 9 M made of Ag is formed on top surfaces of the die pad 3 M and leads 4 M.

The die pad 3 M has a square shape of 2.7 mm in plan view and is disposed at a central portion of the semiconductor device 1 M so that its respective side surfaces are parallel to side surfaces of the semiconductor device 1 M.

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface side across an entire periphery of a peripheral edge portion of the rear surface of the die pad 3 M. The resin package 6 M enters the recess. The peripheral edge portion of the die pad 3 M is thereby sandwiched from above and below by the resin package 6 M and prevention of fall-off (retaining) of the die pad 3 M with respect to the resin package 6 M is thereby achieved.

Also, with the exception of the peripheral edge portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of the die pad 3 M is exposed from a rear surface of the resin package 6 M.

An equal number of (for example, nine) leads 4 M are disposed at each of positions facing the respective side surfaces of the die pad 3 M. At each of the positions facing the side surfaces of the die pad 3 M, the leads 4 M extend in a direction orthogonal to the facing side surface and are disposed at equal intervals in a direction parallel to the side surface. A longitudinal direction length of each lead 4 M is 0.45 mm. Also, an interval between the die pad 3 M and the lead 4 M is 0.2 mm.

›Example 8 · 3 of 6

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface side at a die pad 3 M side end portion of the rear surface of each lead 4 M. The resin package 6 M enters the recess. The die pad 3 M side end portion of the lead 4 M is thereby sandwiched from above and below by the resin package 6 M and prevention of fall-off (retaining) of the lead 4 M with respect to the resin package 6 M is thereby achieved.

With the exception of the die pad 3 M side end portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of each lead 4 M is exposed from a rear surface of the resin package 6 M. Also, a side surface of the lead 4 M facing the die pad 3 M side is exposed from a side surface of the resin package 6 M.

A plating layer 10 M formed of solder is formed on portions of the rear surfaces of the die pad 3 M and leads 4 M that are exposed from the resin package 6 M.

With its top surface with the pads 7 M disposed thereon facing upward, the semiconductor chip 2 M has its rear surface bonded via a bonding material 11 M to the top surface (plating layer 10 M) of the die pad 3 M. For example, a solder paste is used as the bonding material 11 M. The bonding material 11 M has a thickness of 0.02 mm.

In a case where electrical connection of the semiconductor chip 2 M and the die pad 3 M is unnecessary, the rear metal 8 M may be omitted and the rear surface of the semiconductor chip 2 M may be bonded to the top surface of the die pad 3 M via a bonding material made of silver paste or other insulating paste. In this case, the planar size of the semiconductor chip 2 M is 2.3 mm square. Also, the plating layer 9 M on the top surface of the die pad 3 M may be omitted.

The copper wires 5 M are made, for example, of copper with a purity of no less than 99.99%. One end of each copper wire 5 M is bonded to a pad 7 M of the semiconductor chip 2 M. The other end of the copper wire 5 M is bonded to the top surface of a lead 4 M. The copper wire 5 M is installed so as to form an arch-shaped loop between the semiconductor chip 2 M and the lead 4 M. A height difference between an apex portion of the loop of the copper wire 5 M and the top surface of the semiconductor chip 2 M is 0.16 mm.

As in the first preferred embodiment, in the semiconductor device 1 M, the entire top surface and side surfaces of the semiconductor chip 2 M, the entire top surface and side surfaces of the die pad 3 M, entire top surfaces of the leads 4 M, and the entire copper wires 5 M are covered by an integral water-impermeable insulating film 25 M.

FIG. 159 is an enlarged view of a portion surrounded by broken lines shown in FIG. 157 .

Each pad 7 M is made of a metal that contains aluminum and is formed on an uppermost interlayer insulating film 12 M of the semiconductor chip 2 M. A top surface protective film 13 M is formed on the interlayer insulating film 12 M. The pad 7 M has its peripheral edge portion covered by the top surface protective film 13 M and its central portion is exposed via a pad opening 14 M formed in the top surface protective film 13 M.

The copper wire 5 M is bonded to the central portion of the pad 7 M exposed from the top surface protective film 13 M. As shall be described below, the copper wire 5 M has an FAB formed at its tip and the FAB is pressed against and thereby bonded to the pad 7 M. In this process, the FAB deforms to form a first ball portion 15 M with a stepped disk shape at the portion of bonding of the copper wire 5 M with the pad 7 M. Also, at a periphery of the first ball portion 15 M, the material of the pad 7 M juts out gradually from below the first ball portion 15 M so as to form a jutting portion 16 M without it being lifted greatly from the top surface of the pad 7 M.

For example, in a case where the copper wire 5 M has a wire diameter of 25 μm, an intended diameter of the first ball portion 15 M (designed diameter of the first ball portion 15 M) is 74 to 76 μm, and an intended thickness of the first ball portion 15 M (designed thickness of the first ball portion 15 M) is 17 to 18 μm.

FIG. 160A to FIG. 160D are schematic sectional views for describing a method for manufacturing the semiconductor device according to the thirteenth preferred embodiment in order of process.

The copper wires 5 M are installed across the semiconductor chip 2 M and the leads 4 M by a wire bonder in a state where the die pad 3 M and the leads 4 M are connected to a frame (not shown) that surrounds these components, that is, in a state where the die pad 3 M and leads 4 M make up a lead frame.

The wire bonder includes a capillary C. As shown in FIG. 160A , the capillary C has a substantially cylindrical shape with a wire insertion hole 41 M formed along a central axis. The copper wire 5 M is inserted through the wire insertion hole 41 M and fed out from a tip (lower end) of the wire insertion hole 41 M.

A chamfer 42 M of truncated conical shape that is in communication with the wire insertion hole 41 M is formed below the wire insertion hole 41 M at a tip portion of the capillary C. Also, the tip portion of the capillary C has a face 43 M that is continuous with a lower end edge of the chamfer 42 M and is a surface that faces a pad 7 M and a lead 4 M during bonding (during wire bonding) of the copper wire 5 M to these components. An outer side of the face 43 M is gradually inclined upwardly with respect to a plane orthogonal to the central axis of the capillary C.

First, as shown in FIG. 160A , the capillary C is moved to a position directly above the pad 7 M. Next, in a state where a tip of the copper wire 5 M is positioned at the chamfer 42 M, a current is applied to a tip portion of the copper wire 5 M and an FAB 44 is thereby formed at the tip portion. The value and application time of the current are set suitably in accordance with the wire diameter of the copper wire 5 M and an intended diameter of the FAB 44 (designed diameter of the FAB 44 ). A portion of the FAB 44 protrudes below the chamfer 42 M.

›Example 8 · 4 of 6

Thereafter, as shown in FIG. 160B , the capillary 44 is lowered toward the pad 7 M and the FAB 44 is pressed against the pad 7 M by the capillary C. In this process, a load is applied to the FAB 44 by the capillary C and ultrasonic vibration, emitted from an ultrasonic transducer (not shown) provided in the capillary C, is applied to the FAB 44 .

FIG. 161 is a graph of changes with time of the load applied to the FAB and a driving current applied to the ultrasonic transducer during the bonding of the FAB to the pad.

For example, as shown in FIG. 161 , a relatively large initial load P 1 is applied from the capillary C to the FAB 44 from a time T 1 at which the FAB 44 contacts the pad 7 M to a time T 2 after elapse of a predetermined time period. The predetermined time period is set to no more than 3 msec. Also, the initial load P 1 is set based on a value obtained by multiplying an intended bonding area of the first ball portion 15 M with respect to the pad 7 (designed bonding area of the first ball portion 15 M with respect to the pad 7 ) by a fixed factor (for example, 28786 in a case where the unit of the initial load P 1 is g and the unit of the bonding area is mm 2 ). From the time T 2 onward, the load applied to the FAB 44 from the capillary C is lowered and a relatively small load P 2 is applied to the FAB 44 . The load P 2 is applied continuously until a time T 4 at which the capillary C is raised.

Meanwhile, a drive current of a relatively small value U 1 is applied to the ultrasonic transducer from before the time T 1 at which the FAB 44 contacts the pad 7 M. The drive current value U 1 is set to less than 30 mA.

Then, from the time T 1 at which the FAB 44 contacts the pad 7 M to a time T 3 , the value of the drive current applied to the ultrasonic transducer is raised at a fixed rate of change (monotonously) from the value U 1 to a relatively large value U 2 . Also, the drive current values U 1 and U 2 are set so that an integrated value of the drive current applied to the ultrasonic transducer during the predetermined time period in which the initial load is applied to the FAB 44 is no more than 146 mA·msec. From the time T 3 onward until the time T 4 , the drive current of the value U 2 continues to be applied to the ultrasonic transducer.

Consequently, the FAB 44 deforms along the shapes of the chamfer 42 M and the face 43 M of the capillary C, and the first ball portion 15 M with a stepped disk shape is formed on the pad 7 M with the jutting portion 16 M being formed along its periphery as shown in FIG. 159 . Bonding (first bonding) of the copper wire 5 M with the pad 7 M is thereby achieved. The drive current value U 1 may be set to zero, and in this case, the drive current is not applied to the ultrasonic transducer before the time T 1 .

When the time T 4 arrives upon elapse of a bonding time determined in advance from the time T 1 , the capillary C separates upwardly from the pad 7 M. Thereafter, the capillary C is moved obliquely downward toward the top surface of the lead 4 M. Then, as shown in FIG. 160C , the drive current is applied to the ultrasonic transducer, and while ultrasonic vibration is being applied to the capillary C, the copper wire 5 M is pressed against the top surface of the lead 4 M by the capillary C and then broken. A stitch portion with a wedge shape in side view that is made up of the other end portion of the copper wire 5 M is thereby formed on the top surface of the lead 4 M and the bonding (second bonding) of the copper wire with respect to the lead 4 M is thereby achieved.

Thereafter, the processes shown in FIG. 160A to FIG. 160C are performed on another pad 7 M and the corresponding lead 4 M. By the processes shown in FIG. 160A to FIG. 160C then being repeated, copper wires 5 M are installed across all pads 7 M of the semiconductor chip 2 M and the leads 4 M as shown in FIG. 160 D. After the end of all of the wire bonding, the water-impermeable insulating film 25 M is formed by the same method as that of FIG. 4D .

As described above, after the FAB 44 formed on the tip of the copper wire 5 M is put in contact with a pad 7 M, a relatively large initial load P 1 is applied to the FAB 44 by the capillary C. The FAB 44 , which is made of Cu that is a harder metal than Au, is thereby deformed satisfactorily and thus the initial load P 1 applied to the FAB 44 can be made to contribute to the bonding of the FAB 44 and the pad 7 M while it is suitably attenuated by the deformation of the FAB 44 .

Also, the drive current is applied to the ultrasonic transducer and thus the ultrasonic vibration propagates from the ultrasonic transducer to FAB 44 and the FAB 44 is rubbed against the pad 7 M by the ultrasonic vibration. The drive current applied to the ultrasonic transducer is controlled so that the integrated value of the drive current during the predetermined time period from the contacting of the FAB 44 with the pad 7 M is less than 162 mA·msec. Ultrasonic vibration of an appropriate energy amount is thereby made to propagate to the FAB 44 within the predetermined time period from the contacting of the FAB 44 with the pad 7 M. Consequently, the FAB 44 and the pad 7 M can be bonded satisfactorily by the ultrasonic vibration while preventing occurrence of damage of the pad 7 M and the interlayer insulating film 12 M below the pad 7 M due to excessive energy of the ultrasonic vibration.

The deformation of the FAB 44 due to the pressing of the FAB 44 against the pad 7 M ends when the predetermined time period elapses from the contacting of the FAB 44 , made of Cu, with the pad 7 M. That is, the shape of the first ball portion 15 M is completed when the predetermined time period elapses from the contacting of the FAB 44 , made of Cu, with the pad 7 M. Thus, if a large load continues to be applied to the FAB 44 thereafter, the ultrasonic vibration will not propagate satisfactorily to the portion of contact of the FAB 44 and the pad 7 M. The load applied to the FAB 44 is thus decreased after the elapse of the predetermined time period from the contacting of the FAB 44 with the pad 7 M. The ultrasonic vibration can thereby be made to propagate satisfactorily to the portion of contact of the FAB 44 and the pad 7 M.

›Example 8 · 5 of 6

Thus, by the wire bonding method according to the present preferred embodiment, satisfactory bonding of the copper wire 5 M to a pad 7 M can be realized while preventing occurrence of damage in the pad 7 M and the interlayer insulating film 12 M.

After the contacting of the FAB 44 with the pad 7 M, the value of the drive current applied to the ultrasonic transducer is increased gradually. Meanwhile, by the initial load P 1 being applied to the FAB 44 , the FAB 44 deforms in a squeezed manner and an area of the portion of contact of the FAB 44 and the pad 7 M increases gradually. The ultrasonic vibration energy propagating from the ultrasonic transducer to the FAB 44 is thereby increased gradually and the area of the FAB 44 rubbed against the pad 7 M also increases gradually. Consequently, a state of satisfactory bonding to the pad 7 M can be realized up to a peripheral edge portion of the surface of bonding of the first ball portion 15 M to the pad 7 M while suppressing occurrence of damage in the pad 7 M and the interlayer insulating film 12 M due to rapid increase of the ultrasonic vibration energy propagating to the FAB 44 below a central portion of the first ball portion 15 L.

Also, in the case where the drive current is applied to the ultrasonic transducer from before the contacting of the FAB 44 with the pad 7 M, the ultrasonic vibration propagates to the portion of contact of the FAB 44 and the pad 7 M from the instant at which the FAB 44 contacts the pad 7 M, and the contacting portion is rubbed against the pad 7 M. Consequently, a state where a central portion of a surface of the first ball portion 15 M that bonds with the pad 7 M (portion at which the FAB 44 and the pad 7 M first make contact) is satisfactorily bonded to the pad 7 M can be realized.

As a method for bonding the FAB 44 to a pad 7 M, continued application of a fixed load to the FAB 44 and continued application of a fixed drive current to the ultrasonic transducer after contacting of the FAB 44 with the pad 7 M may be considered. However, with this method, no matter what magnitude the load applied to the FAB 44 and value the drive current applied to the ultrasonic transducer are set, the FAB 44 is not adequately bonded to the pad 7 M or so-called splash, in which the material of the pad 7 M protrudes greatly outward in a form of a thin collar to sides of the first ball portion 15 M, occurs.

With the wire bonding method according to the present preferred embodiment, the occurrence of splash is prevented by the value of the drive current applied to the ultrasonic transducer from before the contacting of the FAB 44 with the pad 7 M and the magnitude of the initial load being set appropriately.

That is, the value U 1 of the drive current applied to the ultrasonic transducer from before the contacting of the FAB 44 with the pad 7 M is set to less than 30 mA. The ultrasonic vibration energy that propagates to the FAB 44 immediately after the FAB 44 contacts the pad 7 M can thereby be prevented from being excessive. Consequently, occurrence of splash and occurrence of damage in the pad 7 M and the interlayer insulating film 12 M below the central portion of the first ball portion 15 M can be prevented satisfactorily.

Also, the magnitude of the initial load P 1 is set to a value obtained by multiplying the intended bonding area of the first ball portion 15 M with respect to the pad 7 M by a fixed factor. The magnitude of the initial load P 1 can thus be set appropriately in accordance with the intended bonding area of the first ball portion 15 M. Consequently, satisfactory deformation of the FAB 44 can be achieved while satisfactorily preventing the occurrence of splash and occurrence of damage of the pad 7 M and the interlayer insulating film 12 M below the central portion of the first ball portion 15 M.

Although the thirteenth preferred embodiment of the present invention has been described above, the thirteenth preferred embodiment may also be modified as follows.

For example, although a QFN package type is applied to the semiconductor device 1 M, the present invention may also be applied to the manufacture of a semiconductor device to which another type of non-leaded package, such as an SON (small outlined non-leaded package), is applied.

Also, although with the above-described preferred embodiment, a mode in which the copper wires 5 M are covered by the water-impermeable insulating film 25 M was described as an example, the water-impermeable insulating film 25 M may be omitted as shown in FIG. 162 as long as at least the thirteenth object for resolving the thirteenth issue is achieved.

Experiments related to the present thirteenth preferred embodiment were performed. The present invention is not restricted to the examples described below.

1. Evaluation Test 1

A capillary made by Micro-Swiss was used. The capillary has the following dimensions. ACD dimension that is a diameter of a lower end edge of a chamfer is 66 μm (0.066 mm). A T dimension that is an outer diameter of a face is 178 μm (0.178 mm). A chamfer angle, which two straight lines extending along a side surface of the chamfer form in a cross section of the capillary taken along a plane that includes a central axis (see cross section shown in FIG. 160A ), is 90°. A face angle that is an angle that the face forms with a plane orthogonal to the central axis of the capillary is 8°. An angle, which, in the cross section of the capillary taken along the plane that includes the central axis, a portion of the side surface of the capillary that extends upward beyond the upper end of the face forms with the central axis, is 20°. An upper end portion of the face is arcuate and an OR dimension that is a radius of curvature of this portion is 20 μm (0.020 mm).

›Example 8 · 6 of 6

As shown in FIG. 163 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

›Example 1

In Example 1, the ramp-up time was set to 3.6 msec. In other words, 30% of the time period from the contacting of the FAB with the pad to the raising of the capillary (12 msec, hereinafter referred to as the “bonding time”) was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 147.5 mA·msec.

Comparative Example 1

In Comparative Example 1, the ramp-up time was set to 3.0 msec. In other words, 25% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 165 mA·msec.

Comparative Example 2

In Comparative Example 2, the ramp-up time was set to 2.4 msec. In other words, 20% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 207 mA·msec.

Comparative Example 3

In Comparative Example 3, the ramp-up time was set to 1.8 msec. In other words, 15% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 228 mA·msec.

Comparative Example 4

In Comparative Example 4, the ramp-up time was set to 1.2 msec. In other words, 10% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 249 mA·msec.

Comparative Example 5

In Comparative Example 5, the ramp-up time was set to 0 msec. In other words, 0% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 270 mA·msec.

(1) Crack Evaluation

With each of Example 1 and Comparative Examples 1 to 5, FABs were bonded to 48 pads, whether or not a crack formed in the interlayer insulating film at the lower layer of each pad was examined, and a crack occurrence rate (number of pads with which a crack formed in the interlayer insulating film at the lower layer/48×100) was computed. The computation results are shown in FIG. 164 .

As shown in FIG. 164 , with Example 1, with which the ramp-up time was 30% of the bonding time and the integrated value of the drive current was 147.5 mA·msec, it was confirmed that a crack did not occur in the interlayer insulating film.

On the other hand, with each of Comparative Examples 1 to 4, with which the ramp-up time was no more than 25% of the bonding time and the integrated value of the drive current was 165 mA·msec, it was confirmed that a crack occurred in the interlayer insulating film.

2. Evaluation Test 2

A capillary made by Micro-Swiss was used. The capillary has the following dimensions. The CD dimension that is the diameter of the lower end edge of the chamfer is 66 μm (0.066 mm). The T dimension that is the outer diameter of the face is 178 μm (0.178 mm). The chamfer angle, which two straight lines extending along the side surface of the chamfer form in the cross section of the capillary taken along the plane that includes the central axis (see cross section shown in FIG. 160A ), is 90°. The face angle FA that is the angle that the face forms with the plane orthogonal to the central axis of the capillary is 8°. The angle, which, in the cross section of the capillary taken along the plane that includes the central axis, the portion of the side surface of the capillary that extends upward beyond the upper end of the face forms with the central axis, is 20°. The upper end portion of the face is arcuate and the OR dimension that is the radius of curvature of this portion is 20 μm (0.020 mm).

As shown in FIG. 165 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, from before the contacting of the FAB with the pad, a drive current was applied to the ultrasonic transducer provided in the capillary, and after the FAB contacted the pad, the value of the drive current applied to the ultrasonic transducer was raised to 90 mA at a fixed rate of change in the period of 3.6 msec and the state of applying the drive current of 90 mA to the ultrasonic transducer was maintained until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary). Examples 2 to 6 and Comparative Examples 6 to 8 differ in the value of the drive current applied to the ultrasonic transducer from before the contacting of the FAB with the pad.

›Example 2

In Example 2, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 0 mA. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 112.5 mA·msec.

›Example 3

In Example 3, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 10 mA. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 130 mA·msec.

›Example 4

In Example 4, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 15 mA. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 138.75 mA·msec.

›Example 5

In Example 5, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 20 mA. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 147.5 mA·msec.

›Example 6

In Example 6, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 25 mA. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 156.25 mA·msec.

Comparative Example 6

In Comparative Example 6, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 30 mA. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 165 mA·msec.

Comparative Example 7

In Comparative Example 7, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 60 mA. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 255 mA·msec.

Comparative Example 8

In Comparative Example 8, the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was set to 90 mA. That is, the drive current applied to the ultrasonic transducer does not change before and after the contacting of the FAB with the pad. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 270 mA·msec.

(1) Crack Evaluation

With each of Examples 2 to 6 and Comparative Examples 6 to 8, FABs were bonded to 48 pads, whether or not a crack formed in the interlayer insulating film at the lower layer of each pad was examined, and a crack occurrence rate (number of pads with which a crack formed in the interlayer insulating film at the lower layer/48×100) was computed. The computation results are shown in FIG. 166 .

As shown in FIG. 166 , it was confirmed that, with each of Examples 2 to 6, with which the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was no more than 25 mA and the integrated value of the drive current was no more than 6.25 mA·msec, a crack did not occur in the interlayer insulating film.

On the other hand, it was confirmed that, with each of Comparative Examples 6 to 8, with which the value of the drive current applied to the ultrasonic transducer from before the FAB contacted the pad was no less than 30 mA and the integrated value of the drive current was no less than 255 mA·m, a crack occurred in the interlayer insulating film.

3. Evaluation Test 3

A capillary made by Micro-Swiss was used. The capillary has the following dimensions. The CD dimension that is the diameter of the lower end edge of the chamfer is 66 μm (0.066 mm). The T dimension that is the outer diameter of the face is 178 μm (0.178 mm). The chamfer angle, which two straight lines extending along the side surface of the chamfer form in the cross section of the capillary taken along the plane that includes the central axis (see cross section shown in FIG. 160A ), is 90°. The face angle FA that is the angle that the face forms with the plane orthogonal to the central axis of the capillary is 8°. The angle, which, in the cross section of the capillary taken along the plane that includes the central axis, the portion of the side surface of the capillary that extends upward beyond the upper end of the face forms with the central axis, is 20°. The upper end portion of the face is arcuate and the OR dimension that is the radius of curvature of this portion is 20 μm (0.020 mm).

The capillary was positioned at a position of 7 mil (approximately 178 μm) height from the top surface of a pad made of an Al—Cu-based alloy and an FAB of 2.33 mil (approximately 60 μm) diameter was formed on the tip of a copper wire with a wire diameter of 25 μm. The capillary was then lowered toward the pad at a speed of 0.4 mil/msec (approximately 10.2 μm/msec) to press the FAB against the pad and form a first ball portion on the pad by deformation of the FAB. The intended diameter of the first ball portion was 74 μm and the intended bonding area of the fast ball portion with respect to the pad was 0.00430 mm 2 .

As shown in FIG. 167 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, before the contacting of the FAB with the pad, a drive current was not applied to the ultrasonic transducer provided in the capillary, and after the FAB contacted the pad, the value of the drive current applied to the ultrasonic transducer was increased from 0 mA to 90 mA at a fixed rate of change and the state of applying the drive current of 90 mA to the ultrasonic transducer was maintained until the capillary was raised (until 29.5 msec elapsed from the start of descent of the capillary). Examples 7 and 8 and Comparative Examples 9 to 12 differ in a time (ramp-up time) taken for the drive current applied to the ultrasonic transducer to reach 90 mA from 0 mA.

›Example 7

In Example 7, the ramp-up time was set to 3.6 msec. In other words, 30% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 112.5 mA·msec.

›Example 8 · 1 of 6

In Example 8, the ramp-up time was set to 3.0 msec. In other words, 25% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 135 mA·msec.

Comparative Example 9

In Comparative Example 9, the ramp-up time was set to 2.4 msec. In other words, 20% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 162 mA·msec.

Comparative Example 10

In Comparative Example 10, the ramp-up time was set to 1.8 msec. In other words, 15% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 189 mA·msec.

Comparative Example 11

In Comparative Example 11, the ramp-up time was set to 1.2 msec. In other words, 10% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 216 mA·msec.

Comparative Example 12

In Comparative Example 6, the ramp-up time was set to 0 msec. In other words, 0% of the bonding time was set as the ramp-up time. In this case, the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g was applied to the FAB was 270 mA·msec.

Crack Evaluation

With each of Examples 7 and 8 and Comparative Examples 9 to 12, FABs were bonded to 48 pads, whether or not a crack formed in the interlayer insulating film at the lower layer of each pad was examined, and a crack occurrence rate (number of pads with which a crack formed in the interlayer insulating film at the lower layer/48×100) was computed. The computation results are shown in FIG. 168 .

As shown in FIG. 168 , it was confirmed that, with each of Examples 7 and 8, with which the ramp-up time was no less than 25% of the bonding time and the integrated value of the drive current was 135 mA·msec, a crack did not occur in the interlayer insulating film.

On the other hand, it was confirmed that, with each of Comparative Examples 9 to 12, with which the ramp-up time was no more than 20% of the bonding time and the integrated value of the drive current was 162 mA·m, a crack occurred in the interlayer insulating film.

From the results of evaluation tests 1 to 3, it was confirmed that a crack does not occur in the interlayer insulating film if the integrated value of the drive current applied to the ultrasonic transducer in the period of 3 msec during which the initial load of 130 g is applied to the FAB is less than 162 mA·msec.

Fourteenth Preferred Embodiment FIG. 169 to FIG. 187

By disclosure of a fourteenth preferred embodiment, a fourteenth issue concerning a fourteenth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Fourteenth Background Art

(2) Fourteenth Issue

However, an FAB formed on a tip of a copper wire is harder than an FAB formed on a tip of a gold wire, and thus if a copper wire is bonded to a pad under the same conditions (magnitudes of load and ultrasonic transducer drive current, etc.) as those for a gold wire, satisfactory bonding of the copper wire and the pad cannot be obtained. Presently, conditions that enable satisfactory bonding of a copper wire and a pad to be achieved are not clear and active replacement of gold wires by copper wires is yet to take place.

Thus, a fourteenth object of the present invention related to the fourteenth preferred embodiment is to provide a wire bonding method that enables satisfactory bonding of a copper wire to a pad to be achieved.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 169 is a schematic sectional view of a semiconductor device according to the fourteenth preferred embodiment of the present invention. FIG. 170 is a schematic bottom view of the semiconductor device shown in FIG. 169 .

The semiconductor device 1 N is a semiconductor device to which a QFN (quad flat non-leaded package) configuration is applied and has a structure in which a semiconductor chip 2 N is sealed together with a die pad 3 N, leads 4 N, and copper wires 5 N by a resin package 6 N. An outer shape of the semiconductor device 1 N (resin package 6 N) is a flat, rectangular parallelepiped shape.

›Example 8 · 2 of 6

In the present preferred embodiment, the outer shape of the semiconductor device 1 N is a hexahedron having a square shape of 4 mm square as a planar shape and a thickness of 0.85 mm, and dimensions of respective portions of the semiconductor device 1 N cited below make up an example in the case where the semiconductor device 1 N has the above outer dimensions.

The semiconductor chip 2 N has a square shape of 2.3 mm in plan view, and the semiconductor chip 2 N has a thickness of 0.23 mm. A plurality of pads 7 N are disposed at peripheral edge portions of a top surface of the semiconductor chip 2 N. Each pad 7 N is electrically connected to a circuit built into the semiconductor chip 2 N. A rear metal 8 N made of a metal layer of Au, Ni (nickel), Ag (silver), etc., is formed on a rear surface of the semiconductor chip 2 N.

The die pad 3 N and the leads 4 N are formed by punching out a metal thin plate (for example, a copper thin plate). The metal thin plate (die pad 3 or lead 4 N) has a thickness of 0.2 mm. A plating layer 9 N made of Ag is formed on top surfaces of the die pad 3 N and leads 4 N.

The die pad 3 N has a square shape of 2.7 mm in plan view and is disposed at a central portion of the semiconductor device 1 N so that its respective side surfaces are parallel to side surfaces of the semiconductor device 1 N.

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface across an entire periphery of a peripheral edge portion of the rear surface of the die pad 3 N. The resin package 6 N enters the recess. The peripheral edge portion of the die pad 3 N is thereby sandwiched from above and below by the resin package 6 N and prevention of fall-off (retaining) of the die pad 3 N with respect to the resin package 6 N is thereby achieved.

Also, with the exception of the peripheral edge portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of the die pad 3 N is exposed from a rear surface of the resin package 6 N.

An equal number of (for example, nine) leads 4 N are disposed at each of positions facing the respective side surfaces of the die pad 3 N. At each of the positions facing the side surfaces of the die pad 3 N, the leads 4 N extend in a direction orthogonal to the facing side surface and are disposed at equal intervals in a direction parallel to the side surface. A longitudinal direction length of each lead 4 N is 0.45 mm. Also, an interval between the die pad 3 N and the lead 4 N is 0.2 mm.

A recess with a substantially quarter-elliptical shape in cross section is formed by performing a squeezing process from the rear surface at a die pad 3 N side end portion of the rear surface of each lead 4 N. The resin package 6 N enters the recess. The die pad 3 N side end portion of the lead 4 N is thereby sandwiched from above and below by the resin package 6 N and prevention of fall-off (retaining) of the lead 4 N with respect to the resin package 6 N is thereby achieved.

With the exception of the die pad 3 N side end portion (portion recessed to the substantially quarter-elliptical shape in cross section), the rear surface of each lead 4 N is exposed from a rear surface of the resin package 6 N. Also, a side surface of the lead 4 N facing the die pad 3 N side is exposed from a side surface of the resin package 6 N.

A plating layer 10 N formed of solder is formed on portions of the rear surfaces of the die pad 3 N and leads 4 N that are exposed from the resin package 6 N.

With its top surface with the pads 7 N disposed thereon facing upward, the semiconductor chip 2 N has its rear surface bonded via a bonding material 11 N to the top surface (plating layer 10 N) of the die pad 3 N. For example, a solder paste is used as the bonding material 11 N. The bonding material 11 N has a thickness of 0.02 mm.

In a case where electrical connection of the semiconductor chip 2 N and the die pad 3 N is unnecessary, the rear metal 8 N may be omitted and the rear surface of the semiconductor chip 2 N may be bonded to the top surface of the die pad 3 N via a bonding material made of silver paste or other insulating paste. In this case, the planar size of the semiconductor chip 2 N is 2.3 mm square. Also, the plating layer 9 N on the top surface of the die pad 3 N may be omitted.

The copper wires 5 N are made, for example, of copper with a purity of no less than 99.99%. One end of each copper wire 5 N is bonded to a pad 7 N of the semiconductor chip 2 N. The other end of the copper wire 5 N is bonded to the top surface of a lead 4 N. The copper wire 5 N is installed so as to form an arch-shaped loop between the semiconductor chip 2 N and the lead 4 N. A height difference between an apex portion of the loop of the copper wire 5 N and the top surface of the semiconductor chip 2 N is 0.16 mm.

As in the first preferred embodiment, in the semiconductor device 1 N, the entire top surface and side surfaces of the semiconductor chip 2 N, the entire top surface and side surfaces of the die pad 3 N, entire top surfaces of the leads 4 N, and the entire copper wires 5 N are covered by an integral water-impermeable insulating film 25 N.

FIG. 171 is an enlarged view of a portion surrounded by broken lines shown in FIG. 169 .

Each pad 7 N is made of a metal that contains Al and is formed on an uppermost interlayer insulating film 12 N of the semiconductor chip 2 N. A top surface protective film 13 N is formed on the interlayer insulating film 12 N. The pad 7 N has its peripheral edge portion covered by the top surface protective film 13 N and its central portion is exposed via a pad opening 14 N formed in the top surface protective film 13 N.

The copper wire 5 N is bonded to the central portion of the pad 7 N exposed from the top surface protective film 13 N. As shall be described below, the copper wire 5 N has an FAB formed at its tip and the FAB is pressed against and thereby bonded to the pad 7 N. In this process, the FAB deforms to form a first ball portion 15 N with a stepped disk shape at the portion of bonding of the copper wire 5 N with the pad 7 N. Also, at a periphery of the first ball portion 15 N, the material of the pad 7 N juts out gradually from below the first ball portion 15 N so as to form a jutting portion 16 N without it being lifted greatly from the top surface of the pad 7 N.

›Example 8 · 3 of 6

For example, in a case where the copper wire 5 N has a wire diameter of 25 μm, an intended diameter of the first ball portion 15 N (designed diameter of the first ball portion 15 N) is 76 μm, and an intended thickness of the first ball portion 15 N (designed thickness of the first ball portion 15 N) is 17 μm.

FIG. 172A to FIG. 172D are schematic sectional views for describing a method for manufacturing the semiconductor device according to the fourteenth preferred embodiment of the present invention in order of process.

The copper wires 5 N are installed across the semiconductor chip 2 N and the leads 4 N by a wire bonder in a state where the die pad 3 N and the leads 4 N are connected to a frame (not shown) that surrounds these components, that is, in a state where the die pad 3 N and leads 4 N make up a lead frame.

The wire bonder includes a capillary C. As shown in FIG. 172A , the capillary C has a substantially cylindrical shape with a wire insertion hole 41 N formed along a central axis. The copper wire 5 N is inserted through the wire insertion hole 41 N and fed out from a tip (lower end) of the wire insertion hole 41 N.

A chamfer 42 N of truncated conical shape that is in communication with the wire insertion hole 41 N is formed below the wire insertion hole 41 N at a tip portion of the capillary C. Also, the tip portion of the capillary C has a face 43 N that is continuous with a lower end edge of the chamfer 42 N and is a surface that faces a pad 7 N and a lead 4 N during bonding (during wire bonding) of the copper wire 5 N to these components. An outer side of the face 43 N is gradually inclined upwardly with respect to a plane orthogonal to the central axis of the capillary C.

First, as shown in FIG. 172A , the capillary C is moved to a position directly above the pad 7 N. Next, in a state where a tip of the copper wire 5 N is positioned at the chamfer 42 N, a current is applied to a tip portion of the copper wire 5 N and an FAB 44 is thereby formed at the tip portion. The value and application time of the current are set suitably in accordance with the wire diameter of the copper wire 5 N and an intended diameter of the FAB 44 (designed diameter of the FAB 44 ). A portion of the FAB 44 protrudes below the chamfer 42 N.

Thereafter, as shown in FIG. 172B , the capillary C is lowered toward the pad 7 N and the FAB 44 is pressed against the pad 7 N by the capillary C. In this process, a load is applied to the FAB 44 by the capillary C and ultrasonic vibration, emitted from an ultrasonic transducer (not shown) provided in the capillary C, is applied to the FAB 44 .

FIG. 173 is a graph of changes with time of the load applied to the FAB and a driving current applied to the ultrasonic transducer during the bonding of the FAB to the pad.

For example, as shown in FIG. 173 , a relatively large initial load P 1 is applied from the capillary C to the FAB 44 from a time T 1 at which the FAB 44 contacts the pad 7 N to a time T 2 after elapse of a predetermined time period. The predetermined time period is set, for example, to 3 msec. Also, the initial load P 1 is set based on a value obtained by multiplying an intended bonding area of the first ball portion 15 N with respect to the pad 7 N (designed bonding area of the first ball portion 15 N with respect to the pad 7 ) by a fixed factor (for example, 28786 in a case where the unit of the initial load P 1 is g and the unit of the bonding area is mm 2 ). From the time T 2 onward, the load applied to the FAB 44 from the capillary C is lowered and a relatively small load P 2 is applied to the FAB 44 . The load P 2 is applied continuously until a time T 4 at which the capillary C is raised.

Meanwhile, when the FAB 44 contacts the pad 7 N, supplying of a drive current to the ultrasonic transducer is started, and from that time T 1 to a time T 3 , the value of the drive current is raised at a fixed rate of change (monotonously) to a value U. The value U of the drive current applied to the ultrasonic transducer from the time T 3 onward is set so that a value obtained by dividing the value U by the intended bonding area of the first ball portion 15 N is no more than 0.0197 mA/μm 2 . Thereafter, the drive current of the value U continues to be applied to the ultrasonic transducer until a time T 4 .

Consequently, the FAB 44 deforms along the shapes of the chamfer 42 N and the face 43 N of the capillary C, and the first ball portion 15 N with a stepped disk shape is formed on the pad 7 N with the jutting portion 16 N being formed along its periphery as shown in FIG. 171 . Bonding (first bonding) of the copper wire 5 N with the pad 7 N is thereby achieved. When the time T 4 arrives upon elapse of a bonding time determined in advance from the time T 1 , the capillary C separates upwardly from the pad 7 N. Thereafter, the capillary C is moved obliquely downward toward the top surface of the lead 4 N. Then, as shown in FIG. 172C , the drive current is applied to the ultrasonic transducer, and while ultrasonic vibration is being applied to the capillary C, the copper wire 5 N is pressed against the top surface of the lead 4 N by the capillary C and then broken. A stitch portion with a wedge shape in side view that is made up of the other end portion of the copper wire 5 N is thereby formed on the top surface of the lead 4 N and the bonding (second bonding) of the copper wire with respect to the lead 4 N is thereby achieved.

Thereafter, the processes shown in FIG. 172A to FIG. 172C are performed on another pad 7 N and the corresponding lead 4 N. By the processes shown in FIG. 172A to FIG. 172C then being repeated, copper wires 5 N are installed across all pads 7 N of the semiconductor chip 2 N and the leads 4 N as shown in FIG. 172D . After the end of all of the wire bonding, the water-impermeable insulating film 25 N is formed by the same method as that of FIG. 4D .

The following tests 1 to 3 were performed to appropriately set the predetermined time period during which the initial load P 1 is applied to an FAB.

›Example 8 · 4 of 6

(1) Test 1

An FAB 44 was formed at a tip of a copper wire 5 N of 25 μm wire diameter, the capillary C was lowered toward a pad 7 N, the FAB 44 was pressed against the pad 7 N, and a fixed load was applied to the FAB 44 to form a first ball portion 15 N on the pad 7 N by deformation of the FAB 44 . The intended diameter of the first ball portion 15 N was 58 μm and the intended thickness thereof was 10 μm. For each of cases where the magnitude of the load applied to the FAB 44 was set to 50 g, 80 g, and 110 g, changes of the diameter and the thickness of the first ball portion 15 N with time elapsed from the contacting of the FAB 44 with the pad 7 N were examined. Changes with time of the diameter (ball diameter) are shown in FIG. 174 , and changes with time of the thickness (ball thicknesses) are shown in FIG. 175 .

(2) Test 2

An FAB 44 was formed at a tip of a copper wire 5 N of 25 μm wire diameter, the capillary C was lowered toward a pad 7 N, the FAB 44 was pressed against the pad 7 N, and a fixed load was applied to the FAB 44 to form a first ball portion 15 N on the pad 7 N by deformation of the FAB 44 . The intended diameter of the first ball portion 15 N was 76 μm and the intended thickness thereof was 18 μm. For each of cases where the magnitude of the load applied to the FAB 44 was set to 70 g, 90 g, 110 g, 130 g, 150 g, and 200 g, changes of the diameter and the thickness of the first ball portion 15 N with time elapsed from the contacting of the FAB 44 with the pad 7 N were examined. Changes with time of the diameter (ball diameter) are shown in FIG. 176 , and changes with time of the thickness (ball thicknesses) are shown in FIG. 177 .

(3) Test 3

An FAB 44 was formed at a tip of a copper wire 5 N of 38 μm wire diameter, the capillary C was lowered toward a pad 7 N, the FAB 44 was pressed against the pad 7 N, and a fixed load was applied to the FAB 44 to form a first ball portion 15 N on the pad 7 N by deformation of the FAB 44 . The intended diameter of the first ball portion 15 N was 104 μm and the intended thickness thereof was 25 μm. For each of cases where the magnitude of the load applied to the FAB 44 was set to 200 g, 230 g, 250 g, 300 g, 400 g, and 500 g, changes of the diameter and the thickness of the first ball portion 15 N with time elapsed from the contacting of the FAB 44 with the pad 7 N were examined. Changes with time of the diameter (ball diameter) are shown in FIG. 178 , and changes with time of the thickness (ball thicknesses) are shown in FIG. 179 .

As can be understood from reference to FIG. 174 to FIG. 179 , regardless of the wire diameter of the copper wire 5 N, the magnitude of the load, and the intended diameter and intended thickness of the first ball portion 15 N, the deformation of the FAB 44 is not completed in less than 2 msec from contact with the pad 7 N. On the other hand, it is considered that, beyond 4 msec from the contacting of the FAB 44 with the pad 7 N, the diameter and thickness of the FAB 44 are substantially unchanged and the deformation of the FAB 44 is reliably completed. To be more detailed, it is considered that, regardless of the wire diameter of the copper wire 5 N, the magnitude of the load, and the intended diameter and intended thickness of the first ball portion 15 N, the changes of the diameter and thickness of the FAB 44 are ended and the deformation of the FAB 44 is completed at a point of elapse of substantially 3 msec from the contacting of the FAB 44 with the pad 7 N.

It is thus considered that the predetermined time period during which the initial load P 1 is applied to an FAB is appropriately in a range of 2 to 4 msec and is more appropriately 3 msec.

As described above, after the FAB 44 formed on the tip of the copper wire 5 N is put in contact with a pad, a load is applied to the FAB 44 by the capillary C. Also, in parallel, a drive current is applied to the ultrasonic transducer provided in the capillary C. Thus, while the FAB 44 is deformed by the load, the FAB is rubbed against the pad 7 N by the ultrasonic vibration propagating from the ultrasonic transducer.

The value of the drive current applied to the ultrasonic transducer after elapse of the predetermined time period from the contacting of the FAB 44 with the pad 7 N is set so that the value obtained by dividing the drive current value by the intended bonding area of the first ball portion 15 N is no more than 0.0197 mA/μm 2 . Application of ultrasonic vibration of an excessive energy amount to the FAB 44 after the predetermined time period from the contacting of the FAB 44 with the pad 7 N can thereby be prevented.

Satisfactory bonding of the copper wire 5 N (FAB 44 ) to the pad 7 N can thereby be achieved while preventing occurrence of crack or other damage in the pad 7 N and the interlayer insulating film 12 N below the pad 7 N due to excessive energy of the ultrasonic vibration.

The deformation of the FAB 44 due to the load ends within 3 msec from the contacting of the FAB 44 with the pad 7 N. That is, the shape of the FAB 44 after completion of bonding (first ball portion) is completed within 3 msec from the contacting of the FAB 44 with the pad 7 N. When the deformation of the FAB 44 ends, the ultrasonic vibration applied to the FAB 44 propagates to the bonding portion of the FAB 44 and the pad 7 N substantially without attenuation. Thus, when ultrasonic vibration of an excessive energy amount is applied to the FAB 44 after the end of deformation of the FAB 44 , crack or other damage may occur in the pad 7 N or the interlayer insulating film 12 N below a peripheral edge portion of the first ball portion 15 N.

The predetermined time period is thus set to the time period from the point of contacting of the FAB 44 with the pad 7 N to the point at which the deformation of the FAB 44 ends substantially, that is, to 3 msec. Occurrence of damage in the pad 7 N or the interlayer insulating film 12 N below the peripheral edge portion of the first ball portion 15 N can thereby be prevented.

›Example 8 · 5 of 6

Also, if the large initial load P 1 continues to be applied to the first ball portion 15 N after completion of the shape of the first ball portion 15 N, the ultrasonic vibration will not propagate satisfactorily to the portion of contact of the first ball portion 15 N and the pad 7 N.

Thus, when the predetermined time period elapses from the contacting of the FAB 44 with the pad 7 N, the load applied to the FAB 44 by the capillary C is decreased from the initial load P 1 to the lower load P 2 . By the relatively large initial load P 1 being applied to the FAB 44 after contacting of the FAB 44 with the pad 7 N, the FAB 44 , which is made of Cu that is a harder metal than Au, can be deformed satisfactorily. When the predetermined time period elapses from the contacting of the FAB 44 with the pad 7 N, the load applied to the FAB 44 is decreased to the load P 2 and thus the ultrasonic vibration can be made to propagate satisfactorily to the portion of contact of the FAB 44 (first ball portion 15 N) and the pad 7 N.

The magnitude of the initial load P 1 is preferably set based on a value obtained by multiplying the intended bonding area of the first ball portion 15 N with respect to the pad 7 N by a fixed factor. The magnitude of the initial load P 1 can thereby be set appropriately in accordance with the intended bonding area of the first ball portion 15 N. Consequently, satisfactory deformation of the FAB 44 can be achieved while satisfactorily preventing the occurrence of damage in the pad 7 N and the interlayer insulating layer 12 N below the central portion of the first ball portion 15 N.

After the FAB 44 contacts the pad 7 N, the value of the drive current applied to the ultrasonic transducer is increased gradually at the fixed rate of change. Meanwhile, the load is applied to the FAB so that the FAB 44 deforms in a squeezed manner and an area of the portion of contact of the FAB 44 and the pad 7 N increases gradually. The ultrasonic vibration energy propagating from the ultrasonic transducer to the FAB 44 is thereby increased gradually and the area of the FAB 44 rubbed against the pad 7 N also increases gradually. Consequently, a state of satisfactory bonding to the pad 7 N can be realized up to the peripheral edge portion of the surface of bonding of the first ball portion 15 N to the pad 7 N while suppressing occurrence of damage in the pad 7 N and the interlayer insulating film 12 N due to rapid increase of the ultrasonic vibration energy propagating to the FAB 44 below a central portion of the first ball portion 15 N.

Although the fourteenth preferred embodiment of the present invention has been described above, the fourteenth preferred embodiment may also be modified as follows.

For example, although a QFN package type is applied to the semiconductor device 1 N, the present invention may also be applied to the manufacture of a semiconductor device to which another type of non-leaded package, such as an SON (small outlined non-leaded package), is applied.

Also, although with the above-described preferred embodiment, a mode in which the copper wires 5 N are covered by the water-impermeable insulating film 25 N was described as an example, the water-impermeable insulating film 25 N may be omitted as shown in FIG. 180 as long as at least the fourteenth object for resolving the fourteenth issue is achieved.

Next, experiments related to the present fourteenth preferred embodiment were performed. In addition, the present invention is not restricted to the examples described below.

1. Evaluation Test 1

A capillary made by Micro-Swiss was used. The capillary has the following dimensions. The CD dimension that is the diameter of the lower end edge of the chamfer is 66 μm (0.066 mm). The T dimension that is the outer diameter of the face is 178 μm (0.178 mm). The chamfer angle, which two straight lines extending along the side surface of the chamfer form in a cross section of the capillary taken along the plane that includes the central axis (see cross section shown in FIG. 172A ), is 90°. The face angle that is the angle that the face forms with the plane orthogonal to the central axis of the capillary is 8°. The angle, which, in the cross section of the capillary taken along the plane that includes the central axis, the portion of the side surface of the capillary that extends upward beyond the upper end of the face forms with the central axis, is 20°. The upper end portion of the face is arcuate and the OR dimension that is the radius of curvature of this portion is 20 μm (0.020 mm).

The capillary was positioned at a position of 7 mil (approximately 178 μm) height from a top surface of a pad made of an Al—Cu-based alloy and an FAB of 45 μm diameter was formed on a tip of a copper wire with a wire diameter of 25 μm. The capillary was then lowered toward the pad at a speed of 0.4 mil/msec (approximately 10.2 μm/msec) to press the FAB against the pad and form a first ball portion on the pad by deformation of the FAB. The intended diameter of the first ball portion was 60 μm, the intended thickness of the first ball portion was 13 μm, and the intended bonding area of the first ball portion with respect to the pad was 2826 μm 2 .

As shown in FIG. 181 , for 3 msec after contacting of the FAB with the pad, an initial load of 80 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

›Example 8 · 6 of 6

Also, supplying of the drive current to the ultrasonic transducer provided in the capillary was started when the FAB contacted the pad, and thereafter, the value of the drive current was raised to a predetermined value at a fixed rate of change in a period of 3.6 msec and then a state of applying the drive current of the predetermined value to the ultrasonic transducer was maintained until the capillary was raised (for 8.4 msec). Examples 1 to 3 and Comparative Examples 1 to 4 differ in the predetermined value that is the value of the drive current applied to the ultrasonic transducer in the final stage.

›Example 1

In Example 1, the predetermined value was set to 40 mA.

›Example 2

In Example 2, the predetermined value was set to 50 mA.

›Example 3

In Example 3, the predetermined value was set to 60 mA.

Comparative Example 1

In Comparative Example 1, the predetermined value was set to 70 mA.

Comparative Example 2

In Comparative Example 2, the predetermined value was set to 80 mA.

Comparative Example 3

In Comparative Example 3, the predetermined value was set to 90 mA.

Comparative Example 4

In Comparative Example 4, the predetermined value was set to 100 mA.

With each of Examples 1 to 3 and Comparative Examples 1 to 4, FABs were bonded to 84 pads, whether or not a crack formed in the interlayer insulating film at the lower layer of each pad was examined, and a crack occurrence rate (number of pads with which a crack formed in the interlayer insulating film at the lower layer/84×100) was computed. The computation results are shown in FIG. 182 .

As shown in FIG. 182 , it was confirmed that, with each of Examples 1 to 3, with which the predetermined value was no more than 60 mA and the value obtained by dividing the predetermined value by the intended bonding area of the first ball portion was no more than 0.0212 mA/μm 2 , a crack did not occur in the interlayer insulating film.

On the other hand, it was confirmed that, with each of Comparative Examples 1 to 4, with which the predetermined value was no less than 70 mA and the value obtained by dividing the predetermined value by the intended bonding area of the first ball portion was no less than 0.0248 mA/μm 2 , a crack occurred in the interlayer insulating film.

2. Evaluation Test 2

A capillary made by Micro-Swiss was used. The capillary has the following dimensions. The CD dimension that is the diameter of the lower end edge of the chamfer is 66 μm (0.066 mm). The T dimension that is the outer diameter of the face is 178 μm (0.178 mm). The chamfer angle, which two straight lines extending along the side surface of the chamfer form in a cross section of the capillary taken along the plane that includes the central axis (see cross section shown in FIG. 172A ), is 90°. The face angle FA that is the angle that the face forms with the plane orthogonal to the central axis of the capillary is 8°. The angle, which, in the cross section of the capillary taken along the plane that includes the central axis, the portion of the side surface of the capillary that extends upward beyond the upper end of the face forms with the central axis, is 20°. The upper end portion of the face is arcuate and the OR dimension that is the radius of curvature of this portion is 20 μm (0.020 mm).

The capillary was positioned at a position of 7 mil (approximately 178 μm) height from a top surface of a pad made of an Al—Cu-based alloy and an FAB of 59 μm diameter was formed on a tip of a copper wire with a wire diameter of 30 μm (or a wire diameter of 25 μm). The capillary was then lowered toward the pad at a speed of 0.4 mil/msec (approximately 10.2 μm/msec) to press the FAB against the pad and form a first ball portion on the pad by deformation of the FAB. The intended diameter of the first ball portion was 76 μm, the intended thickness of the first ball portion was 17 μm, and the intended bonding area of the first ball portion with respect to the pad was 4534.16 μm 2 .

As shown in FIG. 183 , for 3 msec after contacting of the FAB with the pad, an initial load of 130 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, supplying of the drive current to the ultrasonic transducer provided in the capillary was started when the FAB contacted the pad, and thereafter, the value of the drive current was raised to a predetermined value at a fixed rate of change in a period of 3.6 msec and then a state of applying the drive current of the predetermined value to the ultrasonic transducer was maintained until the capillary was raised (for 8.4 msec). Examples 4 and 5 and Comparative Examples 5 to 9 differ in the predetermined value that is the value of the drive current applied to the ultrasonic transducer in the final stage.

›Example 4

In Example 4, the predetermined value was set to 90 mA.

›Example 5

In Example 5, the predetermined value was set to 100 mA.

Comparative Example 5

In Comparative Example 5, the predetermined value was set to 110 mA.

Comparative Example 6

In Comparative Example 6, the predetermined value was set to 120 mA.

Comparative Example 7

In Comparative Example 7, the predetermined value was set to 130 mA.

Comparative Example 8

In Comparative Example 8, the predetermined value was set to 140 mA.

Comparative Example 9

In Comparative Example 9, the predetermined value was set to 150 mA.

With each of Examples 4 and 5 and Comparative Examples 5 to 9, FABs were bonded to 84 pads, whether or not a crack formed in the interlayer insulating film at the lower layer of each pad was examined, and a crack occurrence rate (number of pads with which a crack formed in the interlayer insulating film at the lower layer/84×100) was computed. The computation results are shown in FIG. 184 .

As shown in FIG. 184 , it was confirmed that, with each of Examples 4 and 5, with which the predetermined value was no more than 100 mA and the value obtained by dividing the predetermined value by the intended bonding area of the first ball portion was no more than 0.0221 mA/μm 2 , a crack did not occur in the interlayer insulating film.

On the other hand, it was confirmed that, with each of Comparative Examples 5 to 9, with which the predetermined value was no less than 110 mA and the value obtained by dividing the predetermined value by the intended bonding area of the first ball portion was no less than 0.0243 mA/μm 2 , a crack occurred in the interlayer insulating film.

3. Evaluation Test 3

A capillary made by Micro-Swiss was used. The capillary has the following dimensions. The CD dimension that is the diameter of the lower end edge of the chamfer is 66 μm (0.066 mm). The T dimension that is the outer diameter of the face is 178 μm (0.178 mm). The chamfer angle, which two straight lines extending along the side surface of the chamfer form in a cross section of the capillary taken along the plane that includes the central axis (see cross section shown in FIG. 172A ), is 90°. The face angle that is the angle that the face forms with the plane orthogonal to the central axis of the capillary is 8°. The angle, which, in the cross section of the capillary taken along the plane that includes the central axis, the portion of the side surface of the capillary that extends upward beyond the upper end of the face forms with the central axis, is 20°. The upper end portion of the face is arcuate and the OR dimension that is the radius of curvature of this portion is 20 μm (0.020 mm).

The capillary was positioned at a position of 7 mil (approximately 178 μm) height from a top surface of a pad made of an Al—Cu-based alloy and an FAB of 45 μm diameter was formed on a tip of a copper wire with a wire diameter of 38 μm. The capillary was then lowered toward the pad at a speed of 0.4 mil/msec (approximately 10.2 μm/msec) to press the FAB against the pad and form a first ball portion on the pad by deformation of the FAB. The intended diameter of the first ball portion was 104 μm, the intended thickness of the first ball portion was 24 μm, and the intended bonding area of the first ball portion with respect to the pad was 8490.56 μm 2 .

As shown in FIG. 185 , for 3 msec after contacting of the FAB with the pad, an initial load of 240 g was applied to the FAB by the capillary, and at the point of elapse of the 3 msec, the load applied to the FAB was decreased to 30 g and the state of applying the load of 30 g to the FAB was maintained for 9 msec. Thereafter, the capillary was raised.

Also, supplying of the drive current to the ultrasonic transducer provided in the capillary was started when the FAB contacted the pad, and thereafter, the value of the drive current was raised to a predetermined value at a fixed rate of change in a period of 3.6 msec and then a state of applying the drive current of the predetermined value to the ultrasonic transducer was maintained until the capillary was raised (for 8.4 msec). Examples 6 to 8 and Comparative Examples 10 to 13 differ in the predetermined value that is the value of the drive current applied to the ultrasonic transducer in the final stage.

›Example 6

In Example 6, the predetermined value was set to 90 mA.

›Example 7

In Example 7, the predetermined value was set to 150 mA.

›Example 8 · 1 of 2

In Example 8, the predetermined value was set to 160 mA.

Comparative Example 10

In Comparative Example 10, the predetermined value was set to 170 mA.

Comparative Example 11

In Comparative Example 11, the predetermined value was set to 180 mA.

Comparative Example 12

In Comparative Example 12, the predetermined value was set to 190 mA.

Comparative Example 13

In Comparative Example 13, the predetermined value was set to 200 mA.

With each of Examples 6 to 8 and Comparative Examples 10 to 13, FABs were bonded to 84 pads, whether or not a crack formed in the interlayer insulating film at the lower layer of each pad was examined, and a crack occurrence rate (number of pads with which a crack formed in the interlayer insulating film at the lower layer/84×100) was computed. The computation results are shown in FIG. 186 .

As shown in FIG. 186 , it was confirmed that, with each of Examples 1 to 3, with which the predetermined value was no more than 160 mA and the value obtained by dividing the predetermined value by the intended bonding area of the first ball portion was no more than 0.0188 mA/μm 2 , a crack did not occur in the interlayer insulating film.

On the other hand, it was confirmed that, with each of Comparative Examples 1 to 4, with which the predetermined value was no less than 170 mA and the value obtained by dividing the predetermined value by the intended bonding area of the first ball portion was no less than 0.0200 mA/μm 2 , a crack occurred in the interlayer insulating film.

FIG. 187 shows a plot of the values of the drive current applied to the ultrasonic transducer in Examples 3, 5, and 8 on a graph area having the intended bonding area of the first ball portion as the X axis and the drive current of the ultrasonic transducer as the Y axis, and it was confirmed that there is a proportional relationship expressed by y=0.0197× between the intended bonding area and the value of the drive current of the ultrasonic transducer.

Fifteenth Preferred Embodiment FIG. 188 to FIG. 203

By disclosure of a fifteenth preferred embodiment, a fifteenth issue concerning a fifteenth background art described below can be resolved in addition to the issues described above in the “OBJECT(S) OF THE INVENTION.”

(1) Fifteenth Background Art

(2) Fifteenth Issue

However, an FAB formed on a tip of a copper wire is harder than an FAB formed on a tip of a gold wire, and thus if a copper wire is bonded to a pad under the same conditions (magnitudes of load and ultrasonic transducer drive current, etc.) as those for a gold wire, satisfactory bonding of the copper wire and the pad cannot be obtained. Presently, conditions that enable satisfactory bonding of a copper wire and a pad to be achieved are not clear and active replacement of gold wires by copper wires is yet to take place.

Thus, a fifteenth object of the present invention related to the fifteenth preferred embodiment is to provide a wire bonding method that enables satisfactory bonding of a copper wire to a pad to be achieved.

(3) Disclosure of a Specific Preferred Embodiment

FIG. 188 is a schematic sectional view of a semiconductor device according to the fifteenth preferred embodiment of the present invention. FIG. 189 is a schematic bottom view of the semiconductor device shown in FIG. 188 .

The semiconductor device 1 P is a semiconductor device to which a QFN (quad flat non-leaded package) configuration is applied and has a structure in which a semiconductor chip 2 P is sealed together with a die pad 3 P, leads 4 P, and copper wires 5 P by a resin package 6 P. An outer shape of the semiconductor device 1 P (resin package 6 P) is a flat, rectangular parallelepiped shape.

In the present preferred embodiment, the outer shape of the semiconductor device 1 P is a hexahedron having a square shape of 4 mm square as a planar shape and a thickness of 0.85 mm, and dimensions of respective portions of the semiconductor device 1 P cited below make up an example in the case where the semiconductor device 1 P has the above outer dimensions.

The semiconductor chip 2 P has a square shape of 2.3 mm in plan view, and the semiconductor chip 2 P has a thickness of 0.23 mm. A plurality of pads 7 P are disposed at peripheral edge portions of a top surface of the semiconductor chip 2 P. Each pad 7 P is electrically connected to a circuit built into the semiconductor chip 2 P. A rear metal 8 P made of a metal layer of Au, Ni (nickel), Ag (silver), etc., is formed on a rear surface of the semiconductor chip 2 P.

›Example 8 · 2 of 2

The die pad 3 P and the leads 4 P are formed by punching out a metal thin plate (for example, a copper thin plate). The metal thin plate (die pad 3 or lead 4 P) has a thickness of 0.2 mm. A plating layer 9 P made of Ag is formed on top surfaces of the die pad 3 P and leads 4 P.

The die pad

›Tables in the description — 9

TABLE 1

	Section-	Wiring/		Number of
	al struc-	bond	Pad thickness	defective
	tural	region	(Å)	items
	diagram	(%)	28000	15000	5000	(pads)
Example 1	See FIG.	26.8	0	0	0	0
Example 2	43	26.8	0	0	0	0
Example 3		26.8	0	0	0	0
Comparative		100	10	10	11	31
Example 1
Comparative		85.9	5	0	4	9
Example 2
Comparative		85.9	1	0	2	3
Example 3
Comparative		100	0	0	1	1
Example 4
Comparative		100	2	1	4	7
Example 5
Comparative		100	0	1	5	6
Example 6

TABLE 2 — Variation of volume V (%)

	Diameter	Diameter	Thickness	Volume V	AVE	AVE − V	(AVE − V)/
Cycle	Dx (μm)	Dy (μm)	Tz (μm)	(μm 3 )	(μm 3 )	(μm 3 )	AVE × 100
Example 1
1	74.1	75.1	15.0	83449.4	84513.0	1063.6	1.26
2	71.5	72.5	15.5	80348.1	84513.0	4164.9	4.98
3	78.0	76.5	13.5	80554.5	84513.0	3958.5	4.68
4	73.0	75.5	15.0	82672.5	84513.0	1840.5	2.18
5	72.5	77.0	15.5	86528.8	84513.0	2015.7	2.39
6	72.0	76.0	14.5	79344.0	84513.0	5169.0	6.12
7	73.5	73.5	15.5	83734.9	84513.0	778.2	0.92
8	74.5	74.0	15.5	85451.5	84513.0	938.5	1.11
9	75.5	74.5	15.0	84371.3	84513.0	141.8	0.17
10	74.0	75.0	15.5	86025.0	84513.0	1512.0	1.79
11	74.0	76.5	15.0	84915.0	84513.0	402.0	0.48
12	75.0	75.0	15.0	84375.0	84513.0	138.0	0.16
13	76.0	74.5	16.0	90592.0	84513.0	6079.0	7.19
14	73.0	77.0	15.5	87125.5	84513.0	2612.5	3.09
15	74.5	74.0	16.0	88208.0	84513.0	3695.0	4.37
Total of volumes V (μm 3 )	1267695.4
Average AVE of volumes V (μm 3 )	84513.0
Example 2
1	75.2	77.1	16.9	97762.8	97765.4	2.6	0.00
2	74.0	76.5	16.5	93406.5	97765.4	4358.9	4.46
3	74.0	76.5	15.0	84915.0	97765.4	12850.4	13.14
4	74.5	76.5	17.0	96887.3	97765.4	878.2	0.90
5	76.5	75.0	18.0	103275.0	97765.4	5509.6	5.64
6	78.0	77.0	17.0	102102.0	97765.4	4336.6	4.44
7	76.5	77.0	17.5	103083.8	97765.4	5318.3	5.44
8	75.0	77.0	17.5	101062.5	97765.4	3297.1	3.37
9	75.5	78.5	15.5	91864.6	97765.4	5900.8	6.04
10	74.0	78.0	17.5	101010.0	97765.4	3244.6	3.32
11	75.5	78.0	17.0	100113.0	97765.4	2347.6	2.40
12	74.5	77.0	17.0	97520.5	97765.4	244.9	0.25
13	74.0	76.5	17.0	96237.0	97765.4	1528.4	1.56
14	75.5	78.5	16.5	97791.4	97765.4	26.0	0.03
15	75.0	78.0	17.0	99450.0	97765.4	1684.6	1.72
Total of volumes V (μm 3 )	1466481.3
Average AVE of volumes V (μm 3 )	97765.4

TABLE 3 — Variation of volume V (%)

	Diameter	Diameter	Thickness	Volume V	AVE	AVE − V	(AVE − V)/
Cycle	Dx (μm)	Dy (μm)	Tz (μm)	(μm 3 )	(μm 3 )	(μm 3 )	AVE × 100
Example 3
1	74.9	77.6	16.7	96985.8	96945.8	39.9	0.04
2	73.5	80.0	15.0	88200.0	96945.8	8745.8	9.02
3	74.5	74.5	17.5	97129.4	96945.8	183.5	0.19
4	74.0	79.5	17.0	100011.0	96945.8	3065.2	3.16
5	74.0	78.0	15.5	89466.0	96945.8	7479.8	7.72
6	76.0	76.0	17.0	98192.0	96945.8	1246.2	1.29
7	72.0	78.0	17.0	95472.0	96945.8	1473.8	1.52
8	78.0	77.0	16.5	99099.0	96945.8	2153.2	2.22
9	74.0	76.5	16.5	93406.5	96945.8	3539.3	3.65
10	76.5	75.0	17.0	97537.5	96945.8	591.7	0.61
11	75.0	78.5	16.0	94200.0	96945.8	2745.8	2.83
12	79.0	76.5	16.5	99717.8	96945.8	2771.9	2.86
13	73.5	79.0	16.0	92904.0	96945.8	4041.8	4.17
14	75.0	78.5	17.5	103031.3	96945.8	6085.4	6.28
15	74.0	79.5	18.5	108835.5	96945.8	11889.7	12.26
Total of volumes V (μm 3 )	1454187.6
Average AVE of volumes V (μm 3 )	96945.8
Example 4
1	75.3	77.9	17.8	104460.8	104490.3	29.4	0.03
2	75.0	75.5	17.5	99093.8	104490.3	5396.5	5.16
3	74.5	78.0	17.5	101692.5	104490.3	2797.8	2.68
4	74.0	79.5	17.5	102952.5	104490.3	1537.8	1.47
5	75.0	75.0	18.0	101250.0	104490.3	3240.3	3.10
6	77.0	79.0	18.0	109494.0	104490.3	5003.7	4.79
7	76.0	78.0	18.0	106704.0	104490.3	2213.7	2.12
8	78.5	80.0	18.5	116180.0	104490.3	11689.7	11.19
9	75.0	78.5	18.5	108918.8	104490.3	4428.5	4.24
10	72.5	79.0	17.5	100231.3	104490.3	4259.0	4.08
11	75.0	78.0	17.5	102375.0	104490.3	2115.3	2.02
12	75.5	77.0	17.0	98829.5	104490.3	5660.8	5.42
13	74.5	78.0	18.0	104595.0	104490.3	107.7	0.10
14	76.0	76.0	18.5	106856.0	104490.3	2365.7	2.26
15	75.5	78.5	17.5	103718.1	104490.3	772.2	0.74
Total of volumes V (μm 3 )	1567354.2
Average AVE of volumes V (μm 3 )	104490.3

TABLE 4 — Example 5 Variation of volume V (%)

	Diameter	Diameter	Thickness	Volume V	AVE	AVE − V	(AVE − V)/
Cycle	Dx (μm)	Dy (μm)	Tz (μm)	(μm 3 )	(μm 3 )	(μm 3 )	AVE × 100
1	76.4	78.0	17.9	106667.0	106666.6	0.4	0.00
2	76.0	75.5	17.5	100415.0	106666.6	6251.6	5.86
3	76.5	77.0	17.5	103083.8	106666.6	3582.8	3.36
4	76.0	75.0	18.5	105450.0	106666.6	1216.6	1.14
5	78.5	79.5	17.5	109213.1	106666.6	2546.5	2.39
6	76.5	81.5	17.5	109108.1	106666.6	2441.5	2.29
7	76.0	78.0	18.0	106704.0	106666.6	37.4	0.04
8	76.5	76.5	18.5	108266.6	106666.6	1600.0	1.50
9	73.5	78.5	17.5	100970.6	106666.6	5696.0	5.34
10	77.5	77.0	17.0	101447.5	106666.6	5219.1	4.89
11	76.5	75.5	18.0	103963.5	106666.6	2703.1	2.53
12	73.0	79.0	18.0	103806.0	106666.6	2860.6	2.68
13	77.0	79.0	19.0	115577.0	106666.6	8910.4	8.35
14	77.0	82.0	18.5	116809.0	106666.6	10142.4	9.51
15	79.5	78.0	17.5	108517.5	106666.6	1850.9	1.74
Total of volumes V (μm 3 )	1599998.7
Average AVE of volumes V (μm 3 )	106666.6

TABLE 5 — Variation of volume V (%)

	Diameter	Diameter	Thickness	Volume V	AVE	AVE − V	(AVE − V)/
Cycle	Dx (μm)	Dy (μm)	Tz (μm)	(μm 3 )	(μm 3 )	(μm 3 )	AVE × 100
Comparative Example 1
1	71.0	71.5	13.5	68532.8	83518.6	14985.9	17.94
2	71.5	72.5	15.5	80348.1	83518.6	3170.5	3.80
3	78.0	76.5	13.5	80554.5	83518.6	2964.1	3.55
4	73.0	75.5	15.0	82672.5	83518.6	846.1	1.01
5	72.5	77.0	15.5	86528.8	83518.6	3010.1	3.60
6	72.0	76.0	14.5	79344.0	83518.6	4174.6	5.00
7	73.5	73.5	15.5	83734.9	83518.6	216.3	0.26
8	74.5	74.0	15.5	85451.5	83518.6	1932.9	2.31
9	75.5	74.5	15.0	84371.3	83518.6	852.6	1.02
10	74.0	75.0	15.5	86025.0	83518.6	2506.4	3.00
11	74.0	76.5	15.0	84915.0	83518.6	1396.4	1.67
12	75.0	75.0	15.0	84375.0	83518.6	856.4	1.03
13	76.0	74.5	16.0	90592.0	83518.6	7073.4	8.47
14	73.0	77.0	15.5	87125.5	83518.6	3606.9	4.32
15	74.5	74.0	16.0	88208.0	83518.6	4689.4	5.61
Total of volumes V (μm 3 )	1252778.8
Average AVE of volumes V (μm 3 )	83518.6
Comparative Example 2
1	72.0	72.5	14.0	73080.0	96119.9	23039.9	23.97
2	74.0	76.5	16.5	93406.5	96119.9	2713.4	2.82
3	74.0	76.5	15.0	84915.0	96119.9	11204.9	11.66
4	74.5	76.5	17.0	96887.3	96119.9	767.4	0.80
5	76.5	75.0	18.0	103275.0	96119.9	7155.1	7.44
6	78.0	77.0	17.0	102102.0	96119.9	5982.1	6.22
7	76.5	77.0	17.5	103083.8	96119.9	6963.9	7.24
8	75.0	77.0	17.5	101062.5	96119.9	4942.6	5.14
9	75.5	78.5	15.5	91864.6	96119.9	4255.3	4.43
10	74.0	78.0	17.5	101010.0	96119.9	4890.1	5.09
11	75.5	78.0	17.0	100113.0	96119.9	3993.1	4.15
12	74.5	77.0	17.0	97520.5	96119.9	1400.6	1.46
13	74.0	76.5	17.0	96237.0	96119.9	117.1	0.12
14	75.5	78.5	16.5	97791.4	96119.9	1671.5	1.74
15	75.0	78.0	17.0	99450.0	96119.9	3330.1	3.46
Total of volumes V (μm 3 )	1441798.5
Average AVE of volumes V (μm 3 )	96119.9

TABLE 6 — Variation of volume V (%)

	Diameter	Diameter	Thickness	Volume V	AVE	AVE − V	(AVE − V)/
Cycle	Dx (μm)	Dy (μm)	Tz (μm)	(μm 3 )	(μm 3 )	(μm 3 )	AVE × 100
1	71.0	73.0	13.5	69970.5	95144.8	25174.3	26.46
2	73.5	80.0	15.0	88200.0	95144.8	6944.8	7.30
3	74.5	74.5	17.5	97129.4	95144.8	1984.6	2.09
4	74.0	79.5	17.0	100011.0	95144.8	4866.2	5.11
5	74.0	78.0	15.5	89466.0	95144.8	5678.8	5.97
6	76.0	76.0	17.0	98192.0	95144.8	3047.2	3.20
7	72.0	78.0	17.0	95472.0	95144.8	327.2	0.34
8	78.0	77.0	16.5	99099.0	95144.8	3954.2	4.16
9	74.0	76.5	16.5	93406.5	95144.8	1738.3	1.83
10	76.5	75.0	17.0	97537.5	95144.8	2392.7	2.51
11	75.0	78.5	16.0	94200.0	95144.8	944.8	0.99
12	79.0	76.5	16.5	99717.8	95144.8	4573.0	4.81
13	73.5	79.0	16.0	92904.0	95144.8	2240.8	2.36
14	75.0	78.5	17.5	103031.3	95144.8	7886.5	8.29
15	74.0	79.5	18.5	108835.5	95144.8	13690.7	14.39
Total of volumes V (μm 3 )	1427172.4
Average AVE of volumes V (μm 3 )	95144.8
Comparative Example 4
1	73.5	75.0	14.5	79931.3	102855.0	22923.8	22.29
2	75.0	75.5	17.5	99093.8	102855.0	3761.3	3.66
3	74.5	78.0	17.5	101692.5	102855.0	1162.5	1.13
4	74.0	79.5	17.5	102952.5	102855.0	97.5	0.09
5	75.0	75.0	18.0	101250.0	102855.0	1605.0	1.56
6	77.0	79.0	18.0	109494.0	102855.0	6639.0	6.45
7	76.0	78.0	18.0	106704.0	102855.0	3849.0	3.74
8	78.5	80.0	18.5	116180.0	102855.0	13325.0	12.96
9	75.0	78.5	18.5	108918.8	102855.0	6063.8	5.90
10	72.5	79.0	17.5	100231.3	102855.0	2623.8	2.55
11	75.0	78.0	17.5	102375.0	102855.0	480.0	0.47
12	75.5	77.0	17.0	98829.5	102855.0	4025.5	3.91
13	74.5	78.0	18.0	104598.0	102855.0	1743.0	1.69
14	76.0	76.0	18.5	106856.0	102855.0	4001.0	3.89
15	75.5	78.5	17.5	103718.1	102855.0	863.1	0.84
Total of volumes V (μm 3 )	1542824.6
Average AVE of volumes V (μm 3 )	102855.0

TABLE 7 — Comparative Example 5 Variation of volume V (%)

	Diameter	Diameter	Thickness	Volume V	AVE	AVE − V	(AVE − V)/
Cycle	Dx (μm)	Dy (μm)	Tz (μm)	(μm 3 )	(μm 3 )	(μm 3 )	AVE × 100
1	72.0	74.5	15.5	83142.0	105098.3	21956.3	20.89
2	76.0	75.5	17.5	100415.0	105098.3	4683.3	4.46
3	76.5	77.0	17.5	103083.8	105098.3	2014.6	1.92
4	76.0	75.0	18.5	105450.0	105098.3	351.7	0.33
5	78.5	79.5	17.5	109213.1	105098.3	4114.8	3.92
6	76.5	81.5	17.5	109108.1	105098.3	4009.8	3.82
7	76.0	78.0	18.0	106704.0	105098.3	1605.7	1.53
8	76.5	76.5	18.5	108266.6	105098.3	3168.3	3.01
9	73.5	78.5	17.5	100970.6	105098.3	4127.7	3.93
10	77.5	77.0	17.0	101447.5	105098.3	3650.8	3.47
11	76.5	75.5	18.0	103963.5	105098.3	1134.8	1.08
12	73.0	79.0	18.0	103806.0	105098.3	1292.3	1.23
13	77.0	79.0	19.0	115577.0	105098.3	10478.7	9.97
14	77.0	82.0	18.5	116809.0	105098.3	11710.7	11.14
15	79.5	78.0	17.5	108517.5	105098.3	3419.2	3.25
Total of volumes V (μm 3 )	1576473.8
Average AVE of volumes V (μm 3 )	105098.3

TABLE 8 — pH adjuster *1 In regard to the evaluation, the number of defective items is indicated in the upper box and the defect rate (%) is indicated in the lower box.

	Used/	Added		Evaluation
	Not	amount			100	200	300	500	700	1000
	used	(weight %)	ph		hours	hours	hours	hours	hours	hours
HAST	Example 1	Used	0.25	6.5	*1	0/10	0/10	0/10	0/9	1/9	1/8
130° C.						0	0	0	0	11	22
85%	Example 2	Used	0.15	6.1		0/10	0/10	0/10	2/9	2/7	4/5
5 V						0	0	0	22	44	89
Bias	Example 3	Used	0.05	5.9		0/10	0/10	0/10	2/9	2/7	3/5
	Comparative	Not	0	4.4		0	0	0	22	44	78
	Example 1	used				5/10	3/5	0/2	1/1	—	—
						56	89	89	100	100	100

TABLE 9 — pH adjuster *2 In regard to the evaluation, the number of defective items is indicated in the upper box and the defect rate (%) is indicated in the lower box.

	Used/	Added		Evaluation
	Not	amount			100	200	300	500	700
	used	(weight %)	ph		hours	hours	hours	hours	hours
PCT	Example 1	Used	0.25	6.5	*2	0/30	0/30	0/30	0/30	0/30
121° C.						0	0	0	0	0
100%	Example 2	Used	0.15	6.1		0/30	0/30	0/30	0/30	0/30
						0	0	0	0	0
	Example 3	Used	0.05	5.9		0/30	0/30	0/30	0/30	0/30
						0	0	0	0	0
	Comparative	Not	0	4.4		0/30	0/30	6/30	12/24	11/12
	Example 1	used				0	0	20	60	97

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IPC · International Patent Classification

Section B — Performing operations; transporting

B23K20/10
B23K20/24
B23K20/00

Section H — Electricity

H01L21/56
H10W70/40

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