Method for forming traces of a printed circuit board

In a typical printed circuit board (PCB) fabrication process, copper clad laminate with copper on both sides of the PCB can be used. A photoimagable resist is applied on both sides of the PCB and exposed and developed to create the circuitry. The unwanted copper between the circuitry is then removed using copper chemical etching solutions. The resist is then chemically removed. For multilayer constructions, glass reinforced not fully cured resin prepregs can be placed on both sides of a finished core and laminated under heat, vacuum and pressure using copper foil on both sides of the PCB. Hole formation can be performed using mechanical means such as drilling or lasers to create blind vias to interconnect the outer layers to the inner ones. Prepregs, if not already impregnated with a synthetic resin, can be reinforced with a synthetic resin.

FIG. 1 shows a simplified diagram illustrated a printed circuit board structure with embedded traces in accordance with an implementation.

FIG. 2 sets out a simplified flowchart that summarizes a process for fabricating a printed circuit board with embedded traces in accordance with an implementation.

FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 and FIG. 10 illustrate steps in a process for fabricating a printed circuit board with embedded traces in accordance with an implementation.

In printed circuit board (PCB) fabrication where traces are formed above a laminate surface by 0.5-2.5 mils, there is a potential that voids can be entrapped between the traces during a prepreg lamination or during a solder mask application if the PCB is a two-layer board. In addition, signal integrity and conductor impedance are functions of the dielectric spacing between traces. When PCB traces are formed above a laminate surface, dielectric space above the PCB traces will vary across the length and width of the board. This makes it difficult to accurately control impedance of the PCB traces. Also, when PCB traces are formed above a laminate surface and trace widths and spaces are less than one mil, failures of fine trace lines to properly adhere to the laminate surface can cause both poor yields in fabrication and reliability issues. For example, when forming traces on the substrate surface, the geometry of the traces can vary across the length of the traces due to inaccuracies introduced by the limitations of photolithography and chemical copper etching. Varying geometries of traces can create poor signal propagation and trace impedance.

In order to solve the above issues that arise when PCB traces are formed above a laminate surface, PCB traces are embedded in a laminate substrate so that the PCB traces do not extend above the laminate surface. This is illustrated in FIG. 2 where PCB traces 12 are embedded within a laminate substrate 10 . A next layer 13 can be, for example, a solder mask for a two-layer PCB board, or a prepreg lamination layer for a PCB board that includes more than two-layers or a non-glass reinforced catalytic adhesive.

PCB traces 12 are formed in channels with a depth, for example, between 0.25 and 2.5 mils. The channels are ablated in the surface of laminate substrate 10 . Embedding PCB traces 12 provides for better electrical performance since the geometry of the PCB traces is very well controlled by the channel formation process. Also, embedding PCB traces 12 in laminate substrate 10 solves the adhesion problem that arises when traces are very fine, for example, when trace thickness and space between traces is less than one mil. When PCB traces are embedded they are constrained on three sides by laminate surfaces.

FIG. 2 sets out a simplified flowchart that summarizes a process for fabricating a printed circuit board with embedded traces. In a block 31 , the process starts with a laminate substrate. For example, a catalytic base laminate is used without any copper. For example, the catalytic base laminate uses palladium powder that includes palladium catalytic particles made out of inorganic fillers primarily Kaolin. For example, the inorganic fillers are produced by contacting a salt palladium, at the surface of a filler such as aluminum silicate, and clays such as Kaolin with a reducing agent. Alternatively, instead of salt of palladium, salt of another metal such as silver can be used.

Hydrazine hydrate can be used as a reducing agent to reduce the palladium salt to palladium metal. The filler can be added into a mixing tank with water in a form of slurry and then a palladium chlorine (PdCl) and hydrochloric acid (HCl) solution added into the mixture followed by the hydrazine hydrate. For more information on making such a catalytic power, see U.S. Pat. No. 4,287,253.

The catalytic powder can be dispersed in an epoxy resin well. The epoxy resin with the catalytic filler in it can be used to impregnate a glass cloth with resin and catalyst using conventional glass cloth coating and drying equipment. The coated semi-cured resin/glass cloths can be used to make laminates for printed circuit boards by pressing the coated semi-cured resin/glass cloths together under standard vacuum laminating equipment. The resulting layered laminate material can be used as a catalytic laminate substrate for a printed circuit board.

For example, laminate substrate 10 is a catalytic laminate substrate of any thickness between, for example, two and sixty mils. For example, laminate substrate 10 is composed of a non-clad catalytic base laminate with outside prepregs that are resin rich so that after vacuum lamination the resulting finished laminate has a resin rich surface. For example, resin rich prepregs can have (but are not limited to) a glass style 106 with 71% resin content or a glass style 1035 with 65% resin content. Using a resin rich laminate surface assures that when channels are made, primarily resin is removed and not glass. This can speed up the channel formation process and improve the quality of the channel. For example, the surface of the resin rich catalytic laminate is initially protected with a release film so that the surface is protected from scratches as scratches will plate up copper and create defects. When ready for channel formation, the release film is removed from both sides of laminate substrate 10 .

In a block 32 , laser ablation is used to break the surface of laminate substrate 10 and form channels 11 , as shown in FIG. 4 . The laser ablation can be accomplished, for example, with an ultraviolet (UV) excimer laser, with a Yttrium aluminum garnet (YAG) laser, with a UV YAG laser or with some other type of laser, or alternatively, a non-laser ablation process. Excimer laser ablation creates good depth control and channel resolution.

As an alternative to using laser ablation to form channels, resist can be applied on both sides of laminate substrate 10 . The resist is exposed and developed to delineate locations of the channels. For example, resist thickness is thicker than the depth of the channels. For example, for a channel depth of 0.5 mils, resist thickness can be 1.0 to 1.5 mils. The formation of the channels can then be performed using plasma etching with a combination of gasses (e.g., O2, CF4, Ar, etc.) along with the proper power and duration. It is expected the channel will be etched at a different rate than the resist. For example, the resist thickness should be sufficiently thicker that the channel depth so that when the channel depth is reached there is some resist left protecting unexposed regions of the surfaces of laminate substrate 10 . After plasma etching, the remaining resist can be removed by a resist stripper.

Alternatively, instead of protecting the surface of laminate substrate with resist when performing plasma etch, other protective material can be used. For example, the protection can be accomplished using a foil, such as a copper foil or aluminum foil, that gets applied to laminate substrate 10 . The shiny side of the foil can be placed facing laminate substrate 10 so the foil can be peeled off after channel formation. For example, after applying the foil to laminate substrate 10 , resist will be applied over the foil. The resist is exposed/develop to expose the foil over the channel regions. The foil is etched to expose the channel regions in laminate substrate 10 . The remaining resist is then stripped and the channels are plasma etched. The remaining foil is peeled off and processing continues.

Alternatively, channels can be formed using high pressure water cutting. The high pressure water cutting can be performed using programmable high pressure water cutting machines such as those used for cutting hard materials such as steel and stainless steel. Another mechanical processes such as drilling and routing can be used for making the channels.

In a block 33 , the laminate substrate is cleaned to remove debris from channels 11 . For example, the cleaning can be accomplished by an ultrasonic rinse using acoustic wave with a frequency within the range of 40 to 160 megahertz (MHz). A more aggressive chemical cleaning is typically not used as an aggressive chemical cleaning may result in the surface of laminate substrate 10 being roughened or etched. If the surface of laminate substrate 10 is etched this can result in metal plating at locations not within formed channels.

In a block 34 , traces 12 are formed in channels 11 , as illustrated by FIG. 5 . For example, traces 12 are a metal such as copper. For example, to form copper traces, laminate substrate 10 is immersed into a fast electroless copper bath. Channels 11 are plated all the way up and slightly above the surface of laminate substrate 10 . The electroless copper bath plates only on the exposed catalytic areas that were exposed by the ablation process. No copper plates outside channels 11 since during the lamination process of making laminate substrate 10 the copper catalyzes only at locations where the surface of the laminate substrate 10 where the surface is ablated, scratched or roughened. As a result copper traces form where ablation has penetrated the surface of laminate substrate 10 . A simplified top view of traces within laminate substrate 10 is shown in FIG. 6 .

In a block 35 , the surfaces of laminate substrate 10 are planarized, for example, using fine grid sandpaper (e.g., 420 grit to 1200 grit). The planarization removes any excess copper that extends above the channels. For example, a planarization machine such as those produced by MASS, Inc., can be used. The resulting planarization is illustrated in FIG. 7 . For a two-layer PCB board, a solder mask is applied. For example, the PCB may be finished by performing selective gold plating followed by singulation and inspection.

When the PCB board will have more than two layers, in a block 36 , a resin rich catalytic prepreg material 13 is laminated on both sides of laminate substrate. For example, a release film such as tedlar or Teflon is used. The result is shown in FIG. 8 . Alternative to using resin rich catalytic prepreg material 13 , a not catalytic material can be used such as a catalytic adhesive material implemented, for example, as a layer of non-glass reinforced catalytic adhesive.

In a block 37 , blind and through vias are formed, for example by use of laser or mechanical means such as a drill. The result is illustrated by FIG. 9 where a blind via 14 , a blind via 15 and a through via 16 are shown.

After an ultrasonic cleaning in water, in a block 38 , traces 17 are formed. For example traces 17 are a metal, such as copper. For example, traces 17 are formed by electroless copper plating. The electroless copper plating will result in traces being formed within vias 14 , 15 and 16 , as illustrated by trace regions 18 , 19 and 20 , respectively. This results in the four layer board structure shown in FIG. 10 . For example, the PCB may be finished by performing processing steps such as applying a solder mask, selective gold plating, singulation (i.e., depaneling from an array) and inspection.

Alternatively, in a block 39 , additional layers may be added by repeating blocks 36 , 37 and 38 as often as necessary to reach the desired numbers of layers. When the desired numbers of layers are reached, in a block 40 , the PCB may be finished by performing such processing steps such as applying a solder mask, selective gold plating, singulation (i.e., depaneling PCBs from an array) and inspection.

The foregoing discussion discloses and describes merely exemplary methods and embodiments. As will be understood by those familiar with the art, the disclosed subject matter may be embodied in other specific forms without departing from the spirit or characteristics thereof. Accordingly, the present disclosure is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.