Inventor

Konstantine Karavakis

Inventor

Pleasanton, CA, US

Overview

1997–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 70 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%

H05KPrinted circuits26%

Y10TTechnical subjects covered by former us classification20%

G01RMeasuring electric variables6%

H01RElectrically-conductive connections4%

C23CCoating metallic material4%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%

H01LSemiconductor devices2%

B29BPreparation or pretreatment of the material to be shaped1%

B29CShaping or joining of plastics1%

PatentTitleYear

10,959,329Circuit board using non-catalytic laminate with catalytic adhesive overlay2021 10,849,233Process for forming traces on a catalytic laminate2020 10,827,624Catalytic laminate with conductive traces formed during lamination2020 10,806,029Catalytic circuit board with traces and vias2020 10,765,003Method for making a multi-layer circuit board using conductive paste with interposer layer2020 10,765,012Process for printed circuit boards using backing foil2020 10,685,931Method and apparatus for forming contacts on an integrated circuit die using a catalytic adhesive2020 10,573,610Method for wafer level packaging2020 10,349,520Multi-layer circuit board using interposer layer and conductive paste2019 10,306,756Circuit board with catalytic adhesive2019 9,942,981Circuit board apparatus and method2018 9,922,951'Integrated circuit wafer integration with catalytic laminate or adhesive'2018 9,706,650'Catalytic laminate apparatus and method'2017 9,706,667'Via in a printed circuit board'2017 9,674,967'Via in a printed circuit board'2017 9,631,279'Methods for forming embedded traces'2017 9,398,703'Via in a printed circuit board'2016 9,380,700'Method for forming traces of a printed circuit board'2016 8,558,386'Methods of making compliant semiconductor chip packages'2013 8,338,925'Microelectronic assemblies having compliant layers'2012 8,004,296'Probe head apparatus for testing semiconductors'2011 7,872,344'Microelectronic assemblies having compliant layers'2011 7,834,447'Compliant thermal contactor'2010 7,719,816'Compliant thermal contactor'2010 7,491,069'Self-cleaning socket for microelectronic devices'2009 7,408,260'Microelectronic assemblies having compliant layers'2008 7,170,306'Connecting a probe card and an interposer using a compliant connector'2007 7,114,250'Method of making components with releasable leads'2006 7,112,879'Microelectronic assemblies having compliant layers'2006 7,067,742'Connection component with peelable leads'2006 6,998,864'Structures for testing circuits and methods for fabricating the structures'2006 6,946,859'Probe structures using clamped substrates with compliant interconnectors'2005 6,924,654'Structures for testing circuits and methods for fabricating the structures'2005 6,897,090'Method of making a compliant integrated circuit package'2005 6,847,101'Microelectronic package having a compliant layer with bumped protrusions'2005 6,847,107'Image forming apparatus with improved transfer efficiency'2005 6,763,579'Method of making components with releasable leads'2004 6,664,484'Components with releasable leads'2003 6,602,431'Enhancements in sheet processing and lead formation'2003 6,603,209'Compliant integrated circuit package'2003 6,557,253'Method of making components with releasable leads'2003 6,500,528'Enhancements in sheet processing and lead formation'2002 6,495,462'Components with releasable leads'2002 6,465,878'Compliant microelectronic assemblies'2002 6,423,907'Components with releasable leads'2002 6,373,128'Semiconductor assemblies with reinforced peripheral regions'2002 6,370,032'Compliant microelectronic mounting device'2002 6,357,112'Method of making connection component'2002 6,274,822'Manufacture of semiconductor connection components with frangible lead sections'2001 6,274,820'Electrical connections with deformable contacts'2001 6,266,874'Methods of making microelectronic components having electrophoretically deposited layers'2001 6,239,386'Electrical connections with deformable contacts'2001 6,215,191'Compliant lead structures for microelectronic devices'2001 6,211,572'Semiconductor chip package with fan-in leads'2001 6,204,455'Microelectronic component mounting with deformable shell terminals'2001 6,157,075'Semiconductor assemblies with reinforced peripheral regions'2000 6,086,386'Flexible connectors for microelectronic elements'2000 6,012,224'Method of forming compliant microelectronic mounting device'2000 5,971,253'Microelectronic component mounting with deformable shell terminals'1999 5,966,587'Methods of making semiconductor assemblies with reinforced peripheral regions'1999 5,966,592'Structure and method for making a compliant lead for a microelectronic device'1999 5,929,517'Compliant integrated circuit package and method of fabricating the same'1999 5,821,609'Semiconductor connection component with frangible lead sections'1998 5,776,796'Method of encapsulating a semiconductor package'1998 5,777,379'Semiconductor assemblies with reinforced peripheral regions'1998 5,706,174'Compliant microelectrionic mounting device'1998 5,663,106'Method of encapsulating die and chip carrier'1997 5,629,239'Manufacture of semiconductor connection components with frangible lead sections'1997 5,597,470'Method for making a flexible lead for a microelectronic device'1997 5,590,460'Method of making multilayer circuit'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2013Patents assigned to TESSERA INC (44)· patent assignee history

1997–2003Based in Cupertino, CA, US· patent location history

1997Based in Coram, NY, US· patent location history

1999–2021Based in Pleasanton, CA, US· patent location history

2003–2005Based in Pleasant Hill, CA, US· patent location history

2005–2007Patents assigned to CELERITY RES INC (4)· patent assignee history

2012–2017Patents assigned to KARAVAKIS KONSTANTINE (5)· patent assignee history

2016–2020Patents assigned to SIERRA CIRCUITS INC (13)· patent assignee history

2019–2021Patents assigned to CATLAM LLC (9)· patent assignee history

2020Based in Livermore, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TESSERA INC	44	1997–2013
SIERRA CIRCUITS INC	13	2016–2020
CATLAM LLC	9	2019–2021
KARAVAKIS KONSTANTINEself	5	2012–2017
CELERITY RES INC	4	2005–2007

Locations

Location	Patents	Span
Pleasanton, California, US	48	1999–2021
Cupertino, California, US	17	1997–2003
Pleasant Hill, California, US	3	2003–2005
Livermore, California, US	1	2020
Coram, New York, US	1	1997