Inventor
Kenneth S. Bahl
Inventor
Saratoga, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H05Kprimary
H05KPrinted circuits45%
C23CCoating metallic material15%
Y10TTechnical subjects covered by former us classification13%
H01LSemiconductor devices8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
B29BPreparation or pretreatment of the material to be shaped3%
B29CShaping or joining of plastics3%
C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients3%
C25DProcesses for the electrolytic or electrophoretic production of coatings3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
PatentTitleYear
11,039,540Multi-layer circuit board with traces thicker than a circuit board layer202110,959,329Circuit board using non-catalytic laminate with catalytic adhesive overlay202110,849,233Process for forming traces on a catalytic laminate202010,827,624Catalytic laminate with conductive traces formed during lamination202010,806,029Catalytic circuit board with traces and vias202010,765,012Process for printed circuit boards using backing foil202010,765,003Method for making a multi-layer circuit board using conductive paste with interposer layer202010,685,931Method and apparatus for forming contacts on an integrated circuit die using a catalytic adhesive202010,573,610Method for wafer level packaging202010,349,520Multi-layer circuit board using interposer layer and conductive paste201910,306,756Circuit board with catalytic adhesive20199,942,981Circuit board apparatus and method20189,922,951'Integrated circuit wafer integration with catalytic laminate or adhesive'20189,706,667'Via in a printed circuit board'20179,706,650'Catalytic laminate apparatus and method'20179,674,967'Via in a printed circuit board'20179,631,279'Methods for forming embedded traces'20179,398,703'Via in a printed circuit board'20169,380,700'Method for forming traces of a printed circuit board'2016Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2016–2020Patents assigned to SIERRA CIRCUITS INC (13)· patent assignee history
2016–2017Patents assigned to BAHL KENNETH S (3)· patent assignee history
2016–2017Patents assigned to KARAVAKIS KONSTANTINE (3)· patent assignee history
2016–2017Patents assigned to CARNEY STEVE (2)· patent assignee history
2016–2021Based in Saratoga, CA, US· patent location history
2019–2021Patents assigned to CATLAM LLC (10)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SIERRA CIRCUITS INC | 13 | 2016–2020 |
| CATLAM LLC | 10 | 2019–2021 |
| BAHL KENNETH Sself | 3 | 2016–2017 |
| KARAVAKIS KONSTANTINE | 3 | 2016–2017 |
| CARNEY STEVE | 2 | 2016–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga, California, US | 19 | 2016–2021 |