Method and apparatus for selecting voltage and frequency levels for use in at-speed testing

The present invention relates generally to design automation, and relates more particularly to the at-speed structural test (ASST) of integrated circuit (IC) chips.

When IC chips come off the manufacturing line, the chips are tested “at-speed” to ensure that they perform correctly (and to filter out chips that do not perform correctly). In particular, the chips are tested at a specified voltage level (V test ). In addition, the chips must meet a specified frequency level (F test ) to be qualified as “good” chips.

The determination of V test and F test directly impacts the yield (i.e., the percentage of the chips that are shipped to customers) and the shipped product quality loss (i.e., the percentage of the chips that are shipped to customers that are “bad” chips). More stringent test conditions will improve shipped product quality loss but worsen yield. More relaxed test conditions will improve yield but worsen shipped product quality loss.

Conventionally, V test and F test are determined in a heuristic manner based on empirical hardware characterization. This approach is performed manually using engineering judgment. Thus, inherently, this approach has no mathematical formulation or statistical basis and requires significant human effort. The resulting test conditions are typically highly sensitive to variations in sample chips.

In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

FIG. 1 is a flow diagram illustrating one embodiment of a method for selecting voltage and frequency levels for use in at-speed testing of a set of integrated circuit chips, according to the present invention;

FIG. 2 is a graph illustrating voltage versus highest working frequency for a set of four sample chips; and

FIG. 3 is a high-level block diagram of test condition selection method that is implemented using a general purpose computing device.

In one embodiment, the present invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing of IC chips. Embodiments of the invention provide an automated technique for determining the optimal voltage and frequency levels for testing a set of IC chips. The voltage and frequency levels are then applied by a tester (i.e., a system or device that electronically tests the IC chips under a set of test parameters in order to determine whether their operational characteristics match simulation models or other documentation for the IC chips). The present invention achieves better and more robust testing of IC chips, as well as higher productivity, than is possible with conventional heuristic practices.

FIG. 1 is a flow diagram illustrating one embodiment of a method 100 for selecting voltage and frequency levels for use in at-speed testing of a set of IC chips, according to the present invention. The method 100 may be implemented, for example, at a processor that is coupled to a tester for testing the set of IC chips. Alternatively, the method 100 may be implemented at the tester.

The method 100 is initialized at step 102 and proceeds to step 104 , where the method 100 obtains a set of k sample chips from the set of N IC chips (where k≦N). The k sample chips can be selected randomly or selected over a set of parametric indicators (for example, over a range of performance-sensitive ring oscillator (PSRO) frequencies over the set of N IC chips).

In step 106 , the method 100 shmoos (i.e., plots the response varying over a range of conditions and inputs) the set of sample chips. In one embodiment, shmooing involves, for each of the k sample chips, applying a set of voltages over some range of voltages. At each applied voltage, the frequency of the sample chip is varied until the sample chip fails. Thus, the highest working frequency (i.e., the highest operating frequency at which the sample chip does not fail) is obtained for each sample chip under different voltage levels.

FIG. 2 , for example, is a graph illustrating voltage versus the highest working frequency, with the domain frequency (i.e., the frequency used by customers in normal operation) illustrated as a horizontal line for a set of four sample chips (designated as SAMPLE CHIP 1 , SAMPLE CHIP 2 , SAMPLE CHIP 3 , and SAMPLE CHIP 4 ). The PSRO frequency for each sample chip is indicated in parentheses; as illustrated, the sample chips cover a range of PSRO frequencies from 151 nanoseconds to 219 nanoseconds. Each point on the graph designates, for a given sample chip, the highest working frequency at a corresponding voltage.

Referring back to FIG. 1 , in step 108 , the method 100 runs a regression on the highest working frequencies obtained in step 106 . The result of the regression is a mathematical model that captures the relation between the working frequencies, the characteristics of the set of sample chips, and the different voltage levels.

In step 110 , the method 100 uses the regression data to solve a statistical optimization problem. The solution to the optimization problem comprises the optimal testing conditions for the frequency and the voltage (i.e., F test and V test ). In particular, the optimization problem attempts to achieve a target scrap rate, T scrap (i.e., a percentage of the set of N IC chips that is scrapped during ASST) based on the mathematical model obtained in step 108 . The scrap rate is typically used by test engineers as an indicator to judge the testing quality. When the scrap rate is too high, too many chips are discarded, and yield suffers. When the scrap rate is too low, too many chips are shipped to customers, and shipped product quality loss may be at risk of being high. In one embodiment, T scrap is in the range of 0.5 to 2.5 percent.

In one embodiment, the optimization problem seeks to select values for F test and V test that minimize the deviation from the target scrap rate. Thus, in one embodiment, the optimization problem is formulated as follows:

min F test , V test ⁢  P ⁡ ( F ⁡ ( PSRO , V test ) ≤ F test ) - T scrap 

such that:

V min ≦V test ≦V max

F min ≦F test ≦F max

F (PSRO k ,V ), kε[ 1 ,N]ε[V min ,V max ]  (EQN. 1)

where PSRO is the PSRO frequency for all chips in the set of N IC chips, F(PSRO, V) is the modeled highest working frequency for all chips with different PSRO frequencies at any voltage level V, F(PSRO k , V) are the shmooed highest working frequencies for the set of k sample chips (e.g., in the case of FIG. 2 , the k=4 slanted curves), P(F(PSRO,V test )≦F test ) is the probability that the frequency for all chips in the set of N IC chips as a function of PSRO frequency and test voltage V test is less than or equal to the test frequency F test , V min and V max are the minimum and maximum allowable voltage levels, respectively, and F min and F max are the minimum and maximum achievable frequencies in the tester, respectively.

The modeled F(PSRO, V) in the statistical optimization problem defined in EQN. 1 comprises a known (analytical) part and an unknown part. The known part has a given functional form, while the unknown part is modeled as one or more random variables. In one embodiment, the unknown part of the optimization problem is modeled as a random variable that represents variation. For example, F(PSRO, V) may be modeled as follows:

F (PSRO, V )= G (PSRO, V )+Δ R   (EQN. 2)

where R is the random variable.

The known part of F(PSRO, V) can be any user-selected functional form based on engineering knowledge about the process. For example, the known part of the optimization problem can be modeled as:

G (PSRO, V )=α 0 +(α 1 ·PSRO)+(α 2 ·V )  (EQN. 3)

where the frequency F is a linear function of the voltage V and the PSRO frequency.

The regression performed in step 108 provides the known part of F(PSRO, V), based on the shmoo data. The remaining error or uncertainty is assigned to the unknown random variable.

In one embodiment, the PSRO frequency can be modeled as a distribution. In another embodiment, the random variation ΔR can be adjusted to make the model more comfortably capture model uncertainty. This adjustment can be based on the sample chip data and/or on expert or domain knowledge.

For example, referring back to EQN. 1 by assuming Gaussian random distributions for both PSRO and ΔR, EQN. 1 could be alternatively formulated as:

More specifically, solving EQN. 1 based on a linear regression model, one can obtain:

For the same target scrap rate, one can have multiple choices of V test and F test within a valid region. These choices fall within a straight line bounded by [V min , V max ] and [F min , F max ]. In one embodiment, F min is chosen as F domain . Thus, F test can be solved as:

The method 100 outputs the optimal testing conditions F test and V test in step 112 . In one embodiment, the optimal testing conditions are output directly to the tester (e.g., by programming the tester), which applies the optimal testing conditions to testing of the set of IC chips. The method 100 then terminates in step 114 .

The method 100 therefore provides a framework to systematically examine different effects on chosen testing conditions. Application of the method 100 produces high-quality testing results that are robust to sample variations. Moreover, the automated flow of the present invention enhanced the productivity of the testing.

In one embodiment, a more general formulation of EQN. 8 can be used to extend the present invention to IC chips having multiple clock domains. When there are multiple clock domains, each clock domain would have its own model:

∀ iε[ 1 ,m]:F i (PSRO, V )=α i,0 +(α i,1 ·PSRO)+(α i,2 ·V )+Δ R i   (EQN. 9)

The final scrap rate should be a joint scrap rate for all clock domains, i.e.:

P ( F 1 (PSRO, V 1,test )≦ F 1,test , or . . . , or F m (PSRO, V m,test )≦ F m,test )  (EQN. 10)

The optimization problem can thus be similarly formulated as:

min F i , test , V i , test ⁢  P ( F 1 ⁡ ( PSRO , V 1 , test ) ≤ F 1 , test , or ⁢ ⁢ … ⁢ , or ⁢ ⁢ F m ⁡ ( PSRO , V m , test ) ≤ F m , test ) - T scrap  .

such that

∀ iε[ 1 ,m]

V min ≦V i,test ≦V max

F i,min ≦F i,test ≦F max   (EQN. 11)

EQN. 11 can be solved numerically, such that the optimal solution is not unique and may not necessarily form a hyper plane. Alternatively, EQN. 11 can be solved iteratively. In the latter case, the test conditions for each clock domain are independently found to target an adjusted scrap rate that is lower than the target scrap rate. The same procedures described above with respect to FIG. 1 are followed for each clock domain. The joint scrap rate is then computed to determine what joint scrap rate can be finally achieved (e.g., using EQN. 10). If the joint scrap rate is higher than the target scrap rate, the adjusted scrap rate is reduced; if the joint scrap rate is lower than the target scrap rate, the adjusted scrap rate is increased.

The present invention therefore makes use of all shmoo data generated from a set of sample chips. The end result is thus less sensitive to one particular sample chip. In addition, by statistically targeting the “desired” scrap rate directly, the chances of over-scrapping or under-scrapping can be minimized.

FIG. 3 is a high-level block diagram of test condition selection method that is implemented using a general purpose computing device 300 . In one embodiment, a general purpose computing device 300 comprises a processor 302 , a memory 304 , a test condition selection module 305 and various input/output (I/O) devices 306 such as a display, a keyboard, a mouse, a stylus, a wireless network access card, and the like. In one embodiment, at least one I/O device is a storage device (e.g., a disk drive, an optical disk drive, a floppy disk drive, a path selection tool, and/or a test pattern generation tool). It should be understood that the test condition selection module 305 can be implemented as a physical device or subsystem that is coupled to a processor through a communication channel.

Alternatively, the test condition selection module 305 can be represented by one or more software applications (or even a combination of software and hardware, e.g., using Application Specific Integrated Circuits (ASIC)), where the software is loaded from a storage medium (e.g., I/O devices 306 ) and operated by the processor 302 in the memory 304 of the general purpose computing device 300 . Thus, in one embodiment, the test condition selection module 305 for selecting a voltage and frequency levels for use in at-speed structural testing of an IC chip, as described herein with reference to the preceding Figures, can be stored on a non-transitory computer readable storage medium (e.g., RAM, magnetic or optical drive or diskette, and the like).

It should be noted that although not explicitly specified, one or more steps of the methods described herein may include a storing, displaying and/or outputting step as required for a particular application. In other words, any data, records, fields, and/or intermediate results discussed in the methods can be stored, displayed, and/or outputted to another device as required for a particular application. Furthermore, steps or blocks in the accompanying Figures that recite a determining operation or involve a decision, do not necessarily require that both branches of the determining operation be practiced. In other words, one of the branches of the determining operation can be deemed as an optional step.

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. Various embodiments presented herein, or portions thereof, may be combined to create further embodiments. Furthermore, terms such as top, side, bottom, front, back, and the like are relative or positional terms and are used with respect to the exemplary embodiments illustrated in the figures, and as such these terms may be interchangeable.