LexDanaLexDanabeta
Inventor

Chandramouli Visweswariah

Inventor
Croton-on-Hudson, NY, US

Overview

101→
Patents
1999–2021
Patent span
Physics
Primary field (CPC G)

Patents· 101 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing86%
G01RMeasuring electric variables9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
Y02PClimate change mitigation technologies in the production or processing of goods2%
G16ZInformation and communication technology [ict] specially adapted for specific application fields, not otherwise provided for1%
PatentTitleYear
10,970,448Partial parameters and projection thereof included within statistical timing analysis202110,891,409Anomaly localization in a pipeline202110,606,970Selection of corners and/or margins using statistical static timing analysis of an integrated circuit202010,489,540Integrating manufacturing feedback into integrated circuit structure design201910,394,982Partial parameters and projection thereof included within statistical timing analysis201910,289,776Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit201910,169,527Accurate statistical timing for boundary gates of hierarchical timing models201910,055,532Collapsing terms in statistical static timing analysis201810,031,985Sensitivity calculation filtering for statistical static timing analysis of an integrated circuit201810,013,516Selection of corners and/or margins using statistical static timing analysis of an integrated circuit20189,940,431Accurate statistical timing for boundary gates of hierarchical timing models20189,864,824'System and method for efficient statistical timing analysis of cycle time independent tests'20189,858,368'Integrating manufacturing feedback into integrated circuit structure design'20189,852,246System and method for efficient statistical timing analysis of cycle time independent tests20179,767,239'Timing optimization driven by statistical sensitivites'20179,690,899'Prioritized path tracing in statistical timing analysis of integrated circuits'20179,646,122'Variable accuracy parameter modeling in statistical timing'20179,607,124'Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints'20179,600,617'Automated timing analysis'20179,519,747'Dynamic and adaptive timing sensitivity during static timing analysis using look-up table'20169,501,609'Selection of corners and/or margins using statistical static timing analysis of an integrated circuit'20169,495,497'Dynamic voltage frequency scaling'20169,483,604'Variable accuracy parameter modeling in statistical timing'20169,378,328'Modeling multi-patterning variability with statistical timing'20169,348,962'Hierarchical design of integrated circuits with multi-patterning requirements'20169,280,624'System and method for efficient statistical timing analysis of cycle time independent tests'20169,171,124'Parasitic extraction in an integrated circuit with multi-patterning requirements'20158,949,765'Modeling multi-patterning variability with statistical timing'20158,930,864'Method of sharing and re-using timing models in a chip across multiple voltage domains'20158,856,709'Systems and methods for correlated parameters in statistical static timing analysis'20148,850,378'Hierarchical design of integrated circuits with multi-patterning requirements'20148,839,167'Reducing runtime and memory requirements of static timing analysis'20148,832,625'Systems and methods for correlated parameters in statistical static timing analysis'20148,806,402'Modeling multi-patterning variability with statistical timing'20148,781,792'Yield computation and optimization for selective voltage binning'20148,775,988'Decentralized dynamically scheduled parallel static timing analysis'20148,769,452'Parasitic extraction in an integrated circuit with multi-patterning requirements'20148,768,679'System and method for efficient modeling of NPskew effects on static timing tests'20148,732,642'Method for achieving an efficient statistical optimization of integrated circuits'20148,707,233'Systems and methods for correlated parameters in statistical static timing analysis'20148,689,158'System and method for performing static timing analysis in the presence of correlations between asserted arrival times'20148,683,409'Performing statistical timing analysis with non-separable statistical and deterministic variations'20148,676,536'Method and apparatus for selecting voltage and frequency levels for use in at-speed testing'20148,589,842'Device-based random variability modeling in timing analysis'20138,578,310'Method of measuring the impact of clock skew on slack during a statistical static timing analysis'20138,560,989'Statistical clock cycle computation'20138,510,696'Ordering of statistical correlated quantities'20138,468,483'Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence'20138,458,632'Efficient slack projection for truncated distributions'20138,418,107'Performing statistical timing analysis with non-separable statistical and deterministic variations'20138,359,565'Method and apparatus for generating test patterns for use in at-speed testing'20138,359,563'Moment-based characterization waveform for static timing analysis'20138,340,939'Method and apparatus for selecting paths for use in at-speed testing'20128,266,565'Ordering of statistical correlated quantities'20128,176,462'Method and apparatus for generating test patterns for use in at-speed testing'20128,141,025'Method of performing timing analysis on integrated circuit chips with consideration of process variations'20128,141,012'Timing closure on multiple selective corners in a single statistical timing run'20128,122,409'Method and device for selectively adding timing margin in an integrated circuit'20128,122,404'Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits'20128,112,735'Affinity-based clustering of vectors for partitioning the columns of a matrix'20128,104,005'Method and apparatus for efficient incremental statistical timing analysis and optimization'20128,086,976'Methods for statistical slew propagation during block-based statistical static timing analysis'20118,086,988'Chip design and fabrication method optimized for profit'20118,056,035'Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing'20118,015,525'System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis'20118,010,921'System and method for statistical timing analysis of digital circuits'20117,971,120'Method and apparatus for covering a multilayer process space during at-speed testing'20117,958,484'Affinity-based clustering of vectors for partitioning the columns of a matrix'20117,886,247'Method and apparatus for statistical path selection for at-speed testing'20117,886,246'Methods for identifying failing timing requirements in a digital design'20117,873,925'Method and apparatus for computing test margins for at-speed testing'20117,861,199'Method and apparatus for incrementally computing criticality and yield gradient'20107,856,607'System and method for generating at-speed structural tests to improve process and environmental parameter space coverage'20107,849,429'Methods for conserving memory in statistical static timing analysis'20107,844,932'Method to identify timing violations outside of manufacturing specification limits'20107,814,448'Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits'20107,797,657'Parameter ordering for multi-corner static timing analysis'20107,743,355'Method of achieving timing closure in digital integrated circuits by optimizing individual macros'20107,739,640'Method and apparatus for static timing analysis in the presence of a coupling event and process variation'20107,698,674'System and method for efficient analysis of point-to-point delay constraints in static timing'20107,681,157'Variable threshold system and method for multi-corner static timing analysis'20107,620,921'IC chip at-functional-speed testing with process coverage evaluation'20097,555,740'Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis'20097,512,919'System and method for incremental statistical timing analysis of digital circuits'20097,480,880'Method, system, and program product for computing a yield gradient from statistical timing'20097,428,716'System and method for statistical timing analysis of digital circuits'20087,353,359'Affinity-based clustering of vectors for partitioning the columns of a matrix'20087,293,248'System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis'20077,212,946'Method, system, and program product for accommodating spatially-correlated variation in a process parameter'20077,117,455'System and method for derivative-free optimization of electrical circuits'20067,117,466'System and method for correlated process pessimism removal for static timing analysis'20067,111,260'System and method for incremental statistical timing analysis of digital circuits'20067,093,208'Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices'20067,086,023'System and method for probabilistic criticality prediction of digital circuits'20067,010,763'Method of optimizing and analyzing selected portions of a digital integrated circuit'20067,003,747'Method of achieving timing closure in digital integrated circuits by optimizing individual macros'20066,922,819'System and method of optimal waveform shaping'20056,826,733'Parameter variation tolerant method for circuit design optimization'20046,321,362'Method of reformulating static circuit optimization problems for reduced size, degeneracy and redundancy'20015,999,714'Method for incorporating noise considerations in automatic circuit optimization'19995,886,908'Method of efficient gradient computation'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2021Patents assigned to IBM (100)· patent assignee history
1999–2021Based in Croton-on-Hudson, NY, US· patent location history
2011–2018Patents assigned to VISWESWARIAH CHANDRAMOULI (27)· patent assignee history
2011–2014Patents assigned to ZOLOTOV VLADIMIR (13)· patent assignee history
2011–2018Patents assigned to HEMMETT JEFFREY G (10)· patent assignee history
2012–2018Patents assigned to VENKATESWARAN NATESAN (13)· patent assignee history
2012Based in Hopewell Junction, NY, US· patent location history
2013–2014Based in Yorktown Heights, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM1001999–2021
VISWESWARIAH CHANDRAMOULIself272011–2018
VENKATESWARAN NATESAN132012–2018
ZOLOTOV VLADIMIR132011–2014
HEMMETT JEFFREY G102011–2018
Locations
LocationPatentsSpan
Croton-on-Hudson, New York, US961999–2021
Yorktown Heights, New York, US42013–2014
Hopewell Junction, New York, US12012