Digital-to-analog converter using dual-gate transistors

The present invention relates to the field of integrated circuits; more specifically, to digital-to-analog converters using dual-gate transistors.

Digital-to-analog converter (DAC) circuits are well known in the integrated circuit art. These are circuits that convert a digital word comprising N bits to an equivalent analog signal, typically either voltage or current. One of the most common approaches to implementing a linear DAC on an integrated circuit is what is known as a “current-mode DAC”. In this case, the output current is produced by a plurality of binary weighted current sources connected to respective switches whose outputs are, in turn, connected to the common analog output.

Typically, the switches are implemented using CMOS pass gates or CMOS (or bipolar) differential pairs. Since the actual DAC output current flows through the switches, the switches must be sized properly to avoid introducing non-linearity into the DAC transfer function. Most typically, these switch sizes are also binary weighted, each one matching the current mirror group to which it is connected. These switches lead to increased area and reduced performance in the DAC.

Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.

A first aspect of the present invention is a digital to analog converter, comprising: a current mirror comprising N stages, each stage comprising 2 n−1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, each input of the N inputs connected to a different and respective stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.

The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a circuit diagram of an exemplary digital-to-analog converter according to embodiments of the present invention.

FIG. 2 is a plot of drain current versus first gate voltage as a function of second gate voltage for a dual gate finNFET;

FIG. 3 is an exemplary three-dimension diagram of a dual gate finFET; and

FIG. 4 is an exemplary cross-section view of a dual gate FET.

In all of the embodiments of the present invention, equation (1) represents the output signal of a DAC:

Analog Out=( X full-scale /2 N )*Σ(digital bit n )*2 n   (1)

where:

n takes on all integer values between 0 and N−1, N is the number of bits in the digital input word and the number of stages in the DAC, and X full-scale is some full-scale analog value whose units are current.

This transfer function between the digital input bits and the analog output has a familiar shape that looks like a staircase; the “risers” occur at the integer values between 1 and 2 N −1 and the “treads” are the analog levels given by equation (1).

FIG. 1 is a circuit diagram of an exemplary digital-to-analog converter 100 according to embodiments of the present invention. In FIG, 1 , DAC 100 includes a reference circuit 105 and a current mirror/switch 110 arranged in N stages. In FIG. 1 , only the first three stages (stage 1 , stage 2 and stage 3 ) of DAC 100 are illustrated. The last stage would be stage N. Reference circuit includes a dual gate transistor T 0 and a current source Iref. The three stages of current mirror/switch array 110 illustrated in FIG. 1 include dual gated transistors T 1 of stage 0 , dual gated transistors T 2 and T 3 of stage 1 and dual gated transistors T 4 , T 5 , T 6 and T 7 of stage 3 . Subsequent stages would have 2 N−1 dual gated transistors, with N being the stage number. So stage 4 would have eight (2 3 ) dual gated transistors, stage 5 would have sixteen (2 4 ) dual gated transistors and so forth to stage N which would have 2 N−1 dual gated transistors. A dual gate transistor is defined as a transistor having two gates on opposite sides of a channel region of a field effect transistor (FET), the gates being electrically isolated from each other.

In a one embodiment of the present invention all dual gated transistors T 0 through T 7 are n-channel field effect transistors (NFETs) as are all dual gated transistors of stages 4 through N not illustrated in FIG. 1 . For the purposes of describing FIG. 1 , dual gated transistors T 0 through T 7 will be described as NFETs. Current source Iref is connected between VDD and a current reference node REF. The drain of dual gate transistor T 0 is connected to current reference node REF and the source of dual gated transistor is connected to GND. A first gate of dual gate transistor T 0 is connected to current reference node REF and a second gate of dual gate transistor T 0 is connected to VDD. The drains of all dual gated transistors T 1 through T 7 and those of stages 4 through N not illustrated in FIG. 1 are connected to an output pin OUT of DAC 100 . The sources of all dual gated transistors T 1 through T 7 and those of stages 4 through N not illustrated in FIG. 1 are connected to a GND. The first gates of all dual gated transistors T 1 through T 7 and those of stages 4 through N not illustrated in FIG. 1 are connected to current reference node REF. The second gates of all dual gated transistors T 1 through T 7 and those of stages 4 through N not illustrated in FIG. 1 are connected to respective input pins Bit 0 through Bit N−1 (input pins Bit 3 through Bit N−1 are not illustrated in FIG. 1 ) of DAC 100 corresponding to the stage containing the particular dual gated transistor. Thus, in stage 1 the second gate of dual gate transistor T 1 is connected to an input pin Bit 0 , in stage 2 the second gates of dual gate transistors T 2 and T 3 are connected to input pin Bit 1 , in stage 3 the second gates of dual gate transistors T 4 , T 5 , T 6 and T 7 are connected to input pin Bit 2 and so forth through all the second gates of the dual gate transistors of stage N (not shown) being connected to input pin Bit N−1 (not shown). VDD may be considered as the higher voltage potential terminal and GND the lower voltage potential of a power supply. In one example, VDD is a positive voltage potential and GND is a zero voltage potential.

In one example, when a substantially non-zero gate-to-source voltage is applied to a particular input of the Bit 0 through Bit N−1 inputs, a current flowing through corresponding dual gate transistors increases by at least an order of magnitude over a current flowing through those dual gate transistors when a substantially zero gate-to-source voltage is applied to the particular input.

In an another embodiment of the present invention all dual gated transistors T 0 through T 7 are p-channel field effect transistors (PFETs) as are all dual gated transistors of stages 4 through N not illustrated in FIG. 1 . When dual gated transistors T 0 through T 7 are PFETs, the connections of the source and drains would be reversed (i.e., for PFETs the sources of all the dual gated transistors are connected to VDD and the drains of all the dual gate transistors are connected to an output pin OUT of DAC 100 . This is accomplished by swapping the VDD and GND connection illustrated in FIG. 1 , so current source Iref is connected between GND and current reference node REF.

In one example, current source Iref comprises a resistor. In one example current source Iref comprises a PFET. In one example, all dual-gated transistors of DAC 100 are identically designed.

FIG. 2 is a plot of drain current versus first gate voltage as a function of second gate voltage for a dual gate finNFET. A finFET is illustrated in FIG. 3 and described infra. In FIG. 2 , the drain current of a dual gate finNFET versus the voltage on the first gate of dual gate finNFET is plotted for various voltages applied to the second gate of the finNFET. It can be seen, for example, by changing the second gate voltage from 0 volts to 1.0 volt while holding the first gate voltage constant at 0.5 volts, a change in drain current of about 3 to about 4 orders of magnitude results. This indicates that the first gate of a dual gated device can be configured (or connected) as in a current mirror and the second gate used as a switch connected to a DAC input pin. In conventional DACs, these functions require different transistors, so the DAC according to the embodiments of the present invention using dual gate transistors reduces the number of transistors required in the switch/mirror section by half with a corresponding reduction in the amount of integrated chip area used by the DAC.

FIG. 3 is an exemplary three-dimension diagram of a dual gate finFET 115 . In FIG. 3 , dual gate finFET 115 is constructed on a top surface of a dielectric layer 120 formed on a substrate 125 . FinFET 115 includes a source 130 A and a drain 130 B separated by a body region 135 , all formed in a silicon fin 140 (e.g., a block of single-crystal silicon). First and second gate dielectric layers 145 A and 145 B are formed on opposite sidewalls of fin 140 in body region 135 . First and second gates 150 A and 150 B (e.g., polysilicon gates) are formed on respective first and second gate dielectric layers 145 A and 145 B. For a finNFET, source 130 A and drain 130 B are doped n-type and body region 135 is doped p-type. For a finPFET, source 130 A and drain 130 B are doped p-type and body region 135 is doped n-type. First gate 150 A is electrically isolated from second gate 150 B.

FIG. 4 is an exemplary cross-section view of a dual gate FET. In FIG. 4 , a dual gate FET 155 includes a source 160 and a drain 165 separated by a body region 170 , Formed on opposite surfaces of body region 170 between source 160 and drain 165 are gate dielectric layers 175 and 180 . Formed on respective first and second gate dielectric layers 175 and 180 are first and second gates 185 and 190 . For an NFET, source 160 and drain 165 are doped n-type and body region 170 is doped p-type. For a PFET, source 160 and drain 165 are doped p-type and body region 170 is doped n-type. First gate 185 is electrically isolated from second gate 190 . FET 155 is surrounded by dielectric isolation 195 on a substrate. As shown in FIG. 4 , current flow 200 from source 160 through body region 170 to drain 165 is substantially parallel to a top surface 202 of the substrate, so FET 155 is defined as a vertical dual gated FET. By rotating FIG. 4 90° to the left, current flow 200 from source 160 through body region 170 to drain 165 is substantially perpendicular to a new top surface 204 of the substrate, then FET 155 is defined as a lateral dual gated FET. One difference between dual gated finFETs and vertical and lateral FETs is the fabrication process.

Thus the present invention provides DACs that comprise fewer transistors and uses less integrated circuit area than conventional DACs and thus overcome the deficiencies and limitations described supra.

The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.