Inventor

Wagdi W. Abadeer

Inventor

Jericho, VT, US

Overview

80→

Patents

1994–2016

Patent span

Electricity

Primary field (CPC H)

Patents· 80 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices25%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%

G01RMeasuring electric variables7%

H03KPulse technique7%

G11CStatic stores5%

G06FElectric digital data processing4%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%

G05FSystems for regulating electric or magnetic variables3%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%

PatentTitleYear

9,263,517'Extremely thin semiconductor-on-insulator (ETSOI) layer'2016 8,562,210'Thermal sensor for semiconductor circuits'2013 8,413,094'Structure, design structure and process for increasing magnitude of device threshold voltage for low power applications'2013 8,349,697'Field effect transistor with air gap dielectric'2013 8,232,177'Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure'2012 8,216,909'Field effect transistor with air gap dielectric'2012 8,110,483'Forming an extremely thin semiconductor-on-insulator (ETSOI) layer'2012 8,035,452'Structure for transforming an input voltage to obtain linearity between input and output functions and system and method thereof'2011 8,021,950'Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation'2011 7,977,201'Methods for forming back-end-of-line resistive semiconductor structures'2011 7,939,395'High-voltage SOI MOS device structure and method of fabrication'2011 7,939,911'Back-end-of-line resistive semiconductor structures'2011 7,932,552'Multiple source-single drain field effect semiconductor device and circuit'2011 7,915,571'On demand circuit function execution employing optical sensing'2011 7,916,531'Memory elements and methods of using the same'2011 7,904,658'Structure for power-efficient cache memory'2011 7,872,310'Semiconductor structure and system for fabricating an integrated circuit chip'2011 7,873,921'Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal'2011 7,847,605'Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal'2010 7,839,206'Design structure for low voltage applications in an integrated circuit'2010 7,825,469'Threshold voltage compensation for pixel design of CMOS image sensors'2010 7,814,449'Design structure for multiple source-single drain field effect semiconductor device and circuit'2010 7,804,124'Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory'2010 7,795,940'Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures'2010 7,791,010'CMOS image sensor having a third FET device with the gate terminal coupled to the diffusion region of a first FET device, the second terminal coupled to a column signal line, and the first terminal coupled to a row select signal'2010 7,790,524'Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures'2010 7,790,564'Methods for fabricating active devices on a semiconductor-on-insulator substrate utilizing multiple depth shallow trench isolations'2010 7,790,543'Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures'2010 7,763,531'Method and structure to process thick and thin fins and variable fin to fin spacing'2010 7,709,926'Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit'2010 7,700,428'Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory'2010 7,692,130'CMOS imaging sensor having a third FET device with a gate terminal coupled to a second diffusion region of a first FET device and a first terminal coupled to a row select signal'2010 7,687,883'Electronically programmable antifuse and circuits made therewith'2010 7,659,497'On demand circuit function execution employing optical sensing'2010 7,622,946'Design structure for an automatic driver/transmission line/receiver impedance matching circuitry'2009 7,573,300'Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same'2009 7,548,080'Method and apparatus for burn-in optimization'2009 7,545,298'Design structure for a digital-to-analog converter using dual-gate transistors'2009 7,545,297'Digital-to-analog converter using dual-gate transistors'2009 7,498,869'Voltage reference circuit for low voltage applications in an integrated circuit'2009 7,477,541'Memory elements and methods of using the same'2009 7,473,904'Device for monitoring ionizing radiation in silicon-on insulator integrated circuits'2009 7,473,970'Concurrent fin-fet and thick body device fabrication'2009 7,471,114'Design structure for a current control mechanism for power networks and dynamic logic keeper circuits'2008 7,466,171'Voltage detection circuit and circuit for generating a trigger flag signal'2008 7,375,339'Monitoring ionizing radiation in silicon-on insulator integrated circuits'2008 7,358,823'Programmable capacitors and methods of using the same'2008 7,326,987'Non-continuous encapsulation layer for MIM capacitor'2008 7,301,210'Method and structure to process thick and thin fins and variable fin to fin spacing'2007 7,297,582'Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions'2007 7,262,987'SRAM cell using tunnel current loading devices'2007 7,253,066'MOSFET with decoupled halo before extension'2007 7,227,239'Resettable fuse device and method of fabricating the same'2007 7,215,002'Electronically programmable antifuse and circuits made therewith'2007 7,167,053'Integrated circuit amplifier device and method using FET tunneling gate current'2007 7,163,851'Concurrent Fin-FET and thick-body device fabrication'2007 7,141,998'Method and apparatus for burn-in optimization'2006 7,132,325'Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure'2006 7,087,499'Integrated antifuse structure for FINFET and CMOS devices'2006 7,061,308'Voltage divider for integrated circuits'2006 6,982,591'Method and circuit for compensating for tunneling current'2006 6,917,319'Digital to analog converter using tunneling current element'2005 6,913,965'Non-Continuous encapsulation layer for MIM capacitor'2005 6,879,021'Electronically programmable antifuse and circuits made therewith'2005 6,876,035'High voltage N-LDMOS transistors having shallow trench isolation region'2005 6,770,907'Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure'2004 6,730,552'MOSFET with decoupled halo before extension'2004 6,731,179'System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI)'2004 6,714,113'Inductor for integrated circuits'2004 6,624,031'Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure'2003 6,602,772'Method for non-contact stress evaluation of wafer gate dielectric reliability'2003 6,326,732'Apparatus and method for non-contact stress evaluation of wafer gate dielectric reliability'2001 6,278,339'Termination resistance independent system for impedance matching in high speed input-output chip interfacing'2001 6,249,193'Termination impedance independent system for impedance matching in high speed input-output chip interfacing'2001 6,188,234'Method of determining dielectric time-to-breakdown'2001 6,140,885'On-chip automatic system for impedance matching in very high speed input-output chip interfacing'2000 6,049,213'Method and system for testing the reliability of gate dielectric films'2000 5,929,667'Method and apparatus for protecting circuits subjected to high voltage'1999 5,418,738'Low voltage programmable storage element'1995 5,334,880'Low voltage programmable storage element'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2013Patents assigned to IBM (79)· patent assignee history

1994–2016Based in Jericho, VT, US· patent location history

2011–2012Based in Essex Junction, VT, US· patent location history

2011Based in Jerico, VT, US· patent location history

2012–2013Patents assigned to CHATTY KIRAN V (4)· patent assignee history

2012–2013Patents assigned to ABADEER WAGDI W (3)· patent assignee history

2012–2013Patents assigned to GAUTHIER JR ROBERT J (3)· patent assignee history

2012–2013Patents assigned to RANKIN JED H (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	79	1994–2013
CHATTY KIRAN V	4	2012–2013
ABADEER WAGDI Wself	3	2012–2013
GAUTHIER JR ROBERT J	3	2012–2013
RANKIN JED H	3	2012–2013

Locations

Location	Patents	Span
Jericho, VT, US	76	1994–2016
Essex Junction, VT, US	3	2011–2012
Jerico, VT, US	1	2011