Inventor

Joseph A. Iadanza

Inventor

Hinesburg, VT, US

Overview

1996–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 87 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique24%

G06FElectric digital data processing23%

G11CStatic stores11%

G01RMeasuring electric variables8%

H04LTransmission of digital information, e.g. telegraphic communication7%

H10DInorganic electric semiconductor devices6%

H03MCoding5%

G05FSystems for regulating electric or magnetic variables4%

H03HImpedance networks, e.g. resonant circuits3%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%

PatentTitleYear

11,016,144Testing integrated circuit designs containing multiple phase rotators2021 10,761,136Testing integrated circuit designs containing multiple phase rotators2020 10,585,140Testing integrated circuit designs containing multiple phase rotators2020 9,927,489'Testing integrated circuit designs containing multiple phase rotators'2018 9,070,791'Tunable capacitor'2015 8,988,140'Real-time adaptive voltage control of logic blocks'2015 8,978,005'Network reconfiguration in a data converter for improved electrical characteristics'2015 8,841,893'Dual-loop voltage regulator architecture with high DC accuracy and fast response time'2014 8,803,722'Resistor-2 resistor (R-2R) digital-to-analog converter with partial resistor network reconfiguration'2014 8,793,365'Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes'2014 8,711,022'Resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal'2014 8,643,987'Current leakage in RC ESD clamps'2014 8,302,037'Skewed double differential pair circuit for offset cancellation'2012 7,932,774'Structure for intrinsic RC power distribution for noise filtering of analog supplies'2011 7,932,641'Low voltage head room detection for reliable start-up of self-biased analog circuits'2011 7,932,552'Multiple source-single drain field effect semiconductor device and circuit'2011 7,898,286'Critical path redundant logic for mitigation of hardware across chip variation'2011 7,868,809'Digital to analog converter having fastpaths'2011 7,823,107'Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design'2010 7,821,053'Tunable capacitor'2010 7,814,449'Design structure for multiple source-single drain field effect semiconductor device and circuit'2010 7,795,940'Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures'2010 7,793,237'System, structure and method of providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure'2010 7,770,139'Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path'2010 7,760,796'Transceiver for receiving and transmitting data over a network and method for testing the same'2010 7,755,420'Intrinsic RC power distribution for noise filtering of analog supplies'2010 7,743,270'Assigning clock arrival time for noise reduction'2010 7,729,159'Apparatus for improved SRAM device performance through double gate topology'2010 7,716,007'Design structures of powering on integrated circuit'2010 7,710,302'Design structures and systems involving digital to analog converters'2010 7,705,626'Design structure to eliminate step response power supply perturbation'2010 7,685,548'Detection method for identifying unintentionally forward-biased diode devices in an integrated circuit device design'2010 7,643,591'Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design'2010 7,579,897'Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices'2009 7,545,298'Design structure for a digital-to-analog converter using dual-gate transistors'2009 7,545,297'Digital-to-analog converter using dual-gate transistors'2009 7,511,548'Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees'2009 7,511,528'Device and method to eliminate step response power supply perturbation'2009 7,483,806'Design structures, method and systems of powering on integrated circuit'2009 7,479,819'Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees'2009 7,454,305'Method and apparatus for storing circuit calibration information'2008 7,449,942'Intrinsic RC power distribution for noise filtering of analog supplies'2008 7,429,877'Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path'2008 7,408,800'Apparatus and method for improved SRAM device performance through double gate topology'2008 7,404,114'System and method for balancing delay of signal communication paths through well voltage adjustment'2008 7,403,039'Flexible multimode logic element for use in a configurable mixed-logic signal distribution path'2008 7,362,138'Flexible multimode logic element for use in a configurable mixed-logic signal distribution path'2008 7,313,178'Transceiver for receiving and transmitting data over a network and method for testing the same'2007 7,307,467'Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices'2007 7,268,632'Structure and method for providing gate leakage isolation locally within analog circuits'2007 7,257,788'Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits'2007 7,218,135'Method and apparatus for reducing noise in a dynamic manner'2007 7,089,512'Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits'2006 7,000,214'Method for designing an integrated circuit having multiple voltage domains'2006 6,960,837'Method of connecting core I/O pins to backside chip I/O pads'2005 6,927,590'Method and circuit for testing a regulated power supply in an integrated circuit'2005 6,882,230'System and method for control parameter re-centering in a controlled phase lock loop system'2005 6,717,997'Apparatus and method for current demand distribution in electronic systems'2004 6,683,345'Semiconductor device and method for making the device having an electrically modulated conduction channel'2004 6,636,995'Method of automatic latch insertion for testing application specific integrated circuits'2003 6,545,521'Low skew, power sequence independent CMOS receiver device'2003 6,487,701'System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology'2002 6,334,169'System and method for improved bitwrite capability in a field programmable memory array'2001 6,298,458'System and method for manufacturing test of a physical layer transceiver'2001 6,233,191'Field programmable memory array'2001 6,130,854'Programmable address decoder for field programmable memory array'2000 6,118,707'Method of operating a field programmable memory array with a field programmable gate array'2000 6,091,645'Programmable read ports and write ports for I/O buses in a field programmable memory array'2000 6,075,745'Field programmable memory array'2000 6,044,031'Programmable bit line drive modes for memory arrays'2000 6,038,192'Memory cells for field programmable memory array'2000 6,023,421'Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array'2000 5,949,719'Field programmable memory array'1999 5,914,906'Field programmable memory array'1999 5,815,009'Process tolerant delay circuit having process sensitive and process insensitive components placed therein'1998 5,802,003'System for implementing write, initialization, and reset in a memory array using a single cell write port'1998 5,781,032'Programmable inverter circuit used in a programmable logic cell'1998 5,770,960'Process tolerant delay circuit'1998 5,748,009'Programmable logic cell'1998 5,745,422'Cross-coupled bitline segments for generalized data propagation'1998 5,719,889'Programmable parity checking and comparison circuit'1998 5,663,670'Controllable variable delay inverter for a process tolerant delay circuit'1997 5,651,013'Programmable circuits for test and operation of programmable gate arrays'1997 5,646,544'System and method for dynamically reconfiguring a programmable gate array'1997 5,646,546'Programmable logic cell having configurable gates and multiplexers'1997 5,631,578'Programmable array interconnect network'1997 5,548,237'Process tolerant delay circuit'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2021Patents assigned to IBM (87)· patent assignee history

1996–2021Based in Hinesburg, VT, US· patent location history

2012–2015Patents assigned to IADANZA JOSEPH A (6)· patent assignee history

2012–2014Patents assigned to ARSOVSKI IGOR (2)· patent assignee history

2012–2014Patents assigned to THIAGARAJAN PRADEEP (2)· patent assignee history

2012Based in Essex Junction, VT, US· patent location history

2015Patents assigned to BARROWS COREY K (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	87	1996–2021
IADANZA JOSEPH Aself	6	2012–2015
ARSOVSKI IGOR	2	2012–2014
THIAGARAJAN PRADEEP	2	2012–2014
BARROWS COREY K	1	2015

Locations

Location	Patents	Span
Hinesburg, VT, US	86	1996–2021
Essex Junction, VT, US	1	2012