Level shifter for semiconductor memory device implemented with low-voltage transistors

This application claims priority from European patent application No. EP06111337.9, filed Mar. 17, 2006, which is incorporated herein by reference.

This application is related to U.S. patent application Ser. No. 11/605,209, filed on Nov. 27, 2006, which has a common filing date and owner and which is incorporated by reference.

An embodiment of the present invention relates generally to the semiconductor memory device field, and more specifically to level shifters.

Semiconductor memory devices are commonly used to store information (either temporarily or permanently) in a number of applications; particularly, in a non-volatile memory device the information is preserved even when a power supply is off. Typically, the memory device includes a matrix of memory cells that are arranged in a plurality of rows (connected to corresponding word lines) and in a plurality of columns (connected to corresponding bit lines).

For example, flash memory devices are a particular type of non-volatile memory device, in which each memory cell is formed by a floating gate MOSFET transistor. Each memory cell has a threshold voltage (which depends on the electric charge stored in the corresponding floating gate), which can be programmed to different levels representing corresponding logical values. Particularly, in a multi-level flash memory device each memory cell can take more than two levels (and then store a plurality of bits).

In order to retrieve and/or store information, the flash memory device includes a decoding system that is adapted to decode an addressing code identifying a group of memory cells. In particular, the decoding system includes a row selector for selecting a corresponding word line and a column selector for selecting a corresponding set of bit lines. These selectors operate with logical signals at low voltages, of the order of a supply voltage of the flash memory device (such as 3V); for example, the logical signals can take two values equal to a reference voltage (0) or to the supply voltage (1).

However, the decoding system often must be able to apply operative voltages of high value to the selected memory cells (during program and erase operations). These voltages (for example, ranging from −9V to 9V) are higher than the supply voltage (in absolute value). For example, in single supply voltage memory devices, the high voltages are generated inside the flash memory device from the supply voltage, by means of suitable circuits (such as, charge pumps).

For this purpose, the decoding system includes level shifters, which are adapted to convert the logical signals from the selectors into the high voltages necessary during the program and erase operations; for example, during a program operation the level shifters shift the supply voltage used for selecting the desired word line to a program voltage to be applied thereto (such as, 9V).

Therefore, the selectors can be implemented with low voltage components that are designed in such a way to be able to sustain (between their terminals) voltage differences that are limited (in absolute value) by the supply voltage. Indeed, the low voltages that are experienced by those components allow their correct functioning, without causing breaking thereof. For example, those components are low-voltage MOSFET transistors, which are designed in such a way to avoid the occurrence of gate oxide breakdown or undesired junction breakdown when low voltage differences are applied to their terminals (for example, between the gate and source terminals).

Conversely, the level shifters typically must include high-voltage components that are designed in such a way to be able to sustain (between their terminals) voltage differences that are higher than the supply voltage (up to 9V in the case at issue). For example, those components are high-voltage MOSFET transistors, which are designed in such a way to avoid the occurrence of gate oxide breakdown or undesired junction breakdown even when high voltages are applied to their terminals.

The high-voltage transistors have a gate oxide layer thicker than that used for the low voltage transistors. Indeed, the thicker the gate oxide layer the higher the voltage sustained at their terminals without undesired breakdown. Since the high-voltage transistors typically occupy more silicon area compared to the low-voltage transistors, the level shifters may waste a significant area of a chip wherein the flash memory device is integrated.

This problem is more evident with the increment of the number of word lines included in the flash memory device.

Moreover, the use of both low- and high-voltage transistors often increases the number of processing steps and masks (for example, for differentiating the oxide thickness of the high- and low-voltage transistors); this may have a detrimental impact on the manufacturing process of the flash memory device.

An embodiment of the present invention is based on the idea of using components working at reduced voltage.

In detail, an embodiment of the present invention proposes a level shifter. The level shifter includes a stage having a first branch and a second branch. Each branch includes a selection terminal for receiving a selection signal; the selection signal received by the first branch and the second branch is alternatively at a first voltage and at a second voltage (higher than the first voltage in absolute value). The branch also includes a service terminal for receiving a third voltage (higher than the second voltage in absolute value). An input circuit is used for coupling an intermediate node to the selection terminal when at the second voltage, or for insulating the intermediate node from the selection terminal otherwise. The branch further includes an interface circuit for coupling an output terminal to the intermediate node when coupled or for insulating the output terminal from the intermediate node otherwise. At the end, an output circuit is used for insulating the service terminal from the output terminal when coupled, or for coupling the service terminal to the output terminal otherwise. The output terminals of the first branch and the second branch provide an output signal, which is alternatively at the second voltage or at the third voltage according to the selection signal.

In an embodiment of the invention, the input circuit of each branch includes an input transistor between the intermediate node and the selection terminal.

In a further embodiment of the invention, the interface circuit includes an interface transistor between the intermediate node and the output terminal.

Advantageously, the interface transistor is biased for its turning on.

In a further embodiment of the invention, the output circuit of each branch includes an output transistor between the output terminal and the service terminal.

The level shifter may have two or more stages that are cascade connected.

The level shifter may be implemented by means of low voltage transistors.

In an embodiment of the invention, the input and output transistors are of a first type of conductivity (such as p-channel MOSFET transistors) and the interface transistors are of the opposite type of conductivity (such as n-channel MOSFET transistors).

An embodiment is applied to a non-volatile memory device.

Another embodiment of the present invention is a corresponding method.

One or more embodiments of the invention, as well as features and advantages thereof, may be understood by reference to the following detailed description, given purely by way of a non-restrictive indication, to be read in conjunction with the accompanying drawings.

FIG. 1 is a schematic block diagram of a memory device in which the solution according to an embodiment of the invention can be used.

FIG. 2 is an exemplary implementation of a level shifter known in the art.

FIG. 3 shows a level shifter according to an embodiment of the invention.

FIG. 4 shows a level shifter according to a further embodiment of the invention.

Referring to FIG. 1 , a flash memory device 100 is represented. The memory device 100 includes one or more sectors 105 (only one shown). The sector 105 include a plurality of memory cells MC, each one including a floating-gate MOSFET transistor. In particular, the memory device 100 is of the flash type, wherein the memory cells MC of each sector 105 are erased at the same time.

In an erased condition, each memory cell MC has a low threshold voltage (to which a logical level “1” is typically associated). The memory cell MC is programmed by injecting electrons into its floating-gate; in this condition the memory cell MC has a high threshold voltage (to which a logical level “0” is typically associated).

In each sector 105 , the memory cells MC are arranged in rows and columns. The memory cells MC of each column have the drain terminals connected to a respective bit line BL, while the memory cells MC of each row have the gate terminals connected to a respective word line WL. The source terminal of each memory cell MC receives a reference voltage GND (or ground).

The memory device 100 further includes a PMU (acronym for Power Management Unit) 110 . The PMU 110 provides the biasing voltages that are used for performing the conventional operations (such as read, program, erase and verify) on the memory device 100 . The PMU 110 receives a supply voltage Vdd (such as 3V) externally and outputs different operative voltages Vhv; the operative voltages Vhv are generally higher in absolute value than the supply voltage Vdd, for example, ranging from −9V to 9V. For this purpose, the PMU 110 includes a circuitry (e.g., charge pumps) adapted to generate the operative voltages Vhv from the supply voltage Vdd. These charge pumps may be implemented by means of low voltage transistors only, as described in U.S. patent application Ser. No. 11/605,209, filed on Nov. 27, 2006 (the entire disclosure of which is previously incorporated by reference).

Moreover, the memory device 100 receives an addressing code ADD for accessing the memory cells MC. The addressing code ADD includes a logical signal formed by a set of bits (such as 8-32); each bit may be at the supply voltage Vdd (for example, logical level “1”) or at the ground voltage GND (for example, logical level “0”). A portion of the addressing code ADD is supplied to a column decoder 120 , which selects a set of desired bit lines BL (such as 8). Another portion of the addressing code ADD is supplied to a row decoder 125 , which selects one desired word line WL.

The column decoder 120 couples the selected bit lines BL to a read-write circuit 130 . The read/write circuit 130 includes all the components (e.g., sense amplifiers, comparators, reference current/voltage generators, pulse generators, program load circuits and the like), which are normally required for writing the desired logical values into the selected memory cells MC and for reading the logical values currently stored therein. The read/write circuit 130 is coupled to externally-accessible terminals of the memory device 100 (not shown in FIG. 1 ) for receiving/delivering data.

The row decoder 125 includes a selector 132 , which receives the corresponding portion of the addressing code ADD and provides a (logical) selection signal Vp for each word line WL; for example, the selection signal Vp of the selected word line WL is asserted (at the logical value 1) whereas the other selection signals Vp are deasserted (at the logical value 0). Each selection signal Vp is provided to a corresponding level shifter 135 . The level shifter 135 converts the logical value of the selection signal Vp (GND−Vdd) to one of the operative voltages Vhv (from −9V to 9V, according to the operations to be performed on the memory device 100 ).

Referring to FIG. 2 , a schematic representation of a generic level shifter 135 known in the art is shown. The level shifter 135 includes an inverter 203 , for example of CMOS type, and a shifter circuit 205 . The inverter 203 is supplied between the voltages Vdd and GND. The inverter 203 receives the selection signal Vp from the selector (not shown in the figure) and provides a corresponding complemented selection signal Vp# to the shifter circuit 205 . The shifter circuit 205 has a latch structure that includes two p-channel MOSFET transistors P 1 and P 2 and two n-channel MOSFET transistors N 1 and N 2 . The transistors P 1 and P 2 have the source terminals that receive one of the operative voltages Vhv, such as a program voltage POSV (for example, POSV=9V). The transistors N 1 and N 2 have the corresponding drain terminals that are connected to the drain terminals of the transistors P 1 and P 2 , respectively. The gate terminal of the transistor P 1 is connected to the drain terminal of the transistor P 2 , which provides an output signal OUT to the corresponding word line (not shown in the figure); the gate terminal of the transistor P 2 is connected to the drain terminal of the transistor P 1 .

The transistors N 1 and N 2 have the source terminals that receive the reference voltage GND. The gate terminal of the transistor N 2 directly receives the selection signal Vp. The transistor N 1 has the gate terminal that receives the complemented selection signal Vp# from the inverter 203 .

When the selection signal Vp is asserted (at the supply voltage Vdd) the complemented selection signal Vp# is deasserted (at the reference voltage GND). In this biasing condition, the transistor N 2 is on. Therefore, the output signal OUT is brought to the reference voltage GND.

At the same time, the transistor N 1 is off. As a result, the transistor P 1 is on (because its gate terminal receives the reference voltage GND by means of the transistor N 2 ). However, the transistor P 1 is connected in series to the transistor N 1 , thus both the transistors N 1 and P 1 cannot conduct any current because the transistor N 1 is off. The transistor P 1 has the drain terminal that is brought to the program voltage POSV. In this biasing condition, the transistor P 2 is also off, so as not to interfere with the output signal OUT.

On the contrary, when the selection signal Vp is deasserted and the complemented selection signal Vp# is asserted, the transistor N 1 is on and the transistor N 2 is off. In this way, the transistor P 2 is turned on and the transistor P 1 is turned off, so as to bring the output signal OUT to the program voltage POSV.

In the level shifter 135 the driving voltage of the transistors N 1 and N 2 (between the gate and source/drain terminals) may reach the program voltage POSV=9V, when they are driven (at the gate terminals) by the reference voltage GND and receive the program voltage POSV at the drain terminals (through the transistors P 2 and P 1 , respectively). Likewise, the driving voltage of the transistors P 1 and P 2 may reach the program voltage POSV=9V, when they are driven by the reference voltage GND (through the transistors N 1 and N 2 , respectively). Thus, the driving voltage of the transistors N 1 , N 2 , P 1 and P 2 is higher than the supply voltage Vdd. The transistors P 1 , P 2 , N 1 and N 2 are then designed in such a way to guarantee the capability of sustaining, between their gate terminal and any other terminal thereof, voltage differences up to the program voltage POSV.

For this purpose, the transistors P 1 , P 2 , N 1 and N 2 have a thick gate oxide layer. In other words, the transistors P 1 , P 2 , N 1 and N 2 are high-voltage transistors (with the drawbacks previously discussed).

Referring now to FIG. 3 , a level shifter according to an embodiment of the present invention is schematically shown (this implementation is differentiated by adding an apex to its reference, i.e., 135 ′).

In particular, the level shifter 135 ′ includes an input circuit 305 that is coupled to an interface circuit 310 . The interface circuit 310 is in turn coupled to an output circuit 315 .

More in detail, the input circuit 305 includes two p-channel MOSFET transistors M 1 and M 2 and an inverter 320 , which is supplied between the voltages Vdd and GND. As above, the inverter 320 receives the selection signal Vp and provides the complemented selection signal Vp#.

The gate terminal of the transistor M 2 receives the selection signal Vp and the gate terminal of the transistor M 1 receives the complemented selection signal Vp# (through the inverter 320 ). The drain terminal of the transistor M 2 is connected to the gate terminal of the transistor M 1 , and the gate terminal of the transistor M 2 is connected to the drain terminal of the transistor M 1 .

The source terminals of the transistors M 1 and M 2 (denoted as intermediate nodes IN 1 and IN 2 , respectively) are connected to the interface circuit 310 . In particular, the interface circuit 310 includes two n-channel MOSFET transistors M 3 and M 4 . The transistors M 3 and M 4 have the source terminals connected to the intermediate nodes IN 1 and IN 2 , respectively, and the drain terminals that are connected to the output circuit 315 (denoted as output nodes OUT 1 and OUT 2 , respectively). Moreover, the gate terminals of the transistors M 3 and M 4 are connected together and receive a predetermined gate voltage VG 1 . The gate voltage VG 1 is higher than the supply voltage Vdd; more specifically, in one embodiment, the gate voltage VG 1 is at least equal to the supply voltage Vdd plus a typical threshold voltage of the transistors M 3 and M 4 , such as VG 1 =3V+1V=4V. For example, the gate voltage VG 1 is provided by means of a voltage regulator which is included in the PMU of the memory device.

The output circuit 315 has a latch structure as in FIG. 2 , which is implemented by two p-channel MOSFET transistors M 5 and M 6 (with the node OUT 2 that provides a different output signal OUT′). In this case, the source terminals of the transistors M 5 and M 6 receive one of the operative voltages Vhv (denoted with POSV 1 ), which is equal at most to twice the supply voltage Vdd (for example, POSV=6V).

In other words, the level shifter 135 ′ has first and second circuital branches, wherein the first branch includes the transistors Ml, M 3 , M 5 (connected in series) and the second branch includes the transistors M 2 , M 4 and M 6 (connected in series).

During operation of the level shifter 135 ′, when the selection signal Vp is asserted (at the supply voltage Vdd), the complemented selection signal Vp# is deasserted (at the reference voltage GND). In this biasing condition, the transistor M 1 is on. Thus, the transistor M 1 brings the intermediate node IN 1 to the supply voltage Vdd. The transistor M 3 is turned on as well. In this way, the voltage of the output node OUT 1 reaches the supply voltage Vdd. As a result, the transistor M 6 is turned on and the output node OUT 2 is brought to the operative voltage POSV 1 .

In this biasing condition, the transistor M 5 is off (because its driving voltage is equal to zero), so that the output node OUT 1 remains at the supply voltage Vdd. Since the transistor M 2 is off, the transistor M 4 cannot conduct any current as well.

On the contrary, when the selection signal Vp is deasserted (at the reference voltage GND), the transistors M 2 , M 4 and M 5 are turned on and the transistors M 1 , M 3 and M 6 are turned off, so as to bring the output node OUT 2 to the supply voltage Vdd (with the output node OUT 1 that is at the operative voltage POSV 1 ).

As can be noted, during the operation of the level shifter 135 ′, each transistor M 1 -M 6 sustains (between its gate terminal and any other terminal thereof) voltage differences at most equal to the supply voltage Vdd.

Particularly, thanks to the interface circuit 310 , when the transistors M 5 and M 6 are on they are driven by the supply voltage Vdd (and not by the reference voltage GND as in the preceding case); therefore, their driving voltage remains equal to POSV 1 −Vdd and then at most equal to Vdd (being POSV 1 ≦2Vdd). Likewise, when the transistors M 1 and M 2 are off they receive the supply voltage Vdd at the drain terminals through the transistors M 3 and M 4 , respectively (instead of the operative voltage POSV 1 ).

In such a way, the level shifter 135 ′ can be implemented with only low-voltage transistors.

Therefore, it is possible to avoid the use of high-voltage transistors having thick oxide layers (capable of sustaining voltages higher than the supply voltage Vdd). This may reduce the area occupied by the memory device in a chip of semiconductor material where it is integrated.

Moreover, the number of processing steps and masks may be reduced significantly: this may have a beneficial impact on the whole manufacturing process of the memory device.

However, in the level shifter 135 ′, if the operative voltages were higher than 2Vdd, the transistors M 5 and M 6 might experience driving voltages higher than the supply voltage Vdd (so that they might not be implementable with low-voltage transistors).

In order to overcome this limitation, a level shifter according to a further embodiment of the present invention is proposed in FIG. 4 (this implementation is differentiated by adding a double apex to its reference, i.e., 135 ″).

In particular, the level shifter 135 ″ includes the level shifter 135 ′ described above and a further (simplified) level shifter (which is differentiated by adding the index ‘s’ to its references). The simplified level shifter 135 ′ s has a circuital structure as the one of level shifter 135 ′ except for the lack of the inverter 320 . The level shifter 135 ′ and the level shifter 135 ′ s are cascade connected. More in particular, the gate terminal of the transistor M 1 s is coupled to the output node OUT 1 and the gate terminal of the transistor M 2 s is coupled to the output node OUT 2 .

Moreover, all the voltages applied to the transistors M 1 s -M 6 s are increased by the supply voltage Vdd. In detail, the transistors M 1 s and M 2 s are now driven alternatively by the supply voltage Vdd or the operative voltage POSV 1 (provided by the level shifter 135 ′). Moreover, the transistors M 3 s and M 4 s receive a gate voltage VG 2 that is equal to the operative voltage POSV 1 plus their threshold voltage, such as VG 2 =6V+1V=7V. Likewise, the source terminals of the transistors M 5 s and M 6 s receive one of the operative voltages Vhv (denoted with POSV 2 ), which is equal at most to three times the supply voltage Vdd (for example, POSV 2 =9V).

In this case, the output node OUT 2 s provides a higher output signal OUT″ to the corresponding word line (not shown in the figure).

As described above, when the selection signal Vp is asserted (at the supply voltage Vdd), the output node OUT 1 is at the supply voltage Vdd whereas the output node OUT 2 is at the operative voltage POSV 1 . The operation of the level shifter 135 s ′ is the same of the level shifter 135 ′, with the only difference that its voltages are shifted by the supply voltage Vdd. Particularly, in this biasing condition the transistor M 1 s is on, so bringing the intermediate node IN 1 s to the operative voltage POSV 1 . The transistor M 3 s is turned on as well. In this way, the voltage of the output node OUT 1 s reaches the operative voltage POSV 1 . As a result, the transistor M 6 s is turned on and the output node OUT 2 s is brought to the operative voltage POSV 2 .

In this biasing condition, the transistor M 5 s is off (because its driving voltage is equal to zero), so that the output node OUT 1 s remains at the operative voltage POSV 1 . Since the transistor M 2 s is also off, the transistor M 4 s cannot conduct any current.

On the contrary, when the selection signal Vp is deasserted (at the reference voltage GND), the transistors M 2 s , M 4 s and M 5 s are turned on and the transistors M 1 s , M 3 s and M 6 s are turned off, so as to bring the output node OUT 2 s (and thus the output signal OUT″) to the operative voltage POSV 1 (with the output node OUT 1 s that is at the operative voltage POSV 2 ).

As can be noted, during the operation of the level shifter 135 ″, each transistor M 1 s -M 6 s sustains (between its gate terminal and any other terminal thereof) voltage differences at most equal to the supply voltage Vdd.

Particularly, when the transistors M 5 s and M 6 s are on they are driven by the operative voltage POSV 1 ; therefore, their driving voltage remains equal to POSV 2 −POSV 1 and then at most equal to Vdd (being POSV 1 =2Vdd and POSV 2 =3Vdd). Likewise, when the transistors M 1 s and M 2 s are off they receive the supply voltage Vdd at their gate terminals and the operative voltage POSV 1 at their drain terminals (which difference is again at most equal to Vdd).

Therefore, it is now possible to shift the selection signal Vp (GND−Vdd) to a higher output signal OUT″ (POSV 1 −POSV 2 ) again using only low-voltage transistors. The same structure proposed above can be replicated by adding further stages, so as to work with operative voltages up to 4Vdd with 3 stages, 5Vdd with 4 stages, and so on.

Naturally, in order to satisfy local and specific requirements, a person skilled in the art may apply to the solution described above many modifications and alterations. Particularly, although the present invention has been described with a certain degree of particularity with reference to embodiments thereof, it should be understood that various omissions, substitutions and changes in the form and details as well as other embodiments are possible; moreover, it is expressly intended that specific elements and/or method steps described in connection with any disclosed embodiment of the invention may be incorporated in any other embodiment as a general matter of design choice.

For example, similar considerations apply if the level shifter has a similar structure even implemented with equivalent components. Moreover, it should be apparent that the numerical examples of the different voltages described above are merely illustrative and must not to be interpreted in a limitative manner.

Likewise, the input circuit, interface circuit and/or output circuit may have alternative schemes; for example, it is possible to implement the interface circuit with two or more transistors connected in series.

In any case, the use of other types of transistors (for example, bipolar junction transistors) is within the scope of the invention.

Moreover, the use of MOSFET transistor having a type of conductivity opposed to that of the transistors shown in the preceding description is contemplated (so as to work with negative voltages).

Similar considerations apply if the memory device has a different structure or includes equivalent components.

Likewise, it is possible to use the proposed solution for biasing the selected word lines during further operations performed on the memory device.

It should be noted that although in the preceding description reference has been made to the row decoder, this is not to be intended as a limitation; indeed, the same techniques can also be used for implementing a column decoder adapted for biasing the selected bit lines.

An electronic system, such as a computer system, may incorporate the memory device 100 of FIG. 1 , and may incorporate one or more other devices, such as a controller, coupled to the memory device.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.