Inventor

Rino Micheloni

Inventor

Turate, IT

Overview

1998–2021

Patent span

Physics

Primary field (CPC G)

Patents· 139 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores60%

G06FElectric digital data processing18%

H03MCoding12%

H03KPulse technique3%

G05FSystems for regulating electric or magnetic variables2%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%

G11BInformation storage based on relative movement between record carrier and transducer1%

G01RMeasuring electric variables1%

H04LTransmission of digital information, e.g. telegraphic communication1%

PatentTitleYear

10,891,083System and method for randomizing data2021 10,630,317Method for performing error corrections of digital information codified as a symbol sequence2020 10,332,613Nonvolatile memory system with retention monitor2019 10,291,263Auto-learning log likelihood ratio2019 10,283,215Nonvolatile memory system with background reference positioning and local reference positioning2019 10,230,396Method and apparatus for layer-specific LDPC decoding2019 10,157,677Background reference positioning and local reference positioning using threshold voltage shift read2018 10,152,273Nonvolatile memory controller and method for erase suspend management that increments the number of program and erase cycles after erase suspend2018 9,899,092'Nonvolatile memory system with program step manager and method for program step management'2018 9,892,794'Method and apparatus with program suspend using test mode'2018 9,886,214'Nonvolatile memory system with erase suspend circuit and method for erase suspend management'2018 9,813,080'Layer specific LDPC decoder'2017 9,799,405'Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction'2017 9,747,200'Memory system with high speed non-volatile memory backup using pre-aged flash memory devices'2017 9,590,656'System and method for higher quality log likelihood ratios in LDPC decoding'2017 9,454,414'System and method for accumulating soft information in LDPC decoding'2016 9,450,610'High quality log likelihood ratios determined using two-index look-up table'2016 9,448,881'Memory controller and integrated circuit device for correcting errors in data read from memory cells'2016 9,417,804'System and method for memory block pool wear leveling'2016 9,397,701'System and method for lifetime specific LDPC decoding'2016 9,305,661'Nonvolatile memory system that uses programming time to reduce bit errors'2016 9,235,467'System and method with reference voltage partitioning for low density parity check decoding'2016 9,128,858'Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values'2015 9,092,353'Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system'2015 8,990,661'Layer specific attenuation factor LDPC decoder'2015 8,971,112'Method of programming a multi-level memory device'2015 8,966,335'Method for performing error corrections of digital information codified as a symbol sequence'2015 8,707,122'Nonvolatile memory controller with two-stage error correction technique for enhanced reliability'2014 8,694,855'Error correction code technique for improving read stress endurance'2014 8,694,849'Shuffler error correction code system and method'2014 8,656,257'Nonvolatile memory controller with concatenated error correction codes'2014 8,621,318'Nonvolatile memory controller with error detection for concatenated error correction codes'2013 8,572,361'Configuration of a multilevel flash memory device'2013 8,553,462'Method of programming a multi-level memory device'2013 8,397,144'BCH data correction system and method'2013 8,347,201'Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code'2013 8,065,467'Non-volatile, electrically-programmable memory'2011 7,937,576'Configuration of a multi-level flash memory device'2011 7,908,543'Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code'2011 7,889,586'Circuit and method for retrieving data stored in semiconductor memory cells'2011 7,863,967'Multistage regulator for charge-pump boosted voltage applications'2011 7,777,466'Voltage regulator or non-volatile memories implemented with low-voltage transistors'2010 7,730,357'Integrated memory system'2010 7,719,894'Method of programming cells of a NAND memory device'2010 7,630,238'Page buffer for multi-level NAND electrically-programmable semiconductor memories'2009 7,592,849'Level shifter for semiconductor memory device implemented with low-voltage transistors'2009 7,581,153'Memory with embedded error correction codes'2009 7,532,061'Charge-pump type, voltage-boosting device with reduced ripple, in particular for non-volatile flash memories'2009 7,529,136'Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations'2009 7,521,983'High-voltage switch with low output ripple for non-volatile floating-gate memories'2009 7,499,345'Non-volatile memory implemented with low-voltages transistors and related system and method'2009 7,499,332'Circuit and method for electrically programming a non-volatile semiconductor memory via an additional programming pulse after verification'2009 7,474,577'Circuit and method for retrieving data stored in semiconductor memory cells'2009 7,444,543'Data control unit capable of correcting boot errors, and corresponding self-correction method'2008 7,408,819'Semiconductor memory device with a page buffer having an improved layout arrangement'2008 7,394,694'Flash memory device with NAND architecture with reduced capacitive coupling effect'2008 7,382,660'Method for accessing a multilevel nonvolatile memory device of the flash NAND type'2008 7,366,014'Double page programming system and method'2008 7,362,616'NAND flash memory with erase verify based on shorter evaluation time'2008 7,349,265'Reading method of a NAND-type memory device and NAND-type memory device'2008 7,336,538'Page buffer circuit and method for multi-level NAND programmable memories'2008 7,328,397'Method for performing error corrections of digital information codified as a symbol sequence'2008 7,260,005'Data bus architecture for a semiconductor memory'2007 7,221,212'Trimming functional parameters in integrated circuits'2007 7,221,602'Memory system comprising a semiconductor memory'2007 7,184,319'Method for erasing non-volatile memory cells and corresponding memory device'2007 7,184,348'Sensing circuit for a semiconductor memory'2007 7,068,540'Method and device for programming an electrically programmable non-volatile semiconductor memory'2006 7,035,142'Non volatile memory device including a predetermined number of sectors'2006 7,031,193'Method and device for programming an electrically programmable non-volatile semiconductor memory'2006 7,027,317'Semiconductor memory with embedded DRAM'2006 7,017,099'Method for error control in multilevel cells with configurable number of stored bits'2006 6,956,773'Circuit for programming a non-volatile memory device with adaptive program load control'2005 6,947,329'Method for detecting a resistive path or a predetermined potential in non-volatile memory electronic devices'2005 6,944,072'Self-repair method for nonvolatile memory devices with erasing/programming failure, and relative nonvolatile memory device'2005 6,922,366'Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory device'2005 6,901,011'Self-repair method via ECC for nonvolatile memory devices, and relative nonvolatile memory device'2005 6,891,755'Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more sectors'2005 6,871,258'METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE, AND AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE'2005 6,836,442'Nonvolatile memory device having a voltage booster with a discharge circuit activated during standby'2004 6,829,168'Power supply circuit structure for a row decoder of a multilevel non-volatile memory device'2004 6,822,905'Regulation method for the source terminal voltage in a non-volatile memory cell during a program phase and corresponding program circuit'2004 6,809,961'Regulation method for the drain, body and source terminals voltages in a non-volatile memory cell during a program phase and corresponding program circuit'2004 6,788,579'Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude'2004 6,728,141'Method and circuit for timing dynamic reading of a memory cell with control of the integration time'2004 6,724,658'Method and circuit for generating reference voltages for reading a multilevel memory cell'2004 6,674,385'Analog-to-digital conversion method and device, in high-density multilevel non-volatile memory devices'2004 6,650,173'Programmable voltage generator'2003 6,646,913'Method for storing and reading data in a multilevel nonvolatile memory'2003 6,643,179'Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell'2003 6,642,776'Bandgap voltage reference circuit'2003 6,639,833'Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics'2003 6,603,681'Method of pulse programming, in particular for high-parallelism memory devices, and a memory device implementing the method'2003 6,574,146'Circuit and method for timing multi-level non-volatile memories'2003 6,559,627'Voltage regulator for low-consumption circuits'2003 6,542,404'Small size, low consumption, multilevel nonvolatile memory'2003 6,532,171'Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory units'2003 6,515,911'Circuit structure for providing a hierarchical decoding in semiconductor memory devices'2003 6,504,758'Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding'2003 6,493,260'Nonvolatile memory device, having parts with different access time, reliability, and capacity'2002 6,493,268'Circuit device for performing hierarchic row decoding in non-volatile memory devices'2002 6,480,421'Circuit for reading non-volatile memories'2002 6,456,530'Nonvolatile memory device with hierarchical sector decoding'2002 6,456,527'Nonvolatile multilevel memory and reading method thereof'2002 6,456,150'Circuit for biasing a bulk terminal of a MOS transistor'2002 6,437,636'Low consumption voltage boost device'2002 6,433,583'CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching'2002 6,424,121'Voltage generator switching between alternating, first and second voltage values, in particular for programming multilevel cells'2002 6,418,051'Non-volatile memory device with configurable row redundancy'2002 6,404,273'Voltage booster with a low output resistance'2002 6,373,780'Single supply voltage nonvolatile memory device with row decoding'2002 6,356,481'Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages'2002 6,351,413'Nonvolatile memory device, in particular a flash-EEPROM'2002 6,327,184'Read circuit for a nonvolatile memory'2001 6,320,790'Biasing stage for biasing the drain terminal of a nonvolatile memory cell during the read phase'2001 6,307,396'Low-consumption TTL-CMOS input buffer stage'2001 6,307,778'Non volatile memory with detection of short circuits between word lines'2001 6,301,152'Non-volatile memory device with row redundancy'2001 6,301,149'Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory'2001 6,259,632'Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories'2001 6,259,635'Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories'2001 6,249,112'Voltage regulating circuit for a capacitive load'2001 6,237,104'Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory'2001 6,181,602'Device and method for reading nonvolatile memory cells'2001 6,169,423'Method and circuit for regulating the length of an ATD pulse signal'2001 6,157,579'Circuit for providing a reading phase after power-on-reset'2000 6,157,225'Driving circuit with three output levels, one output level being a boosted level'2000 6,144,589'Boosting circuit, particularly for a memory device'2000 6,128,225'Method and circuit for reading low-supply-voltage nonvolatile memory cells'2000 6,122,200'Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub-group of rows of a sector'2000 6,111,809'Line decoder for a low supply voltage memory device'2000 6,094,073'Line decoder for memory devices'2000 6,075,750'Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory'2000 6,069,837'Row decoder circuit for an electronic memory device, particularly for low voltage applications'2000 6,018,255'Line decoder for memory devices'2000 5,946,238'Single-cell reference signal generating circuit for reading nonvolatile memory'1999 5,903,498'Low-supply-voltage nonvolatile memory device with voltage boosting'1999 5,886,925'Read circuit and method for nonvolatile memory cells with an equalizing structure'1999 5,805,500'Circuit and method for generating a read reference signal for nonvolatile memory cells'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2021Based in Turate, IT· patent location history

1999–2009Patents assigned to ST MICROELECTRONICS SRL (81)· patent assignee history

2006Based in Turante, IT· patent location history

2008–2015Patents assigned to MICHELONI RINO (26)· patent assignee history

2008Based in Turatte, IT· patent location history

2009–2014Patents assigned to CRIPPA LUCA (13)· patent assignee history

2011–2015Patents assigned to MARELLI ALESSIA (9)· patent assignee history

2013–2016Patents assigned to PMC SIERRA US INC (10)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ST MICROELECTRONICS SRL	81	1999–2009
MICHELONI RINOself	26	2008–2015
CRIPPA LUCA	13	2009–2014
PMC SIERRA US INC	10	2013–2016
MARELLI ALESSIA	9	2011–2015

Locations

Location	Patents	Span
Turate, IT	137	1998–2021
Turatte, IT	1	2008
Turante, IT	1	2006