Inventor

Giovanni Campardo

Inventor

Bergamo, IT

Overview

1989–2021

Patent span

Physics

Primary field (CPC G)

Patents· 99 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores59%

G06FElectric digital data processing8%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%

H03KPulse technique4%

G05FSystems for regulating electric or magnetic variables3%

H01LSemiconductor devices3%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%

H10BElectronic memory devices2%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%

B81BMicrostructural devices or systems, e.g. micromechanical devices1%

PatentTitleYear

11,069,587Integrated semiconductor device and process for manufacturing an integrated semiconductor device2021 10,847,326Microelectromechanical device, which can be used as non-volatile memory module or relay, and memory including a plurality of microelectromechanical devices2020 10,706,924Non-volatile memory device, in particular phase change memory, and reading method2020 10,381,173Microelectromechanical device, which can be used as non-volatile memory module or relay, and memory including a plurality of microelectromechanical devices2019 10,249,373Circuit and method for reading a memory cell of a non-volatile memory device2019 10,002,672Memory device with progressive row reading and related reading method2018 9,971,536Controller to manage NAND memories2018 9,966,145Row decoder for a non-volatile memory device, and non-volatile memory device2018 9,865,356'Circuit and method for reading a memory cell of a non-volatile memory device'2018 9,805,810'Memory device with progressive row reading and related reading method'2017 9,767,907'Row decoder for a non-volatile memory device, having reduced area occupation'2017 9,679,655'Row decoder for a non-volatile memory device, and non-volatile memory device'2017 9,569,129'Controller to manage NAND memories'2017 9,213,603'Controller to manage NAND memories'2015 9,183,941'Thermal treatment of flash memories'2015 9,069,015'Interface board of a testing head for a test equipment of electronic devices and corresponding probe head'2015 8,984,370'Secondary memory to store error correction information'2015 8,958,242'Thermal treatment of flash memories'2015 8,928,123'Through via structure including a conductive portion and aligned solder portion'2015 8,880,979'Secondary memory to store a varying amount of overhead information'2014 8,806,293'Controller to execute error correcting code algorithms and manage NAND memories'2014 8,759,215'Method for forming bumps in substrates with through vias'2014 8,745,463'Error correcting codes for increased storage capacity in multilevel memory devices'2014 8,458,562'Secondary memory element for non-volatile memory'2013 8,370,702'Error correcting codes for increased storage capacity in multilevel memory devices'2013 8,228,684'Multi chip electronic system'2012 7,777,466'Voltage regulator or non-volatile memories implemented with low-voltage transistors'2010 7,675,788'Electronic non-volatile memory device having a cNAND structure and being monolithically integrated on semiconductor'2010 7,616,515'Integrated electronic device having a low voltage electric supply'2009 7,592,849'Level shifter for semiconductor memory device implemented with low-voltage transistors'2009 7,499,345'Non-volatile memory implemented with low-voltages transistors and related system and method'2009 7,184,319'Method for erasing non-volatile memory cells and corresponding memory device'2007 7,168,016'Method and a device for testing electronic memory devices'2007 7,035,142'Non volatile memory device including a predetermined number of sectors'2006 7,027,317'Semiconductor memory with embedded DRAM'2006 6,947,329'Method for detecting a resistive path or a predetermined potential in non-volatile memory electronic devices'2005 6,944,061'Single cell erasing method for recovering memory cells under programming disturbs in non volatile semiconductor memory devices'2005 6,891,755'Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or programming one or more sectors'2005 6,871,258'METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE, AND AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE'2005 6,829,168'Power supply circuit structure for a row decoder of a multilevel non-volatile memory device'2004 6,728,141'Method and circuit for timing dynamic reading of a memory cell with control of the integration time'2004 6,724,658'Method and circuit for generating reference voltages for reading a multilevel memory cell'2004 6,646,913'Method for storing and reading data in a multilevel nonvolatile memory'2003 6,643,179'Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell'2003 6,639,833'Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics'2003 6,587,914'Non-volatile memory capable of autonomously executing a program'2003 6,532,171'Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory units'2003 6,515,911'Circuit structure for providing a hierarchical decoding in semiconductor memory devices'2003 6,493,260'Nonvolatile memory device, having parts with different access time, reliability, and capacity'2002 6,456,530'Nonvolatile memory device with hierarchical sector decoding'2002 6,456,527'Nonvolatile multilevel memory and reading method thereof'2002 6,433,583'CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching'2002 6,396,168'Programmable logic arrays'2002 6,356,481'Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages'2002 6,351,413'Nonvolatile memory device, in particular a flash-EEPROM'2002 6,327,184'Read circuit for a nonvolatile memory'2001 6,304,490'Memory cell integrated structure with corresponding biasing device'2001 6,301,149'Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory'2001 6,301,152'Non-volatile memory device with row redundancy'2001 6,286,086'Data protection method for a semiconductor memory and corresponding protected memory device'2001 6,266,222'ESD protection network for circuit structures formed in a semiconductor'2001 6,237,104'Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory'2001 6,215,329'Output stage for a memory device and for low voltage applications'2001 6,184,741'Bidirectional charge pump generating either a positive or negative voltage'2001 6,181,602'Device and method for reading nonvolatile memory cells'2001 6,169,423'Method and circuit for regulating the length of an ATD pulse signal'2001 6,157,225'Driving circuit with three output levels, one output level being a boosted level'2000 6,151,251'Memory cell integrated structure with corresponding biasing device'2000 6,150,844'High voltage tolerance output stage'2000 6,144,589'Boosting circuit, particularly for a memory device'2000 6,128,225'Method and circuit for reading low-supply-voltage nonvolatile memory cells'2000 6,122,200'Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub-group of rows of a sector'2000 6,111,809'Line decoder for a low supply voltage memory device'2000 6,094,073'Line decoder for memory devices'2000 6,075,750'Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory'2000 6,069,837'Row decoder circuit for an electronic memory device, particularly for low voltage applications'2000 6,060,753'Low noise output buffer for semiconductor electronic circuits'2000 6,018,255'Line decoder for memory devices'2000 5,982,666'Sense amplifier circuit for semiconductor memory devices'1999 5,949,713'Nonvolatile memory device having sectors of selectable size and number'1999 5,946,238'Single-cell reference signal generating circuit for reading nonvolatile memory'1999 5,923,076'Integrated device with pads'1999 5,903,498'Low-supply-voltage nonvolatile memory device with voltage boosting'1999 5,886,925'Read circuit and method for nonvolatile memory cells with an equalizing structure'1999 5,805,500'Circuit and method for generating a read reference signal for nonvolatile memory cells'1998 5,793,676'Nonvolatile memory device having sectors of selectable size and number'1998 5,778,012'Memory device with improved yield and reliability'1998 5,748,528'EEPROM memory device with simultaneous read and write sector capabilities'1998 5,729,492'Sense amplifier having capacitively coupled input for offset compensation'1998 5,717,636'EEPROM memory with contactless memory cells'1998 5,682,349'Failure tolerant memory device, in particular of the flash EEPROM type'1997 5,633,822'Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors'1997 5,587,946'Method of reading, erasing and programming a nonvolatile flash-EEPROM memory arrray using source line switching transistors'1996 5,541,880'Reference signal generating method and circuit for differential evaluation of the content of nonvolatile memory cells'1996 5,535,157'Monolithically integrated storage device'1996 5,508,956'Nonvolatile flash-EEPROM memory array with source control transistors'1996 4,949,307'Circuit for sensing the state of matrix cells in MOS EPROM memories including an offset current generator'1990 4,874,965'Circuital device for the power-on reset of digital integrated circuits in MOS technology'1989 4,800,297'Source bias generator for natural transistors in MOS digital integrated circuits'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–2021Based in Bergamo, IT· patent location history

1990–2001Patents assigned to SGS THOMSON MICROELECTRONICS (13)· patent assignee history

1996–2021Patents assigned to ST MICROELECTRONICS SRL (66)· patent assignee history

2009–2015Patents assigned to CAMPARDO GIOVANNI (11)· patent assignee history

2009–2015Patents assigned to VANALLI GIAN PIETRO (4)· patent assignee history

2013–2018Patents assigned to MICRON TECHNOLOGY INC (11)· patent assignee history

2015Based in Cernusco Lombardone, IT· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ST MICROELECTRONICS SRL	66	1996–2021
SGS THOMSON MICROELECTRONICS	13	1990–2001
CAMPARDO GIOVANNIself	11	2009–2015
MICRON TECHNOLOGY INC	11	2013–2018
VANALLI GIAN PIETRO	4	2009–2015

Locations

Location	Patents	Span
Bergamo, IT	98	1989–2021
Cernusco Lombardone, IT	1	2015