Method and apparatus for acknowledgement-based handshake mechanism for interactively training links

The present disclosure relates generally to data interfaces between agents, and more specifically to point-to-point data interfaces requiring initialization before general operations of data transfer between the agents.

Microprocessor systems have until recently been interconnected via multi-point drop data buses. The processors, memory controllers, input-output controllers (which may generally be termed “agents”) would be able to exchange data over a common data bus structure. However, as data transmission rates become higher, limitations in the multi-point drop data buses are becoming a problem. The electrical loadings and reflections in a multi-point drop data bus system may limit the data transmission speed. In order to address these and other issues, newer systems are examining individual, dedicated point-to-point data interfaces between the agents of a system.

There will still exist variances among agents attempting to exchange data via the point-to-point interfaces. Source impedances, path impedances, and termination impedances may all vary due to process variations and other influences. Data skew among the various parallel data lines, and between the clock and data lines, may become more of a problem at higher data rates. For this reason, during an initialization process the two agents at the opposite ends of the point-to-point interface may exchange special data messages to support the initialization process. For example, pre-determined data messages may help initialize a set of deskewing buffers in a parallel interface. It would be possible to simply send a large number of such messages and presume that the two agents would successfully receive and act upon a sufficient number of them. However this may prove to be a time-consuming process. If the process consumes too much time, it may impact system performance if the initialization is needed not just on a relatively-rare system reset event, but also on commonly occurring events such as transitions between normal operating modes and low-power operating modes.

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 is a schematic diagram of a pair of agents connected via an interface including a pair of point-to-point links, according to one embodiment of the present disclosure.

FIG. 2 is a timing diagram showing advancing from one training sequence to the next, according to one embodiment of the present disclosure.

FIG. 3 is a timing diagram showing advancing from one training sequence to the next, according to one embodiment of the present disclosure.

FIG. 4 is a timing diagram showing receiving of training sequences containing acknowledgements at two receivers, according to one embodiment of the present disclosure.

FIG. 5 is a flowchart showing the advancement from one training sequence to the next, according to one embodiment of the present disclosure.

FIG. 6 is a schematic diagram of system including processors supporting an interface including a pair of point-to-point links, according to one embodiment of the present disclosure.

The following description describes techniques for handshaking with acknowledgement to initialize a series of individual data lanes into data links is shown. In the following description, numerous specific details such as logic implementations, software module allocation, signaling techniques, and details of operation are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such specific details. In other instances, control structures, gate level circuits and full software instruction sequences have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, will be able to implement appropriate functionality without undue experimentation. In certain embodiments the invention is disclosed in the form of an interface for connecting together several Itanium® Processor Family (IPF) compatible processors, or for connecting together several Pentium® compatible processors, such as those produced by Intel® Corporation. However, the invention may be practiced for interconnecting other kinds of processors, such as an X-Scale® family compatible processor (but not limited to any family of processor), or for interconnecting other forms of agents, such as memory hubs or input/output device hubs or chipsets. The invention may also be practiced in the interfacing of mixed kinds of processors or other agents. Finally, the invention may be practiced in dedicated point-to-point interfaces, where either the sending and receiving of data occur on a pair of one-directional links, or where the sanding and receiving of data occur on simulataneous bi-directional links.

Referring now to FIG. 1 , a schematic diagram of a pair of agents connected via an interface including a pair of point-to-point links is shown, according to one embodiment of the present disclosure. For the purpose of the present disclosure, an “agent” may be a processor, digital signal processor, memory controller, input/output controller, chipset, or any other functional circuit that connects to another functional circuit via the interface under consideration. Agent A 100 may be connected to a link 1 140 for transmitting data to agent B 150 and a second link 2 190 for receiving data sent by agent B 150 . Link 1 140 and link 2 190 may be said to form an interface between agent A 100 and agent B 150 .

Agent A 100 may have series of lane transmitters T 1 102 through TN 110 and a clock transmitter TCLK 112 for sending data across link 1 140 . In other embodiments, the external clock transmitter may be omitted and the lane transmitters may send self-clocked data. Agent B 150 may have a series of lane receivers R 1 152 through RN 160 and a clock receiver RCLK 162 to receive the data and clock sent by agent A 100 . Similarly, Agent B 150 may have series of lane transmitters T 1 170 through TN 1178 and a clock transmitter TCLK 180 for sending data across link 2 190 . In other embodiments, the external clock transmitter may be omitted and the lane transmitters may send self-clocked data. Agent A 100 may have a series of lane receivers R 1 120 through RN 128 and a clock receiver RCLK 130 to receive the data and clock sent by agent B 150 .

The link 1 140 and link 2 190 are shown as including interconnecting lanes for physical transport between agents A 100 and B 150 . The lanes in various embodiments may be unbalanced or balanced, differentially-driven. The number of lanes N may be any number. In some embodiments, when soft errors or hard errors in one or more lane are detected, those lanes may be ignored and the link may be configured for operation as a parallel interface with fewer than N lanes.

The signal path lengths and impedances of lanes 132 , 134 , 136 , up to 142 may have significant differences, which may cause differing signal propagation times. This may cause unacceptable skews between lanes. For this reason, an initialization process may be undertaken upon power-on or other system reset activity. The initialization process may train the individual receivers R 1 152 through RN 160 to compensate for skew and other anomalies to permit efficient operation of link 1 140 as a parallel data interface. Similarly the initialization process may train the individual receivers R 1 120 through RN 128 to compensate for skew and other anomalies to permit efficient operation of link 2 190 as a parallel data interface.

In one embodiment, a sequence of numbered messages, called “training sequences”, may be sent over the individual lanes ( 132 through 142 ) temporarily acting during the initialization process as N individual serial interfaces clocked by TCLK 112 . The use of the lanes as individual serial interfaces avoids the skew and other anomalies initially present when using link 1 140 and link 2 190 as parallel interfaces. There may be a first type of training sequence, a second type of training sequence, up to a final type of training sequence. Each of these numbered training sequences may pass parameter data for efficiently setting up the link 1 140 . An equivalent series of training sequences may be sent on link 2 190 . The outcome of the passing of training sequences back and forth across link 1 140 and link 2 190 may be to configure operational parallel interfaces using the lanes of link 1 140 and link 2 190 . For example, the first training sequence may exhibit a known data pattern from which intra-lane skew timing may be determined. A second training sequence may pass parametric data about this timing and also about soft and hard data errors detected in the lanes.

Referring now to FIG. 2 , a timing diagram of advancing from one training sequence to the next is shown, according to one embodiment of the present disclosure. It would be possible to send each of the various training sequences for a pre-determined period of time. This would presume that the links would be trained within the collective time period. However, it has been determined that merely using such a timer-based training method would be difficult to validate and also to debug. Therefore, in one embodiment, a fixed time per training sequence has been replaced by a handshaking method that includes acknowledgements.

The FIG. 2 embodiment shows a representative lane from transmitter Tx of agent A sending to receiver Rx of agent B, and corresponding lane in the reverse direction from transmitter Tx of agent B sending to receiver Rx of agent A. Each of the transmitters Tj of agents A and B may send the training sequences in serial form during the initialization process as described above in connection with FIG. 1 . Generally what may be received at a given Rx of agent B is what was transmitted at the corresponding Tx of agent A, allowing for a time of flight delay and any errors. FIG. 2 shows events with respect to the two time bases, time base A and time base B, which may be considered with respect to the clocks transmitted by agents A and B, respectively.

FIG. 2 presumes that both agent A and agent B have previously agreed to commence sending the second training sequence message TS 2 . At time A 1 , Tx at agent A (Tx @ A) begins transmitting the second training sequence message TS 2 . It repeats transmitting TS 2 as indicated by TS 2 A_ 1 , TS 2 A_ 2 , TS 2 A_ 3 , and so on. These training sequences are received by Rx @ B a short while later. At time B 1 , Tx @ B begins its transmission of the second training sequence message TS 2 .

In one embodiment, each agent agrees to begin sending its training sequences, modified to include an acknowledgement, after it correctly receives from the other agent two consecutive current training sequences. In other embodiments, the number of received current training sequences may be more or fewer than 2, and they need not be received consecutively. The selection of 2 consecutive received training sequences as a criteria may help reduce circuit complexity, as only one training sequence may need to be stored in order to compare with an incoming training sequence. The form of the acknowledgement may be a modification of a data pattern, a flag being set somewhere in the training sequence, or any other means of indicating an acknowledgment.

In keeping with this agreement, both agent A and agent B begin to determine whether they have correctly received two consecutive current training sequences from the other agent as soon as they begin transmitting the current training sequence themselves. At time B 1 , agent B begins transmitting at Tx @ B the current training sequence TS 2 , and examines the receipt of training sequence TS 2 at Rx @ B. As agent A has been sending training sequences TS 2 from time A 1 , at time B 2 agent B will have successfully received TS 2 A_ 3 and TS 2 A_ 4 . Therefore agent B has successfully received two of the current training sequences, and may then begin adding an acknowledgment indicator to subsequent transmissions of TS 2 , starting with TS 2 B_ 3 . In one embodiment, agent B sends at least 4 of the TS 2 messages including an acknowledgement. In other embodiments, few than 4 or more than 4 could be sent.

Because agent B began transmitting at a later time B 1 , agent A does not begin receiving training sequence TS 2 until time A 2 . The Rx @ A successfully receives TS 2 B_ 1 , but receives with an error TS 2 B_ 2 . Only when Rx @ A receives TS 2 B_ 3 and TS 2 B_ 4 , at time A 5 , does it receive 2 consecutive TS 2 messages. Note that these TS 2 messages do contain the acknowledgement, but this is permitted. (The second agent to correctly receive the 2 consecutive training sequences may generally be receiving one with an acknowledgement.) Since agent A has received 2 consecutive training sequences at time A 5 , Tx @ A may then transmit, at time A 6 , the TS 2 messages including an acknowledgement, starting with TS 2 A_ 9 .

Therefore at time A 6 both agent A and agent B are currently transmitting TS 2 messages including an acknowledgement. In one embodiment, each agent agrees to begin sending the next in the sequence of training sequences after (1) each agent has begun transmitting the current training sequence including an acknowledgement, and has transmitted at least 4 of these messages and (2) after beginning such transmissions, each agent correctly receives from the other agent two consecutive current training sequences, including an acknowledgement. In other embodiments, the number of received current training sequences including acknowledgement may be more or fewer than 2, and they need not be received consecutively. Additionally, in other embodiments the number of transmitted messages may be more or fewer than 4.

At time B 4 , agent B has transmitted at least 4 of TS 2 including an acknowledgement (TS 2 B_ 3 through TS 2 B_ 7 ) and has also subsequently correctly received two consecutive TS 2 messages including acknowledgement from agent A (TS 2 A_ 9 and TS 2 A_ 10 ). Therefore, agent B may then begin transmitting the next training sequence after TS 2 , namely TS 3 , at time B 4 . The first of these TS 3 messages is transmitted from Tx @ B at time B 4 (TS 3 B_ 1 ).

Similarly, at time A 7 , agent A has transmitted at least 4 of TS 2 including an acknowledgement (TS 2 A_ 9 through TS 2 A_ 12 ) and has also (in this present example) subsequently correctly received two consecutive TS 2 messages including acknowledgement from agent B (TS 2 B_ 6 and TS 2 A_ 7 ). Therefore, agent A may then begin transmitting the next training sequence after TS 2 , namely TS 3 , at time A 7 . The first of these TS 3 messages is transmitted from Tx @ A at time A 7 (TS 3 A_ 1 ). (It is noteworthy that the transmission of at least 4 of TS 2 including an acknowledgement and correctly receiving two consecutive TS 2 messages including acknowledgement from agent B may in fact occur in any order.)

The FIG. 2 example showed handshaking with acknowledgment for a representative pair of lanes Tx @ A-Rx @ B and Tx @ B-Rx @ A between agent A and agent B. It is intended that the transmissions of training sequences may take place across all of the lanes. In this case, if there is an error in reception on one lane (e.g. TS 2 B_ 2 ), then that lane may disregard the corresponding training sequence for the purpose of changing from transmitting a training sequence to transmitting the training sequence with acknowledgement, or for the purpose of changing from transmitting one training sequence to transmitting a subsequent training sequence. In some embodiments, the lanes encountering many soft errors, or a hard error, may be removed from the handshaking process.

Referring now to FIG. 3 , a timing diagram of advancing from one training sequence to the next is shown, according to one embodiment of the present disclosure. The same rules for agreement for advancing from transmitting a training sequence to transmitting the training sequence with acknowledgement, or for the purpose of changing from transmitting one training sequence to transmitting a subsequent training sequence discussed above in connection with FIG. 2 may be applied in FIG. 3 as well.

At event E 1 , a first training sequence TS 1 B_ 1 may be sent from Tx @ B and received at Rx @ A. At event E 2 , a corresponding first training sequence TS 1 A_ 2 may be sent from Tx @ A and received at Rx @ B. At event E 3 , Rx @ B may receive with error a second TS 1 from Tx @ A, and therefore the Rx @ B may discard any history (e.g. TS 1 A_ 2 and TS 1 A_ 3 ).

At event E 4 , the Rx @ A has correctly received 2 consecutive training sequences (TS 1 B_ 1 and TS 1 B_ 2 ), so starting with TS 1 A_ 4 the Tx @ A may begin transmitting at least 4 training sequences including acknowledgement. Then from event E 5 to event E 6 , Rx @ B may correctly receive two consecutive training sequences (in this case including acknowledgement) TS 1 A_ 4 and TS 1 A_ 5 . Therefore, at event E 7 , Tx @ B may begin transmitting at least 4 training sequences including acknowledgement. In other embodiments, the number of training sequences required to be received or transmitted may be different.

At event E 8 , Rx @ A has correctly received two consecutive TS 1 including acknowledgement subsequent to Tx @ A beginning to transmit TS 1 including acknowledgement. Therefore Tx @ A may begin sending the next in the sequence of training sequences, TS 2 , beginning at TS 2 A_ 1 . At event E 9 , as agent A has advanced to transmitting TS 2 , Rx @ A may begin expecting to receive TS 2 messages, but will simply ignore older TS 1 messages (e.g. TS 1 B_ 10 ) as no longer relevant. Similarly, at event E 10 , agent B has advanced to transmitting TS 2 so Rx @ B may begin expecting to receive TS 2 message at that time. Here Rx @ B will simply ignore previously-received TS 2 messages (e.g. TS 2 A_ 1 and TS 2 A_ 2 ) because they arrived before Rx @ B was ready for them.

Referring now to FIG. 4 , a timing diagram of receiving of training sequences containing acknowledgements at two receivers is shown, according to one embodiment of the present disclosure. Here the two receivers are Rx @ A and Ry @ A of agent A. At time A 1 , agent A begins looking for 2 consecutive training sequences with acknowledgement. Rx @ A and Rx @ B both successfully receive TS 1 _ 4 . But then Rx @ A successfully receives TS 1 _ 5 , while Ry @ A receives TS 1 _ 5 with an error. Although at time A 3 Rx @ A has received 2 consecutive training sequences with acknowledgement, Ry @ A has not. Therefore agent A does not proceed to transmitting TS 2 messages, but waits until Ry @ A has received 2 consecutive training sequences with acknowledgement. Only at time A 5 , after Ry @ A has successfully received TS 1 _ 6 and TS 1 _ 7 , may agent A proceed to transmitting TS 2 messages. In other embodiments, the number of training sequences to receive may be fewer than or greater than 2.

Referring now to FIG. 5 , a flowchart of the advancement from one training sequence to the next is shown, according to one embodiment of the present disclosure. The FIG. 5 flowchart shows the actions taken by one specific agent, and references to “send” or “receive” are with respect to that agent. At block 510 the number M of the training sequence is initialized at 1. (A time count for supporting a timeout may also be initialized to 0 at this time.) Then in block 514 the training sequence message TSM is transmitted. In decision block 518 , it is determined whether 2 consecutive TSM messages have been correctly received. In other embodiments, more than 2 or fewer than 2 messages may be examined. Here the TSM messages may or may not include an acknowledgment. If 2 consecutive TSM messages have not been correctly received, then the process exits decision block 518 via the NO path, and in block 538 another TSM message may be sent. Then in decision block 542 it may be determined whether the current time count exceeds a limit. If not, then the process exits via the NO path and re-enters decision block 518 . If so, then the process exits via the YES path and enters block 552 .

When in decision block 518 it is determined that 2 consecutive TSM messages have been correctly received, then the process exits via the YES path and in block 522 TSM messages with acknowledgment may begin being sent. In one embodiment, 4 of these TSM messages with acknowledgement may be eventually sent. In other embodiments, fewer than 4 or more than 4 TSM messages with acknowledgement may be eventually sent. Then in decision block 526 , it may be determined whether 2 consecutive TSM messages with acknowledgement have been correctly received and whether 4 TSM messages with acknowledgement have been sent. (Note that if any of the TSM messages sent in blocks 514 or 538 were TSM messages with acknowledgement, these should be included in the count determined in decision block 526 .) In other embodiments, more than 2 or fewer than 2 received TSM messages with acknowledgement may be examined. If 2 consecutive TSM messages with acknowledgement have not been correctly received, or 4 TSM messages with acknowledgement have not been sent, then the process exits decision block 526 via the NO path, and in block 546 another TSM message including acknowledgement may be sent. Then in decision block 550 it may be determined whether the current time count exceeds a limit. If not, then the process exits via the NO path and re-enters decision block 526 . If so, then the process exits via the YES path and enters block 552 .

When either decision block 542 or decision block 550 exits via the YES path, the fact that the current time count exceeds a limit indicates a problem with one or more of the lanes. Therefore in block 552 some of the lanes, including lanes where the time limit was exceeded, may be removed from further consideration during the process. In one embodiment, standard subsets of the lanes may be removed and the interface may proceed with the remaining subsets of the lanes. For example, the subsets may be either one quarter or one half of all of the lanes, and the interface may proceed with either the remaining three quarters or one half, respectively, of the lanes. After block 552 , the process then enters block 530 .

When in decision block 526 it is determined that 2 consecutive TSM messages with acknowledgment have been correctly received, and that 4 TSM messages with acknowledgement have been sent, then the process exits via the YES path and in block 530 the training sequence message number M may be incremented. This may cause future sending of training sequences to advance from one training sequence to the next. In block 534 the time count may be reset and the process may repeat at block 514 . The TSM now sent at block 514 will be advanced in sequence number.

Referring now to FIG. 6 , a schematic diagram of system including a processors supporting an interface including a pair of point-to-point links is shown, according to one embodiment of the present disclosure. The FIG. 6 system generally shows a system where processors, memory, and input/output devices are interconnected by a number of point-to-point interfaces.

The FIG. 6 system may include several processors, of which only two, processors 70 , 80 are shown for clarity. Processors 70 , 80 may each include a local memory controller hub (MCH) 72 , 82 to connect with memory 2 , 4 . Processors 70 , 80 may exchange data via a point-to-point interface 50 using point-to-point interface circuits 78 , 88 . Processors 70 , 80 may each exchange data with a chipset 90 via individual point-to-point interfaces 52 , 54 using point to point interface circuits 76 , 94 , 86 , 98 . In one embodiment, point-to-point interfaces 50 , 52 , 54 may be interfaces as described in FIGS. 1 through 5 of the present disclosure. Chipset 90 may also exchange data with a high-performance graphics circuit 38 via a high-performance graphics interface 92 .

In the FIG. 6 system, chipset 90 may exchange data with a bus 16 via a bus interface 96 . In the system, there may be various input/output I/O devices 14 on the bus 16 , including in some embodiments low performance graphics controllers, video controllers, and networking controllers. Another bus bridge 18 may in some embodiments be used to permit data exchanges between bus 16 and bus 20 . Bus 20 may in some embodiments be a small computer system interface (SCSI) bus, an integrated drive electronics (IDE) bus, or a universal serial bus (USB) bus. Additional I/O devices may be connected with bus 20 . These may include keyboard and cursor control devices 22 , including mice, audio I/O 24 , communications devices 26 , including modems and network interfaces, and data storage devices 28 . Software code 30 may be stored on data storage device 28 . In some embodiments, data storage device 28 may be a fixed magnetic disk, a floppy disk drive, an optical disk drive, a magneto-optical disk drive, a magnetic tape, or non-volatile memory including flash memory.

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.