Inventor
Tim Frodsham
Inventor
Portland, OR, US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing31%
H04LTransmission of digital information, e.g. telegraphic communication27%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use18%
G01RMeasuring electric variables10%
H03KPulse technique6%
H04WWireless communication networks4%
H04JMultiplex communication2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
PatentTitleYear
9,794,349'Dynamically modulating link width'20178,914,541'Dynamically modulating link width'20148,250,416'Redundant acknowledgment in loopback entry'20128,205,111'Communicating via an in-die interconnect'20128,204,067'Technique for lane virtualization'20128,046,488'Dynamically modulating link width'20117,965,741'Method, apparatus, and system for idle state definition for power management'20117,957,428'Methods and apparatuses to effect a variable-width link'20117,844,767'Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link'20107,804,890'Method and system for response determinism by synchronization'20107,747,888'Technique to create link determinism'20107,746,795'Method, system, and apparatus for loopback parameter exchange'20107,711,878'Method and apparatus for acknowledgement-based handshake mechanism for interactively training links'20107,681,093'Redundant acknowledgment in loopback entry'20107,610,500'Link power saving state'20097,586,951'Method, apparatus, and system for idle state definition for power management'20097,568,118'Deterministic operation of an input/output interface'20097,386,773'Method and system for testing distributed logic circuitry'20087,366,964'Method, system, and apparatus for loopback entry and exit'20087,362,739'Methods and apparatuses for detecting clock failure and establishing an alternate clock lane'20087,328,359'Technique to create link determinism'20087,313,712'Link power saving state'20077,219,220'Methods and apparatuses for resetting the physical layers of two agents interconnected through a link-based interconnection'20077,209,907'Method and apparatus for periodically retraining a serial links interface'20077,203,872'Cache based physical layer self test'20076,704,892'Automated clock alignment for testing processors in a bypass mode'20046,594,769'Reference voltage distribution for multiload I/O systems'20036,453,422'Reference voltage distribution for multiload i/o systems'20026,320,441'I/O tranceiver having a pulsed latch receiver circuit'20016,195,395'Multi-agent pseudo-differential signaling scheme'20015,721,875'I/O transceiver having a pulsed latch receiver circuit'19985,483,188'Gil edge rate control circuit'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2017Patents assigned to INTEL CORP (32)· patent assignee history
1996–2017Based in Portland, OR, US· patent location history
2012–2014Patents assigned to FRODSHAM TIM (4)· patent assignee history
2012–2014Patents assigned to DABRAL SANJAY (3)· patent assignee history
2012–2014Patents assigned to CHERUKURI NAVEEN (2)· patent assignee history
2012–2014Patents assigned to SCHOENBORN THEODORE Z (2)· patent assignee history
2012Based in Beaverton, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 32 | 1996–2017 |
| FRODSHAM TIMself | 4 | 2012–2014 |
| DABRAL SANJAY | 3 | 2012–2014 |
| CHERUKURI NAVEEN | 2 | 2012–2014 |
| SCHOENBORN THEODORE Z | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 31 | 1996–2017 |
| Beaverton, OR, US | 1 | 2012 |