Inventor

Theodore Z. Schoenborn

Inventor

Portland, OR, US

Overview

70→

Patents

2002–2020

Patent span

Physics

Primary field (CPC G)

Patents· 70 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing32%

H04LTransmission of digital information, e.g. telegraphic communication20%

G11CStatic stores17%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use12%

G01RMeasuring electric variables8%

H04WWireless communication networks5%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%

H04BTransmission2%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%

H03KPulse technique1%

PatentTitleYear

10,712,809Link power savings with state retention2020 10,516,439Interference testing2019 10,446,222Memory subsystem I/O performance based on in-system empirical testing2019 10,347,319Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system2019 10,210,925Row hammer refresh command2019 10,175,744Link power savings with state retention2019 9,922,725'Integrated circuit defect detection and repair'2018 9,865,326'Row hammer refresh command'2018 9,794,349'Dynamically modulating link width'2017 9,747,971'Row hammer refresh command'2017 9,722,663'Interference testing'2017 9,588,575'Link power savings with state retention'2017 9,575,922'Apparatus, system, and method for improving equalization with a software equalization algorithm'2017 9,564,245'Integrated circuit defect detection and repair'2017 9,548,137'Integrated circuit defect detection and repair'2017 9,536,626'Memory subsystem I/O performance based on in-system empirical testing'2017 9,373,365'Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system'2016 9,330,734'Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system'2016 9,236,110'Row hammer refresh command'2016 9,196,384'Memory subsystem performance based on in-system weak bit detection'2015 9,117,544'Row hammer refresh command'2015 9,076,499'Refresh rate performance based on in-system weak bit detection'2015 9,009,540'Memory subsystem command bus stress testing'2015 9,009,531'Memory subsystem data bus stress testing'2015 9,003,246'Functional memory array testing with a transaction-level test engine'2015 8,996,934'Transaction-level testing of memory I/O and memory device'2015 8,938,573'Row hammer condition monitoring'2015 8,914,541'Dynamically modulating link width'2014 8,885,735'Methods and apparatus for signaling on a differential link'2014 8,868,992'Robust memory link testing using memory controller'2014 8,831,666'Link power savings with state retention'2014 8,819,474'Active training of memory command timing'2014 8,761,031'Physical layer loopback'2014 8,750,138'Physical layer loopback'2014 8,204,067'Technique for lane virtualization'2012 8,046,488'Dynamically modulating link width'2011 7,965,741'Method, apparatus, and system for idle state definition for power management'2011 7,957,428'Methods and apparatuses to effect a variable-width link'2011 7,936,684'Physical layer loopback'2011 7,844,767'Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link'2010 7,804,890'Method and system for response determinism by synchronization'2010 7,746,795'Method, system, and apparatus for loopback parameter exchange'2010 7,747,888'Technique to create link determinism'2010 7,711,878'Method and apparatus for acknowledgement-based handshake mechanism for interactively training links'2010 7,610,500'Link power saving state'2009 7,586,951'Method, apparatus, and system for idle state definition for power management'2009 7,464,307'High performance serial bus testing methodology'2008 7,444,558'Programmable measurement mode for a serial point to point link'2008 7,427,872'Asynchronous coupling and decoupling of chips'2008 7,366,964'Method, system, and apparatus for loopback entry and exit'2008 7,362,739'Methods and apparatuses for detecting clock failure and establishing an alternate clock lane'2008 7,328,359'Technique to create link determinism'2008 7,324,458'Physical layer loopback'2008 7,313,712'Link power saving state'2007 7,219,220'Methods and apparatuses for resetting the physical layers of two agents interconnected through a link-based interconnection'2007 7,209,907'Method and apparatus for periodically retraining a serial links interface'2007 7,206,981'Compliance testing through test equipment'2007 7,203,872'Cache based physical layer self test'2007 7,161,388'Remote receiver detection'2007 7,155,352'Using feedback to select transmitting voltage'2006 6,968,474'Generating and recovering clock signals based on differential scheme'2005 6,909,174'Reference plane of integrated circuit packages'2005 6,906,549'Asynchronous coupling and decoupling of chips'2005 6,825,693'Remote receiver detection'2004 6,628,528'Current sharing in memory packages'2003 6,594,769'Reference voltage distribution for multiload I/O systems'2003 6,580,619'Multilayer reference plane in package devices'2003 6,532,162'Reference plane of integrated circuit packages'2003 6,510,526'Differential clocking for digital platforms'2003 6,453,422'Reference voltage distribution for multiload i/o systems'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2020Patents assigned to INTEL CORP (69)· patent assignee history

2002–2020Based in Portland, OR, US· patent location history

2012–2017Patents assigned to SCHOENBORN THEODORE Z (12)· patent assignee history

2012–2014Patents assigned to CHERUKURI NAVEEN (3)· patent assignee history

2014–2017Patents assigned to MOZAK CHRISTOPHER P (7)· patent assignee history

2014–2016Patents assigned to GREENFIELD ZVIKA (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	69	2002–2020
SCHOENBORN THEODORE Zself	12	2012–2017
MOZAK CHRISTOPHER P	7	2014–2017
GREENFIELD ZVIKA	5	2014–2016
CHERUKURI NAVEEN	3	2012–2014

Locations

Location	Patents	Span
Portland, OR, US	70	2002–2020