Power-on detect circuit for use with multiple voltage domains

Disclosed embodiments of the present invention relate to the field of integrated circuits (IC), and more particularly to providing signal integrity across multiple voltage domains of the IC.

Many types of modern electronic devices may incorporate multiple voltage domains. For example, a modern microprocessor chip may include core logic that operates in one voltage domain while interacting with input/output (I/O) circuitry operating in another.

During the initial power up sequencing the different voltage domains may reach a nominal power level at different times. If logic in a first voltage domain is required to function only when the voltages of both domains are at their nominal levels, the logic in the first voltage domain may need an indication that the signal(s) outputted by the second domain logic is(are) valid. Prior art methods have attempted to accomplish this by sending a signal through a level shifter from the second voltage domain to the first voltage domain. Unfortunately, the level shifter output may be an undefined signal if the voltage in the second voltage domain has not reached the nominal voltage level. The propagation of this undefined signal into the first voltage domain could falsely indicate that the signal(s) outputted from the second voltage domain is(are) valid.

Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which the like references indicate similar elements and in which:

FIGS. 1 a– 1 d illustrate a power-on detect circuit for use to assure proper voltage levels of multiple voltage supplies for multiple voltage domains, in accordance with an embodiment of the present invention;

FIG. 2 illustrates an example of a power-on detect circuit described in FIGS. 1 a – 1 d, in accordance with an embodiment of the present invention;

FIGS. 3 a – 3 b illustrate various voltage levels and voltage goodness signals as a function of time, for an example sequential ramp up of two voltage supplies;

FIG. 4 illustrates an integrated circuit with multiple voltage supplies, multiple operational circuits operating in multiple voltage domains, a level shifter circuit, and a power-on detect circuit, in accordance with an embodiment of the present invention;

FIG. 5 represents a truth table corresponding to the level shifter circuit diagram in FIG. 4 , in accordance with one embodiment of the present invention; and

FIG. 6 illustrates a system using a power-on detect circuit, in accordance with one embodiment of the present invention.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration of specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the embodiments of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of the embodiments of the present invention is defined by the appended claims and their equivalents.

FIGS. 1 a – 1 d illustrate a power-on detect (POD) circuit 100 that may be used to assure voltage levels of multiple voltages for multiple voltage domains, in accordance with one embodiment of this invention. In particular, for this embodiment, POD circuit 100 may be used to assure the voltage levels of first (V 1 ) and second (V 2 ) voltage supplies for two voltage domains.

For the embodiment, as illustrated in FIG. 1 a, POD circuit 100 includes voltage dividers 102 a – 102 b, V 1 goodness detectors 104 a and 106 b and V 2 goodness detectors 106 a and 104 b coupled to each other as shown. The goodness detectors 104 a, 104 b, 106 a, and 106 b may also be referred to as analyzers. Voltage divider 102 a, V 1 goodness detector 104 a and V 2 goodness detector 106 a serve the V 1 domain, while voltage divider 102 b, V 2 goodness detector 104 b and V 1 goodness detector 106 b serve the V 2 domain. Accordingly, V 1 or V 2 domain may also be referred to as the “client” domain of the circuit elements that serve them.

Each of the voltage dividers 102 a / 102 b is employed to generate two proxy signals V 1 L and V 1 H (or V 2 L and V 2 H) to reflect the voltage level of voltage V 1 /V 2 in different manners. For the embodiment V 1 L/V 2 L rises rapidly as V 1 /V 2 rises and then plateaus out, whereas, V 1 H/V 2 H rises more slowly initially as V 1 /V 2 rises, but then very rapidly thereafter (see also FIG. 3 ). Each of proxy signal pairs, V 1 L and V 1 H or V 2 L and V 2 H, is designed, such that the two proxy signals V 1 L/V 2 L and V 1 H/V 2 H equal each other when the voltage of interest V 1 /V 2 reaches a threshold level of “goodness.” The threshold level that defines goodness is application dependent, and may vary from application to application.

Each of V 1 /V 2 voltage goodness detectors 104 a / 104 b is employed to indicate whether the voltage level of the voltage of its client domain V 1 /V 2 has reached the corresponding desired threshold level. In other words, V 1 voltage goodness detector 104 a is employed to indicate for the V 1 voltage domain, whether the voltage level of the V 1 voltage is good, and V 2 voltage goodness detector 104 b is employed to indicate for the V 2 voltage domain, whether the voltage level of the V 2 voltage is good. Accordingly, V 1 /V 2 voltage goodness detector 104 a / 104 b may also be referred to as local voltage goodness detector. As illustrated, each of V 1 /V 2 voltage goodness detectors 104 a and 104 b generates its indicator based on the corresponding proxy signals, V 1 L and V 1 H or V 2 L and V 2 H.

Each of V 2 /V 1 voltage goodness detectors 106 a and 106 b, on the other hand, is employed to indicate whether the voltage level of the voltage of the other voltage domain V 1 /V 2 has reached the corresponding desired threshold level. In other words, V 2 voltage goodness detector 106 a is employed to indicate for the V 1 voltage domain, whether the voltage level of the V 2 voltage is good, and V 1 voltage goodness detector 106 b is employed to indicate for the V 2 voltage domain, whether the voltage level of the V 1 voltage is good. Accordingly, V 2 /V 1 voltage goodness detectors 106 a and 106 b may also be referred to as neighbor voltage goodness detector. As illustrated, for the embodiment, each of V 2 /V 1 voltage goodness detectors 106 a and 106 b generates its indicator based on two complementary proxy signals of the two domains (e.g. V 2 H and V 1 L for indicating voltage level of V 2 for the V 1 domain, and V 1 H and V 2 L for indicating voltage level of V 1 for the V 2 domain), and the voltage goodness signal of the client domain V 1 good/V 2 good.

FIG. 1 b illustrates a voltage divider in further detail, in accordance with one embodiment. As illustrated, for the embodiment, each of voltage dividers 102 a and 102 b includes two branches. The first branch of the voltage divider 102 a / 102 b may include a linear device 112 a coupled to Vi (where Vi may be V 1 or V 2 ). In one embodiment, the linear device may be any type of resistive device (e.g., a resistor). The linear device 112 a may load a saturating device 114 a, which may be coupled to a ground. Examples of the saturating device may include, but are not limited to, a diode and a diode-connected transistor. It should be noted that although in this embodiment ground is used as the base voltage, it is not essential and may not be so in other embodiments. As illustrated, ViL (e.g., V 1 L or V 2 L) is taken at node 118 which is disposed in between the two devices 112 a and 114 a. The second branch of the voltage divider may be similar to the first, except that the saturating device 114 b and the linear device 112 b may have an opposite orientation. ViH (e.g. V 1 H or V 2 H) is taken at node 130 disposed in between devices 114 b and 112 b.

With the two branches of the voltage dividers having the linear and the saturation devices in opposite positions, as the voltage supply V 1 /V 2 is ramped from zero to its nominal level, the intermediate voltages V 1 H/V 2 H and V 1 L/V 2 L characterize V 1 /V 2 differently as earlier described. Further, for an embodiment using grounded voltage dividers, the linear and the saturation devices are designed such that V 1 H/V 2 H and V 1 L/V 2 L may be identical at exactly one non-ground voltage, when the voltage supply V 1 /V 2 reaches the threshold level.

FIG. 1 c illustrates the local voltage goodness detector 104 a / 104 b in further detail, in accordance with one embodiment. Substantively, each of the local voltage goodness detectors 104 a and 104 b is a differential logic arrangement for detecting a condition indicating that ViH is approximately greater than ViL (e.g., V 1 H and V 1 L, or V 2 H and V 2 L). In one embodiment, the differential logical arrangement could include a voltage comparator 122 and an inverter 124 , coupled to each other and to terminals manifesting voltages ViL/ViH. The terminals may correspond to nodes 118 and 130 of FIG. 1 b. The terminal manifesting voltage V 1 L/V 2 L, may be coupled to, e.g., the (+) input terminal of the voltage comparator 122 , whereas terminal 130 , manifesting voltage V 1 H/V 2 H may be coupled to, e.g., the (−) input terminal of the voltage comparator 122 . The voltage comparator 122 may be an operational amplifier. Thus, before the condition of V 1 H/V 2 H being greater than V 1 L/V 2 L, the output of comparator 122 is positive, but after the condition of V 1 H/V 2 H being greater than V 1 L/V 2 L, the output of comparator 122 is negative. Thus inverter 124 will output a positive signal indicating V 1 /V 2 is good in the V 1 /V 2 domain (also referred to as the V 1 good or V 2 good signal). In an alternate embodiment, the inputs on the comparator 122 may be switched and the inverter 124 removed without changing the function of the goodness detector.

FIG. 1 d illustrates the neighbor voltage goodness detector 106 a / 106 b in further detail, in accordance with one embodiment. Similar to local voltage goodness detector 104 a / 104 b, neighbor voltage goodness detector 106 a / 106 b, substantively, is also a differential logic arrangement. In one embodiment, the differential logic arrangement may include comparator 222 and inverter 224 coupled to each other as shown. Comparator 222 may also be a differential amplifier. The (+) and (−) terminals of comparator 222 are coupled to two terminals manifesting two complementary proxy signals of two voltage domains (e.g., V 1 L and V 2 H or V 2 L and V 1 H) instead. Furthermore, a logic gate such as an AND gate 226 may be used to gate the output of the inverter 224 with the local voltage good indication (V 1 good or V 2 good) for the client domain. Depending on the power-up sequence of a particular embodiment, the AND gate may not be needed to gate the control signal with the local voltage good signal.

In summary, FIG. 2 illustrates one example of a power-on detect circuit 100 including the elements discussed with reference to FIGS. 1 a – 1 d. This power-on detect circuit 100 may include a pair of voltage dividers 244 , a pair of local voltage goodness detectors 248 , and a pair of neighbor voltage goodness detectors 252 including a pair of logic gates 256 . This power-on detect circuit 100 may be capable of outputting four signals including V 1 good, V 2 good, V 1 V 2 good, and V 2 V 1 good, locally assuring the V 1 and V 2 voltage domains that V 1 and V 2 have reached their respective desired threshold levels, as well as neighborly assuring the V 2 and V 1 voltage domains of the same. In one application, selected ones of these signals may then be used to qualify all signals transmitted across the voltage domains, to be discussed further with reference to FIG. 4 .

As is common in the art, the power-on detect circuit 100 may also be described as a power detect, power-on reset, power enable, and/or voltage detect circuit. Embodiments of the present invention relate to all of the above as they are generally understood in the field.

Although the above embodiment is illustrated depicting two power-supply domains, embodiments of this invention are not limited in use to only two domains.

As illustrated in FIG. 2 , the power-on detect circuit includes semiconductor devices such as saturation and linear devices. Although these semiconductor devices are illustrated schematically as single transistors/resistors, this is done to facilitate the discussion of the circuit characteristics. When implemented or manufactured these may comprise multiple devices, depending, for example, upon the application or the particular integrated circuit chip. For example, as it is well known, some form of digital and/or analog circuit compensation may be included to address the potential variation in circuit parameters known to occur as a result of the fabrication process. Therefore, the simplified circuit diagram in FIG. 2 is provided primarily for purposes of illustration and, as one of ordinary skill in the art will appreciate, when actually implementing a particular power-on detect circuit, more complex circuitry to provide a desired operation, such as operations described herein, may be employed. For example, a plurality of transistors having sizes that are binary weighted may be coupled so that each of the transistors may be switched on and off independently to “tune” the overall collection of binary weighted transistors to achieve a particular impedance or effective transistor width.

Also, certain logical functions schematically represented by a logic component should not be limited to that specific component. For example, the AND gate 226 represents the logical function of producing a certain output once two conditions have been satisfied. However, there are logical components other than an AND gate, which may be combined to produce the same function (e.g., a NAND gate followed by an inverter).

Devices that operate with multiple voltage domains may require a power-up sequence for proper initialization. In one embodiment, for example, an input/output domain may be sequenced to power-up before the core logic domain. However, this is not always the case, and other embodiments may use alternative power-up sequencing procedures. Embodiments of the present invention may be readily adapted to any number of power-up supply sequences with multiple voltage domains.

FIGS. 3 a – 3 b further explain the timing of the signals output from the power-on detect circuit 100 in correlation to a particular power-up sequence, in accordance with one example application. FIG. 3 a may depict a set of waveforms where the two voltages V 1 and V 2 are ramped sequentially. The different characterizations of V 1 and V 2 by the proxy signals V 1 L, V 1 H, V 2 L and V 2 H are as shown. FIG. 3 b depicts the binary signals that may be emitted from the differential logic arrangements to denote the goodness of the local or neighbor voltage. The V 1 good signal may be turned on after V 1 H is greater than V 1 L. Similarly, the V 2 good signal may be turned on after V 2 H is greater than V 2 L. Both of these signals indicate that, in their respective voltage domains, the voltage has reached the desired nominal level.

In this embodiment, the V 1 V 2 good signal may not be turned on until V 2 H becomes greater than V 1 L. This may give an indication in the first voltage domain that the neighbor voltage V 2 has reached the desired nominal level. The V 1 V 2 good signal may also need the V 1 good signal; however, because of the power-up sequence of this embodiment, this signal may have already been generated earlier and therefore V 2 H>V 1 L is the final condition for the V 1 V 2 good signal. The V 2 V 1 good signal may work in the opposite way. That is, the V 1 H signal being greater than the V 2 L happens early in the sequence; however, the V 2 good signal has not been issued yet. Therefore, the V 2 good signal is the final event prior to the V 2 V 1 good signal.

FIG. 4 depicts an integrated circuit incorporated with an implementation of the power-on detect circuit 100 , in accordance with one embodiment. As illustrated, integrated circuit 300 includes an operational circuit 302 designed to operate with voltage V 2 , defining the V 2 voltage domain, and another operational circuit 304 designed to operate with voltage V 1 , defining the V 1 voltage domain. For the embodiment, in addition to operational circuits 302 and 304 and POD 100 , integrated circuit 300 also includes level shift arrangement 306 to facilitate transmission of signals from the V 2 voltage domain to the V 1 voltage domain.

In particular, POD 100 is used to qualify any signal transitioning between the two voltage domains. For the embodiment, level shift arrangement 306 includes level shifter 208 and AND gate 212 coupled to each other and the other elements as shown. In this embodiment, a logic signal, in 2 204 , may be input from the V 2 voltage domain. In 2 204 may enter a level shifter 208 to be shifted from the V 2 voltage domain into the V 1 voltage domain. The output may be gated after the level shifter 208 by a control signal indicating that the V 2 voltage has reached the desired nominal level, e.g. V 1 V 2 good, using AND gate 212 . When the AND gate 212 receives the control signal it may provide a level shifted logic signal, out 1 210 , to operational circuit 304 of the V 1 voltage domain. The arrangement may help to reduce the propagation of an X (unknown signal) by the level shifter 208 for the case where the destination voltage supply (e.g., V 1 ) is valid but the driving supply (e.g., V 2 ) is not. In various embodiments, integrated circuit 300 is a general purpose microprocessor, operational circuit 304 may be the core logic of the microprocessor, while operational circuit 302 may be the I/O section of the microprocessor.

FIG. 5 illustrates a truth table depicting the state of the logical outputs (out 1 ) of FIG. 4 under various conditions, in accordance with one embodiment. If the voltage in the V 1 voltage domain is indeed V 1 and the voltage in the V 2 voltage domain is also indeed V 2 , then by virtue of the power-on detect circuit outputting a V 1 V 2 good signal, output out 1 will be valid accordingly. That is, under these conditions, if in 2 is V 2 , then out 1 will be V 1 . Conversely, if in 2 is 0, then out 1 will also be 0. However, if either voltage (V 1 or V 2 ) is 0, then by virtue of the fact that V 1 V 2 good will also be 0, regardless of what in 2 is, out 1 will be 0. Therefore, the occurrence of an undefined X propagated as out 1 may be reduced.

Referring to FIG. 6 , there is illustrated one of many possible systems in which embodiments of the present invention may be used. As illustrated, system 270 includes integrated circuit 280 , and a number of other components and/or input/output devices. The integrated circuit 280 may be coupled to the other components and the input/output devices by means of a bus 282 . A power-on detect circuit, similar to the earlier discussed embodiments, may be incorporated with integrated circuit 280 to validate signals transferring between different domains of the integrated circuit 280 .

The other components may include memory 284 , a graphics processor 286 , a mass storage device 288 , and the input/output devices may include, e.g., a network interface 290 . Examples of the memory 284 include but are not limited to static random access memory (SRAM) and dynamic random access memory (DRAM). Examples of the mass storage device 288 include but are not limited to a hard disk drive, a compact disk drive (CD), a digital versatile disk drive (DVD), and so forth. Examples of other input/output modules 290 include but are not limited to a keyboard, cursor control devices, a display, a network interface, and so forth. Examples of the bus 282 include but are not limited to a peripheral control interface (PCI) bus, and Industry Standard Architecture (ISA) bus, and so forth. In various embodiments, the system 270 may be a wireless mobile phone, a personal digital assistant, a pocket PC, a tablet PC, a notebook PC, a desktop computer, a set-top box, an audio/video controller, a DVD player, and a server.

Although specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiment shown and described without departing from the scope of the present invention. Those with skill in the art will readily appreciate that the present invention may be implemented in a very wide variety of embodiments. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.