Inventor
Gregory F. Taylor
Inventor
Portland, OR, US
Overview
Patents· 54 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique23%
G06FElectric digital data processing19%
G01RMeasuring electric variables15%
G11CStatic stores8%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses7%
G01KMeasuring temperature4%
H03HImpedance networks, e.g. resonant circuits4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G05FSystems for regulating electric or magnetic variables3%
H01HElectric switches3%
PatentTitleYear
10,247,624Self-calibrated thermal sensors of an integrated circuit die20199,702,769'Self-calibrated thermal sensors of an integrated circuit die'20179,470,586'Self-calibrated thermal sensors of an integrated circuit die'20168,827,550'Thermal sensor using a vibrating MEMS resonator of a chip interconnect layer'20148,331,186'Fuse programming schemes for robust yield'20128,314,725'On-die digital-to-analog conversion testing'20127,889,587'Fuse programming schemes for robust yield'20117,602,663'Fuse cell array with redundancy features'20097,501,845'On-chip frequency degradation compensation'20097,417,459'On-die offset reference circuit block'20087,394,274'On-chip frequency degradation compensation'20087,348,790'AC testing of leakage current in integrated circuits using RC time constant'20087,282,937'On-chip frequency degradation compensation'20077,233,162'Arrangements having IC voltage and thermal resistance designated on a per IC basis'20077,199,624'Phase locked loop system capable of deskewing'20077,112,979'Testing arrangement to distribute integrated circuits'20067,109,737'Arrangements having IC voltage and thermal resistance designated on a per IC basis'20067,049,865'Power-on detect circuit for use with multiple voltage domains'20066,967,496'AC testing of leakage current in integrated circuits using RC time constant'20056,885,231'Variable delay element for use in delay tuning of integrated circuits'20056,874,083'Method and apparatus to ensure proper voltage and frequency configuration signals are defined before applying power to processor'20056,792,489'Multistage configuration and power setting'20046,781,428'Input circuit with switched reference signals'20046,777,970'AC testing of leakage current in integrated circuits using RC time constant'20046,748,549'Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock'20046,727,597'Integrated circuit device having C4 and wire bond connections'20046,717,455'Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation'20046,691,241'Delay tuning to improve timing in multi-load systems'20046,671,847'I/O device testing method and apparatus'20036,628,157'Variable delay element for use in delay tuning of integrated circuits'20036,584,591'Timing control for input/output testability'20036,573,764'Method and apparatus for voltage-mode differential simultaneous bi-directional signaling'20036,552,570'Input circuit with non-delayed time blanking'20036,535,047'Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation'20036,453,421'Processor system with power supply selection mechanism'20026,452,502'Method and apparatus for early detection of reliability degradation of electronic devices'20026,410,990'Integrated circuit device having C4 and wire bond connections'20026,396,309'Clocked sense amplifier flip flop with keepers to prevent floating nodes'20026,236,695'Output buffer with timing feedback'20016,208,169'Internal clock jitter detector'20016,157,206'On-chip termination'20006,124,755'Method and apparatus for biasing a charge pump'20006,085,345'Timing control for input/output testability'20006,075,285'Semiconductor package substrate with power die'20005,801,561'Power-on initializing circuit'19985,748,033'Differential power bus comparator'19985,627,736'Power supply noise filter'19975,539,337'Clock noise filter for integrated circuits'19965,399,918'Large fan-in, dynamic, bicmos logic gate'19955,345,120'Swing limiting circuit for BiCMOS sense amplifiers'19945,306,964'Reference generator circuit for BiCMOS ECL gate employing PMOS load devices'19945,153,848'Floating point processor with internal free-running clock'19924,982,352'Methods and apparatus for determining the absolute value of the difference between binary operands'19914,972,362'Method and apparatus for implementing binary multiplication using booth type multiplication'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–1992Patents assigned to BIPOLAR INTEGRATED TECHNOLOGY (3)· patent assignee history
1990–1991Based in Beaverton, OR, US· patent location history
1992–2019Based in Portland, OR, US· patent location history
1994–2019Patents assigned to INTEL CORP (50)· patent assignee history
2012–2014Patents assigned to TAYLOR GREGORY F (3)· patent assignee history
2012Patents assigned to CHEN ZHANPING (1)· patent assignee history
2014Patents assigned to ABDELMONEUM MOHAMED A (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 50 | 1994–2019 |
| BIPOLAR INTEGRATED TECHNOLOGY | 3 | 1990–1992 |
| TAYLOR GREGORY Fself | 3 | 2012–2014 |
| ABDELMONEUM MOHAMED A | 1 | 2014 |
| CHEN ZHANPING | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 52 | 1992–2019 |
| Beaverton, OR, US | 2 | 1990–1991 |