Method and apparatus for improving cycle time in a quad data rate SRAM device

The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for improving cycle time in a Quad Data Rate (QDR) Static Random Access Memory (SRAM) device.

Quad Data Rate (QDR) SRAM devices are currently being manufactured using a high-speed CMOS fabrication process. At the heart of the QDR architecture are two separate Double Data Rate (DDR) ports to allow simultaneous access to the memory storage array. Each port is dedicated, with one performing read operations while the other performs data write operations. By allowing two-way access to the memory array at DDR signaling rates, a quad data rate (QDR) is established.

A QDR SRAM system employs dual circuitry for both the address registers and logic controllers, thus allowing for the dual port architecture. While the WRITE port stores data into the memory storage array, the READ port can simultaneously retrieve data from therefrom. A single reference clock generator controls the speeds of both ports. One signal is passed to both logic controllers, resulting in a smooth flow of data. In addition, the clock generator controls the speed of the read and write data registers, providing consistent core bandwidth and operating rates. If individual timing signals were employed for each circuit, the signals could be slightly mismatched, thus resulting in a stall or crash of the memory system.

In earlier generation double data rate (DDR) devices, the core operations are directly timed from only the rising edge of the reference clock signal. As each address operation is performed, only two data operations can occur. Address operations are performed only during the rising edge of the clock signal. Because only one common data bus (port) is available, simultaneous read and write operations are not available with this technology. Unfortunately, even at higher megahertz clock speeds, DDR SRAM is challenged to provide sufficient bandwidth required by today's high-speed network communications equipment.

In comparison, the differences of QDR signaling versus DDR are evident. In order to facilitate a quad data rate, all data is carried by separate read and write ports. By using a DDR clock with two ports, information can be transferred at four data items per clock (assuming two operations are needed, one read and one write). However, notwithstanding the improved bandwidth provided by QDR SRAM in performing the read operation during the first half of the clock phase and the write operation during the second half of the clock phase, the maximum cycle time of the QDR SRAM is still limited since both the read and the write operations must be performed within one-half clock cycle. In essence, the SRAM performs a complete read and precharge, then a complete write and precharge, all within the same clock cycle.

Accordingly, it would be desirable to implement even further improvements in the cycle time of a QDR SRAM device, such as those used in high bandwidth applications like networking and communications systems.

The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corresponding to the captured read address onto a pair of bit lines. A write operation is commenced for the current clock cycle so as to cause write data to appear on the pair of bit lines as soon as the read data from the captured read address is amplified by a sense amplifier, wherein the write operation uses a previous write address captured during a preceding clock cycle. A current write address is captured during a second half of the current clock cycle, said current write address used for a write operation implemented during a subsequent clock cycle, wherein the write operation for the current clock cycle is timed independent of the current write address captured during said second half of the current clock cycle.

In another embodiment, a method for implementing a self-timed, read to write protocol for a Quad Data Rate (QDR) Static Random Access Memory (SRAM) device includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corresponding to the captured read address onto a pair of bit lines. A write operation is commenced for the current clock cycle so as to cause write data to appear on the pair of bit lines as soon as the read data from the captured read address is amplified by a sense amplifier, wherein the write operation uses a previous write address captured during a preceding clock cycle. A current write address is captured in a write address buffer during a second half of the current clock cycle, the current write address to be used for a write operation implemented during a subsequent clock cycle, wherein the write operation for the current clock cycle is timed independent of the current write address captured during the second half of the current clock cycle.

Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:

FIG. 1 is a timing diagram illustrating the operation of a conventionally configured network QDR SRAM device;

FIGS. 2( a ) and 2 ( b ) are schematic diagrams of an apparatus for implementing a self-timed, read to write protocol for a QDR SRAM device, in accordance with an embodiment of the invention;

FIG. 3 is a schematic diagram illustrating the read to write interlock portion of the apparatus shown in FIG. 2( a ); and

FIG. 4 is a timing diagram illustrating a simulation of the self-timed, read to write protocol, in accordance with a further embodiment of the present invention.

Disclosed herein is a method and apparatus for improving cycle time in a Quad Data Rate (QDR) Static Random Access Memory (SRAM) device, in which write addresses and data are captured and buffered to be used in a subsequent read to write cycle thus allowing the write operation to be timed immediately after the read operation. The start of the write operation does not wait until addresses and data are captured. Instead, the write address and data captured in the preceding cycle is used for the write operation of the current cycle, while the write address and data captured the current cycle is actually written in the next cycle.

In a conventionally configured network QDR SRAM device, the protocols dictate a read operation during the first half of the clock cycle and a write operation during the second half of the clock cycle. For example, as illustrated in the timing diagram of FIG. 1 , addresses A and B correspond to the read and write addresses, respectively. The write data for address B is input in double data rate mode on both the rising and falling edges of the clock signal. The write operation may only start as soon as the corresponding write addresses and data are captured and distributed internally, as reflected by the Internal Write Data signal in FIG. 1 . During the read cycle, activation of the word line (WL) signal starts a bit line signal development as shown by the signal differential on the complement and true bit-lines BLC/BLT. Then, the sense amplifier (SA) data lines are amplified once the SET signal is activated.

Following the read cycle, the write WL is decoded and the write data (DB) is written to the bit lines. In this protocol, cycle time margin is measured from the completion of the previous write cycle to the activation of the read WL for the current cycle. In the example illustrated, the 2.5 ns external cycle simulation of FIG. 1 shows a cycle time margin of only about 0.13 ns.

Therefore, in accordance with an embodiment of the invention, there is disclosed a method and apparatus for improving cycle time in a QDR SRAM device. Briefly stated, an improvement in the cycle time is achieved by implementing a self-timed read to write protocol in which write addresses and data are captured and buffered during a given read to write cycle are actually written in the next read to write cycle. As such, the write operation (of data and address captured in the previous cycle) may be timed immediately after the read operation of the current cycle. This capability is realized, in part, by generating a pair of write clock signals: one write clock for capturing previous cycle write and address data, and another write clock (delayed) for launching the internal write address captured during the previous cycle.

Referring generally now to FIGS. 2( a ) and 2 ( b ), there is shown a schematic diagram of one possible embodiment of an apparatus 200 for implementing a self-timed read to write protocol for a QDR SRAM device. In particular, apparatus 200 generates three self-resetting clock signals (labeled “Clkrd”, “Clkwr 1 ”, “Clkwr 2 ”) from read/write commands, as well as a system clock (labeled “Clock”). The signals Clkrd and Clkwr 1 are used to capture read and write addresses from rising and falling edges of Clock, respectively. In addition, Clkrd is also used to generate internal true and complement data addresses. Clkwr 2 is a delayed version of Clkrd that is used to launch the internal write address from the current buffered write address (i.e., the earlier write-cycle address) previously captured by Clkwr 1 .

It will be appreciated that the Clkwr 2 timing is not critical, since the precise timing between read and write cycles in a given array (or subarray) is locally controlled therein. As described in further detail hereinafter, a read to write interlock 202 includes sense amplifier interlock logic used to drive a set signal to the array sense amplifiers for a read operation, to isolate the sense amplifier from the bit lines through a pair of read bit switches, to enable a subarray (including word line) reset operation, and to enable a write activate signal that activates a pair of write bit switches for beginning the write operation.

As shown in FIG. 2( b ), address compare logic 204 is used to fetch read data directly from a write data buffer, rather from than the array itself, whenever data from the address to be read has not yet been written to memory. Thus, the read address (Radd) and the write address (Wadd) are compared with one another on every write cycle, wherein a signal (Match) is generated if the two addresses are equal.

FIG. 3 is a schematic diagram illustrating the read to write interlock 202 shown in FIG. 2( a ). As is shown, signals “Subd”, “We”, “Re”and “Bitd”are subarray-decode, write, read and bit-decode pulse input controls signals to the subarray, which is accessed through a plurality of local word line drivers 302 . For a selected subarray, the signal “Subsel”disables the bit line restore (i.e., precharging) devices through the signal labeled “BLrst”, and also enables the individual word lines (e.g., WL 0 . . . WL 255 ) and read bit switches (through signal RBS). In addition, through the use of a mimic (i.e., dummy) word line (WLM) and bit line (BLM), a signal sent therethrough is capable of tracking the delay through an actual word line and bit line. Moreover, WLM/BLM is also used to time the bit line signal development to as to ensure an adequate signal development at the sense amplifier.

As indicated earlier, the sense amplifier interlock logic 304 includes four functions: driving the SET signal to the sense amplifier(s) 306 ; disabling the read bit switches (through signal RBS) in order to isolate the sense amplifier from the bit lines; enabling a subarray reset (including read word line reset); and enabling signal WRT to activate a pair of write bit switches (activated by signal WBS) to start the write operation. Once the write operation begins, a Write Margin Mimic Delay circuit 308 times the duration of the write operation. The mimic delay circuit 308 provides a more precise timing of the write to the cell, as compared to the previous approach of using a read mimic bit line delay. The end of the write operation occurs when the mimic delay circuit disables signal WBS, enables precharging signal BLrst, and regenerates a second “Subrst”pulse that restores the write word line. Thus, the subarray timings are restored twice: first at the setting of the sense amplifier, and then again at the end of the write duration pulse.

FIG. 4 is a timing diagram illustrating a simulation of the self-timed, read to write protocol, in accordance with a further embodiment of the present invention. At the first rising edge of the main clock, the read portion of the read to write cycle commences. Internally, it is noted the write operation for the previous half-cycle is finishing up, as reflected by the deactivation of the previously addressed word line (signals WL, Wact go from high to low), and the deactivation of the write bit switches (WBS also goes low) to decouple the bit line pair from the write driver. In addition, the fully developed data signal on the bit lines BLC/BLT disappears as the voltage on both is restored to the precharge value of V DD .

At some point during the read half-cycle, the internally generated read clock signal Clkrd (from FIG. 2( a )) goes high to capture the read data and address for the current cycle. Once the addressed wordline signal (WL) is activated by going high and the read bit switches are activated (by RBS going low), an appropriate signal development takes place on the bit line pair BLC/BLT which will then be set and driven to the full swing value by the sense amplifier. It will also be noted, however, that at about the same point in time as the word line signal goes high for the read operation, the internally generated clock signal Clkwr 2 (the delayed version of Clkrd) is activated to begin the write operation immediately after the sense amplifier captures the read data.

Again, the write operation for a given cycle does not depend upon waiting to capture write data and address information during the second half of the current clock cycle, because such information was already captured in the prior cycle. Thus, Clkwr 2 is generated from Clkrd to launch the previously captured write address after the current read address is launched. The active low signal on the mimic bit line (BLM) activates write activation signal Wact, which in turn enables signal WBS for immediate writing of the write data (DZ) onto the bit line pair. There is no need to precharge the bit line pair once the read data is captured by the sense amplifier BL restore after the read operation; as can be seen in FIG. 4 , once the read word line signal is reset and the read bit switches are disabled (RBS goes high), the bit line pair is driven by write data. Finally, after the execution of the write margin mimic delay (i.e., the falling edge of signal Wact) the write bit switches are uncoupled, the write word line is restored and the bit lines BLC/BLT are precharged.

As will be appreciated, the cycle time margin achieved in the simulation of FIG. 4 is about 0.7 ns, which is a significant improvement over 0.13 ns in the conventional scheme of FIG. 1 . Given a 2.5 ns external cycle, then, a cycle time margin of 0.7 ns allows the external cycle time to be reduced to about 1.8 ns.

While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.