LexDanaLexDanabeta
Inventor

George M. Braceras

Inventor
Essex Junction, VT, US

Overview

59→
Patents
1987–2019
Patent span
Physics
Primary field (CPC G)

Patents· 59 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores63%
G06FElectric digital data processing11%
H03KPulse technique11%
G01RMeasuring electric variables6%
H04LTransmission of digital information, e.g. telegraphic communication5%
H02HEmergency protective circuit arrangements2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
10,522,217Column-dependent positive voltage boost for memory cell supply voltage201910,510,384Intracycle bitline restore in high performance memory20199,721,628'Address based memory data path programming scheme'20179,570,155'Circuit to improve SRAM stability'20179,570,156'Data aware write scheme for SRAM'20179,548,104'Boost control to improve SRAM write operation'20179,460,811'Read only memory (ROM) with redundancy'20169,437,282'High performance sense amplifier'20169,390,769'Sense amplifiers and multiplexed latches'20169,236,116'Memory cells with read access schemes'20168,839,054'Read only memory (ROM) with redundancy'20148,654,594'Vdiff max limiter in SRAMs for improved yield and power'20148,630,139'Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method'20148,611,164'Device and method for detecting resistive defect'20138,593,861'Asymmetric memory cells'20138,582,351'Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability'20138,279,687'Single supply sub VDD bit-line precharge SRAM and method for level shifting'20128,233,342'Apparatus and method for implementing write assist for static random access memory arrays'20128,233,337'SRAM delay circuit that tracks bitcell characteristics'20127,904,658'Structure for power-efficient cache memory'20117,894,291'Circuit and method for controlling a standby voltage level of a memory'20117,817,481'Column selectable self-biasing virtual voltages for SRAM write assist'20107,729,159'Apparatus for improved SRAM device performance through double gate topology'20107,643,357'System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture'20107,613,050'Sense-amplifier assist (SAA) with power-reduction technique'20097,573,300'Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same'20097,471,114'Design structure for a current control mechanism for power networks and dynamic logic keeper circuits'20087,408,800'Apparatus and method for improved SRAM device performance through double gate topology'20087,337,268'Content addressable memory structure'20087,307,457'Apparatus for implementing dynamic data path with interlocked keeper and restore devices'20077,180,320'Adaptive integrated circuit based on transistor current measurements'20077,120,732'Content addressable memory structure'20067,061,793'Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices'20066,999,547'Delay-lock-loop with improved accuracy and range'20066,967,861'Method and apparatus for improving cycle time in a quad data rate SRAM device'20056,922,076'Scalable termination'20056,897,674'Adaptive integrated circuit based on transistor current measurements'20056,829,183'Active restore weak write test mode'20046,754,791'Cache memory system and method for accessing a cache memory having a redundant array without displacing a cache line in a main array'20046,711,076'Active restore weak write test mode'20046,650,580'Method for margin testing'20036,542,418'Redundant memory array having dual-use repair elements'20036,509,778'BIST circuit for variable impedance system'20036,510,091'Dynamic precharge decode scheme for fast DRAM'20036,501,293'Method and apparatus for programmable active termination of input/output devices'20026,441,646'Structure and method of alternating precharge in dynamic SOI circuits'20026,392,949'High performance memory architecture'20026,038,181'Efficient semiconductor burn-in circuit and method of operation'20005,929,667'Method and apparatus for protecting circuits subjected to high voltage'19995,815,354'Receiver input voltage protection circuit'19985,802,070'Testing associative memory'19985,793,592'Dynamic dielectric protection circuit for a receiver'19985,781,922'Page boundary caches'19985,751,648'Two stage sensing for large static memory arrays'19985,715,198'Output latching circuit for static memory devices'19985,638,315'Content addressable memory for a data processing system'19975,561,781'Port swapping for improved virtual SRAM performance and processing of concurrent processor access requests'19965,557,768'Functional pipelined virtual multiport cache memory with plural access during a single cycle'19964,709,162'Off-chip driver circuits'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–2017Patents assigned to IBM (53)· patent assignee history
1987Based in South Burlington, VT, US· patent location history
1996–2004Based in Colchester, VT, US· patent location history
1998Based in Calchester, VT, US· patent location history
2000–2019Based in Essex Junction, VT, US· patent location history
2012–2014Patents assigned to BRACERAS GEORGE M (7)· patent assignee history
2012–2014Patents assigned to PILO HAROLD (7)· patent assignee history
2012–2014Patents assigned to ARSOVSKI IGOR (3)· patent assignee history
2014Based in Essex, VT, US· patent location history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM531987–2017
GLOBALFOUNDRIES INC92016–2019
BRACERAS GEORGE Mself72012–2014
PILO HAROLD72012–2014
ARSOVSKI IGOR32012–2014
Locations
LocationPatentsSpan
Essex Junction, VT, US462000–2019
Colchester, VT, US101996–2004
Essex, VT, US12014
Calchester, VT, US11998
South Burlington, VT, US11987