Inventor
Harold Pilo
Inventor
Underhill, VT, US
Overview
Patents· 90 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores73%
G01RMeasuring electric variables9%
H03KPulse technique8%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
G06FElectric digital data processing2%
G05FSystems for regulating electric or magnetic variables1%
H04LTransmission of digital information, e.g. telegraphic communication1%
H10BElectronic memory devices1%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
PatentTitleYear
11,017,873Memory bypass function for a memory202110,971,218Method and apparatus for memory noise-free wake-up protocol from power-down202110,706,916Method and apparatus for integrated level-shifter and memory clock202010,650,906Memory bypass function for a memory202010,636,457Overvoltage protection for a fine grained negative wordline scheme202010,381,052Overvoltage protection for a fine grained negative wordline scheme20199,953,698Overvoltage protection for a fine grained negative wordline scheme20189,881,666'Overvoltage protection for a fine grained negative wordline scheme'20189,734,891'Overvoltage protection for a fine grained negative wordline scheme'20179,734,892'Overvoltage protection for a fine grained negative wordline scheme'20179,679,635'Overvoltage protection for a fine grained negative wordline scheme'20179,613,700'TCAM field enable logic'20179,564,180'Deep-sleep wake up for a memory device'20179,318,162'Overvoltage protection for a fine grained negative wordline scheme'20169,311,978'Regulated power gating for growable memory'20169,230,637'SRAM circuit with increased write margin'20169,183,906'Fine granularity power gating'20159,123,439'SRAM write-assisted operation with VDD-to-VCS level shifting'20159,058,046'Leakage-aware voltage regulation circuit and method'20158,654,594'Vdiff max limiter in SRAMs for improved yield and power'20148,630,139'Dual power supply memory array having a control circuit that dynamically selects a lower of two supply voltages for bitline pre-charge operations and an associated method'20148,611,164'Device and method for detecting resistive defect'20138,611,169'Fine granularity power gating'20138,582,351'Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability'20138,437,201'Word-line level shift circuit'20138,363,453'Static random access memory (SRAM) write assist circuit with leakage suppression and level control'20138,279,687'Single supply sub VDD bit-line precharge SRAM and method for level shifting'20128,233,337'SRAM delay circuit that tracks bitcell characteristics'20128,233,342'Apparatus and method for implementing write assist for static random access memory arrays'20128,228,713'SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same'20128,218,378'Word-line level shift circuit'20128,027,207'Leakage compensated reference voltage generation system'20117,904,658'Structure for power-efficient cache memory'20117,894,291'Circuit and method for controlling a standby voltage level of a memory'20117,826,288'Device threshold calibration through state dependent burn-in'20107,817,481'Column selectable self-biasing virtual voltages for SRAM write assist'20107,791,977'Design structure for low overhead switched header power savings apparatus'20107,724,565'Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices'20107,716,619'Design structure for implementing dynamic data path with interlocked keeper and restore devices'20107,643,357'System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture'20107,613,050'Sense-amplifier assist (SAA) with power-reduction technique'20097,609,569'System and method for implementing row redundancy with reduced access time and reduced device area'20097,573,300'Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same'20097,548,080'Method and apparatus for burn-in optimization'20097,495,950'Voltage controlled static random access memory'20097,492,199'Fully synchronous DLL with architected update window'20097,489,582'Low overhead switched header power savings apparatus'20097,486,586'Voltage controlled static random access memory'20097,471,114'Design structure for a current control mechanism for power networks and dynamic logic keeper circuits'20087,466,582'Voltage controlled static random access memory'20087,403,061'Method of improving fuse state detection and yield in semiconductor applications'20087,400,546'Low overhead switched header power savings apparatus'20087,352,609'Voltage controlled static random access memory'20087,307,457'Apparatus for implementing dynamic data path with interlocked keeper and restore devices'20077,262,987'SRAM cell using tunnel current loading devices'20077,180,320'Adaptive integrated circuit based on transistor current measurements'20077,141,998'Method and apparatus for burn-in optimization'20067,061,793'Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices'20067,049,873'System and method for implementing a micro-stepping delay chain for a delay locked loop'20067,016,251'Method and apparatus for initializing SRAM device during power-up'20066,998,897'System and method for implementing a micro-stepping delay chain for a delay locked loop'20066,999,547'Delay-lock-loop with improved accuracy and range'20066,989,685'Method and system for maintaining uniform module junction temperature during burn-in'20066,967,861'Method and apparatus for improving cycle time in a quad data rate SRAM device'20056,944,090'Method and circuit for precise timing of signals in an embedded DRAM array'20056,922,076'Scalable termination'20056,915,467'System and method for testing a column redundancy of an integrated circuit memory'20056,912,165'Method for transparent updates of output driver impedance'20056,897,674'Adaptive integrated circuit based on transistor current measurements'20056,854,041'DRAM-based separate I/O memory solution for communication applications'20056,754,135'Reduced latency wide-I/O burst architecture'20046,509,778'BIST circuit for variable impedance system'20036,510,091'Dynamic precharge decode scheme for fast DRAM'20036,504,766'System and method for early write to memory by injecting small voltage signal'20036,501,675'Alternating reference wordline scheme for fast DRAM'20026,449,200'Duty-cycle-efficient SRAM cell test'20026,400,629'System and method for early write to memory by holding bitline at fixed potential'20026,392,949'High performance memory architecture'20026,327,224'On-chip method for measuring access time and data-pin spread'20016,219,288'Memory having user programmable AC timings'20016,208,572'Semiconductor memory device having resistive bitline contact testing'20016,198,666'Control input timing-independent dynamic multiplexer circuit'20016,134,182'Cycle independent data to echo clock tracking circuit'20006,133,749'Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance'20006,038,181'Efficient semiconductor burn-in circuit and method of operation'20005,978,929'Computer unit responsive to difference between external clock period and circuit characteristic period'19995,666,078'Programmable impedance output driver'19975,659,508'Special mode enable transparent to normal mode operation'19975,606,526'Glitch-free dual clok read circuit'19975,343,428'Memory having a latching BICMOS sense amplifier'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994Based in Austin, TX, US· patent location history
1997–2020Patents assigned to IBM (82)· patent assignee history
1997–2021Based in Underhill, VT, US· patent location history
1997Based in Chittenden County, VT, US· patent location history
2003Based in Fish Hill, VT, US· patent location history
2011Based in Essex Junction, VT, US· patent location history
2012–2014Patents assigned to PILO HAROLD (12)· patent assignee history
2012–2014Patents assigned to ARSOVSKI IGOR (7)· patent assignee history
2012–2014Patents assigned to BRACERAS GEORGE M (5)· patent assignee history
2012–2013Patents assigned to HOULE ROBERT M (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 82 | 1997–2020 |
| PILO HAROLDself | 12 | 2012–2014 |
| ARSOVSKI IGOR | 7 | 2012–2014 |
| BRACERAS GEORGE M | 5 | 2012–2014 |
| HOULE ROBERT M | 4 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Underhill, VT, US | 86 | 1997–2021 |
| Essex Junction, VT, US | 1 | 2011 |
| Fish Hill, VT, US | 1 | 2003 |
| Chittenden County, VT, US | 1 | 1997 |
| Austin, Texas, US | 1 | 1994 |