Semiconductor device and packaging system therefore

1. Field of the Invention

This invention relates to a semiconductor device and its packaging, specifically to a packaging system for a semiconductor switching device that accommodates a change in an input scheme of control signals of the switching device by changing wire bonding positions while using a same semiconductor chip and a same lead pattern.

2. Description of the Related Art

Switching elements for high frequency signals have been a focus of development in many application areas including mobile communication equipment that utilizes microwaves in GHz frequency range and alternates antennas and receiving/transmitting signals. Such a device is described, for example, in Japanese Laid Open Patent Publication No. Hei 9-181642. This type of device often includes a field effect transistor (FET) functioning as a high frequency switch, which is made of a gallium arsenide (GaAs) material, and is integrated as a monolithic microwave integrated circuit (MMIC) having the high frequency switches.

FIG. 1A is a plan view of a conventional packaging of a semiconductor switching device 63 , and FIG. 1B is a schematic cross-sectional view of the packaging of FIG. 1A cut along line B—B. The chip 63 is made of GaAs, and has an electrode pad I for receiving an input signal, two electrode pads C 1 , C 2 for a pair of control signals and two electrode pads O 1 , O 2 for emitting an output signal. The input electrode pad I is located between the two input electrode pads C 1 , C 2 . The chip 63 is mounted on an island 62 e using a conducting paste 70 , such as a solder. The electrode pads on the top surface of the chip 63 are connected to respective leads of a lead pattern 62 by bonding wires 64 . Namely, the control electrode pad C 1 is connected to a lead 62 a , the input electrode pad I is connected to a lead 62 b , the control electrode pad C 2 is connected to a lead 62 c , and the two output electrode pads O 1 , O 2 are connected to leads 62 d , 62 f , respectively. The island 62 e of the lead pattern 62 , which is electrically connected to the chip 63 , is connected to a ground voltage (reference voltage). A resin body 75 covers the chip 63 and the central portion of the lead pattern 62 . The far ends of the leads extend from the side of the resin body 75 . The lead pattern 62 is formed by a conventional stamping process.

The semiconductor switching device 63 has two switches (not shown in the figure), and each switch receives a control signal through the corresponding control electrode pad C 1 , C 2 , i.e., C 1 is for a first switch and C 2 is for a second switch, respectively. Such a switch is typically made of a field effect transistor (FET). A pair of control signals, for example signals A and B (not shown in the figure), which complement each other, is inputted to the two control electrode pads C 1 , C 2 , and then applied to the two switches of the device through the control electrode pads C 1 , C 2 . In one design, for example, signal A is applied to the first switch of the device through the control electrode pad C 1 , and signal B is applied to the second switch of the device through the control electrode pad C 2 . The chip 63 is manufactured to meet this specification so that the two control electrode pads C 1 , C 2 are located close to their corresponding switches. This design is referred to as a normal control switch and is schematically shown in FIG. 2 . However, in another design of the device, it may be required that signal A be applied to the second switch and signal B be applied to the first switch. This is referred to as a reverse control switch and is schematically shown in FIG. 3 . In this reverse design, additional wiring is required to reverse the signal inputs as shown in FIG. 3 . Accordingly, two different device manufacturing processes must be established for the two different device designs.

The invention provides a semiconductor device including an insulating substrate, a plurality of leads disposed on the substrate, and a semiconductor chip mounted on the insulating substrate and having a plurality of electrode pads disposed on its surface. The electrode pads are connected to the respective leads. The semiconductor chip is disposed with respect to two of the leads to leave areas of each of the two leads not covered by the semiconductor chip at each end of the semiconductor chip. The areas of the two leads are large enough for connecting corresponding leads to the corresponding electrode pads. A first of the two leads is connected to a first of the two electrode pads and a second of the two leads is connected to a second of the two electrode pads when the device is configured so that first of the two electrode pads receives a first signal and the second of the two electrode pads receives a second signal. The first of the two leads is connected to the second of the two electrode pads and the second of the two leads is connected to the first of the two electrode pads when the device is configured so that the first of the two electrode pads receives the second signal and the second of the two electrode pads receives the first signal.

The invention also provides a semiconductor device including a resin body, a plurality of leads embedded in the resin body, and a semiconductor chip embedded in the resin body and having a plurality of electrode pads disposed on its surface. The electrodes pads are connected to the respective leads. The semiconductor chip is disposed with respect to two of the leads to leave areas of each of the two leads uncovered by the semiconductor chip at the ends of the semiconductor chip. The areas of the two leads are large enough for connecting the two leads to the corresponding electrode pads. A first of the two leads is connected to a first of the two electrode pads and a second of the two leads is connected to a second of the electrode pads when the semiconductor device is configured so that the first of the two electrode pads receives a first signal and the second of the two electrode pads receives a second signal. The first of the two leads is connected to the second of the two electrode pads and the second of the two leads is connected to the first of the two electrode pads when the semiconductor device is configured so that the first of the two electrode pads receives the second signal and the second of the two electrode pads receives the first signal.

The invention further provides a device packaging system including an insulating substrate, a first lead disposed on the insulating substrate, a second lead disposed on the insulating substrate, and a surface mounted element mounted on the first and second leads so that at least a portion of each of the leads is left uncovered by the surface mounted element at both ends of the surface mounted element.

The invention also provides a device packaging system including a resin body, a first lead embedded in the resin body, a second lead embedded in the resin body, and a surface mounted element mounted on the first and second leads so that at least a portion of each of the leads is left uncovered by the surface mounted element at both ends of the surface mounted element.

The invention further provides a method of fabricating devices with different internal wirings. This method includes providing lead wiring means for allowing alternative wire bonding configurations, which have a first lead and a second lead, and mounting a surface mounted element on the lead wiring means, which has a first electrode pad and a second electrode pad. The method also includes connecting the first electrode pad to the first lead by a first bonding wire and connecting the second electrode pad to the second lead by a second bonding wire so that the first and second bonding wires do not intersect each other when a device of a first wiring configuration is fabricated, and connecting the first electrode pad to the second lead by the first bonding wire and connecting the second electrode pad to the first lead by the second bonding wire so that the first and second bonding wires do not intersect each other when a device of a second wiring configuration is fabricated.

FIG. 1A is a plan view of a conventional packaging of a semiconductor switching device, and FIG. 1B is a schematic cross-sectional view of the packaging of FIG. 1A cut along line B—B of FIG. 1 A.

FIG. 2 is a schematic circuit diagram showing a connection of a normal control switch.

FIG. 3 is a schematic circuit diagram showing a connection of a reverse control switch.

FIG. 4A is a plan view of a lead pattern of a first embodiment of the invention, and FIG. 4B is a perspective view of an insulating substrate having the lead pattern thereon of the first embodiment.

FIG. 5 is a plan view of a compound semiconductor chip of the first embodiment.

FIG. 6A is a plan view of a packaging with a reverse switch configuration using the lead pattern of FIG. 4 A and the chip of FIG. 5, and FIG. 6B is a plan view of a packaging with a normal switch configuration using the lead pattern of FIG. 4 A and the chip of FIG. 5 .

FIG. 7 is a schematic cross-sectional view of the packaging of FIG. 6A cut along line A—A of FIG. 6 A.

FIG. 8A is a schematic cross-sectional view of a packaging of a second embodiment of the invention, and FIG. 8B is a device intermediate of the packaging of FIG. 8 A.

FIG. 9A is a plan view of a conductive foil for forming a lead pattern of the second embodiment, and FIG. 9B is a plan view of one frame of the conductive foil of FIG. 9A with lead patterns.

FIG. 10 is a plan view of the packaging of the first embodiment with an alternative lead configuration.

A semiconductor device with a packaging structure of a first embodiment of this invention is described with reference to FIGS. 4A-7. FIG. 4A show a lead pattern 2 formed on an insulating substrate 1 of the first embodiment. The insulating substrate 1 is a large insulating plate made of a ceramic, a glass epoxy resin or the like, or a stack of such insulating plates. The total thickness of the insulating substrate 1 is 180 to 250 μm, so that the substrate can withstand mechanical stresses it receives during manufacturing processes.

The lead pattern 2 for one packaging area 10 , which is indicated by the unevenly broken lines in FIGS. 4A and 4B, includes six individual leads that are formed on the insulating substrate 1 and correspond to electrode pads formed on a semiconductor chip for packaging, as shown in FIG. 4 A. The semiconductor chip is mounted on a chip mounting area 11 . The six leads are formed by a gold plating, and two of the six leads penetrate through the chip mounting area 11 to provide areas for wire bonding at both ends of the chip mounting area 11 . The lead pattern 2 does not have an island, such as the one shown FIG. 1A, and a semiconductor chip is mounted on the two leads penetrating though the chip mounting area 11 using an insulating resin. All the lead patterns 2 are identical among the individual packaging areas 10 , and are connected by a connection portion 12 . In this embodiment, the packaging area 10 is about 1.2 mm×0.8 mm, and the chip mounting area 11 is about 0.30 mm×0.37 mm, although the size of the chip mounting area 11 should be adjusted according to the size of a chip mounted thereon. The separations between the package areas 10 are about 100 μm in both the longitudinal and the transverse directions. This separation is required for dicing the substrate 1 into separate individual completed packages. The connection portion 12 is required to form the lead pattern 2 using gold plating. When electroless plating is used for forming the lead pattern 2 , the connection portion is not required and the package areas 10 are formed to be separated from each other.

FIG. 4B is a perspective view of the insulating substrate 1 used in the first embodiment. The substrate 1 is large enough to provide more than one hundred package areas 10 .

FIG. 5 is a plan view of the semiconductor chip 3 used in the first embodiment. The semiconductor chip 3 is a compound semiconductor switching device, and its circuit elements are formed on a GaAs substrate. The back side of the GaAs substrate is semi-insulating. The chip has two FETs, FET 1 , FET 2 positioned in the central portion of the GaAs substrate. The gate electrodes 17 of FET 1 and FET 2 are connected to control electrode pads C 1 , C 2 , respectively, through corresponding resistors R 1 , R 2 . Both of the drain electrodes 15 of the two FETs are connected to an input electrode pad I. The source electrodes 13 of the two FETs are connected to output electrode pads O 1 , O 2 , respectively. All the electrode pads are positioned near the edge of the GaAs substrate, and correspond to the electrode pads of the semiconductor chip 3 . This type of switching device is described in a commonly owned copending U.S. patent application Ser. No. 09/937,197, entitled “COMPOUND SEMICONDUCTOR DEVICE,” the disclosure of which is, in its entirety, incorporated herein by reference.

A gate metal layer 20 made of Ti/Pt/Au is a second wiring layer indicated by the dotted lines in the figure, and includes the gate electrode 17 , which forms a Schottky contact with a channel region of each FET. A pad metal layer 40 made of Ti/Pt/Au is a third wiring layer indicated by the solid lines in the figure, and provides electrode pads and connections between circuit elements. An ohmic metal layer made of AuGe/Ni/Au is a first wiring layer, and forms an ohmic contact with the GaAs substrate. The ohmic metal layer provides the source electrodes 13 and the drain electrodes 15 of the two FETs as well as contact portions of the resistors. The ohmic metal layer overlaps with the pad metal layer 40 and is omitted in the figure.

FIGS. 6A and 6B show two different configurations of the packaging of the first embodiment, which utilize the same lead pattern of FIG. 4 A and the same semiconductor chip of FIG. 5 . In the configuration of FIG. 6A, the semiconductor chip 3 is mounted on the two leads 2 a , 2 c penetrating through the chip mounting area using an insulating resin adhesive. The two leads 2 a , 2 c run underneath the semiconductor chip 3 , and provide areas not covered by the semiconductor chip 3 at the ends of the semiconductor chip 3 , that are large enough for connecting leads to the corresponding electrode pads on the semiconductor chip 3 by wire bonding. The mounting position of the semiconductor chip 3 may be adjusted as long as the uncovered areas are large enough and close enough to the chip 3 for wire bonding.

A lead 2 b is connected to the input electrode pad I, a lead 2 d to the output electrode pad O 1 , a lead 2 f to the output electrode pad O 2 , the lead 2 c to the control electrode pad C 2 , and the lead 2 a to the control electrode pad C 1 . All the connections are made by wire-bonding the leads to the corresponding electrode pads by ball bonding or wedge bonding. The control electrode pad C 1 may be connected to either of the two penetrating leads 2 a , 2 c at the left end of the semiconductor chip 3 . In this configuration, it is connected to the lead 2 a . Likewise, the control electrode pad C 2 is connected to the lead 2 c , instead of the lead 2 a , at the right end of the semiconductor chip 3 . The lead 2 e is at a ground voltage (reference voltage).

In the configuration of FIG. 6B, the connections between the two penetrating leads 2 a , 2 c and the two control electrode pads C 1 , C 2 are altered. That is, in this configuration, the control electrode pad C 1 is connected to the lead 2 c , and the control pad C 2 is connected to the lead 2 a . Other connections between the electrode pads and the leads are the same as those of FIG. 6 A. In both configurations, there are no intersecting bonding wires, which can cause signal interference and larger packaging height.

The configuration of FIG. 6B is a normal control switch and the configuration of FIG. 6A is a reverse control switch. When a pair of complementary signals is applied to the device, signal A of the pair is applied to the lead 2 c and signal B of the pair is applied to the lead 2 a . In the normal control switch of FIG. 6B, signal A is applied to the gate electrode 17 of the FEF 1 through the electrode pad C 1 , and signal B is applied to the gate electrode 17 of the FET 2 through the electrode pad C 2 . In the reverse control switch of FIG. 6A, signal A is applied to the gate electrode 17 of FET 2 and signal B is applied to the gate electrode 17 of the FET 1 .

For both of the configurations, the same lead pattern of FIG. 4 A and the same semiconductor chip of FIG. 5 are used. The only difference is the connections between the penetrating leads 2 a , 2 c and the corresponding electrode pads C 1 , C 2 . These connections are made just by connecting the leads 2 a , 2 c to the corresponding electrode pads C 1 , C 2 . In other words, there is no need for changing the chip design or the lead pattern design. This is possible because each of the two leads 2 a , 2 c has areas large enough to allow wire bonding at both ends of the semiconductor chip. Accordingly, the packaging of the first embodiment provides both the normal and reverse control switches without any modification to the chip or the lead pattern.

The lead pattern 2 is formed by a plating process based on thick film printing. Accordingly, the separations between the leads are as small as 75 μm. This contributes to reduction of overall packaging size because the minimum separation of the conventional lead pattern formed by stamping as shown in FIG. 1A is as large as 120 μm, which is 0.8×frame thickness (150 μm).

FIG. 7 is a schematic cross-sectional view of the packaging structure of FIG. 6A cut along line A—A. The compound semiconductor chip 3 is mounted on the leads 2 a , 2 c with an insulating resin adhesive 50 . The electrode pads are connected to the corresponding leads by the bonding wires 4 . A through hole 5 is formed in the insulating substrate 1 for each of the leads, and connects the lead to a corresponding external electrode 6 formed on the back side of the insulating substrate 1 . The through holes are filled with conducting materials such as tungsten. A resin body 15 seals the semiconductor chip 3 .

As indicated by the dotted circles in FIGS. 6A and 6B, six external electrodes 6 are positioned near the edge of the insulating substrate 1 in a symmetrical manner. Namely, the external electrodes 6 for the electrode pads C 1 , I, C 2 are lined up along the top edge of insulating substrate 1 , and the external electrodes 6 for the electrode pads O 1 , O 2 and the ground lead 2 e are lined up along the bottom edge of the insulating substrate 1 .

Four sides of the individual packaging are cut-away surfaces of the resin body 15 and the insulating substrate 1 . Top and bottom surfaces of the individual packaging are a flattened top surface of the resin body 15 and the bottom surface of the insulating substrate 1 , respectively. In this embodiment, the thickness of the resin body is about 0.3 mm and the thickness of the semiconductor chip 3 is about 130 μm.

Because of the symmetrical configuration of the external electrodes 6 , it may be difficult to identify each external electrode 6 . For this reason, an identification marking for each external electrode 6 is formed on the top surface of the resin layer 15 at a corresponding location. Markings may be formed by indenting the top surface or printing the top surface.

Because the lead pattern 2 is formed on the insulating substrate 1 by gold plating or the like in this embodiment, overall packaging size is much smaller than the size of the conventional packaging of FIG. 1A, in which a lead pattern is made by stamping a metal plate.

A semiconductor device with a packaging structure of a second embodiment of this invention is described with reference to FIGS. 8A-9B. FIG. 8A is a cross-sectional view of the semiconductor device of the second embodiment. The lead pattern of this embodiment is substantially the same as the lead pattern 2 of the first embodiment as shown in FIG. 4 A. The packaging structure of this embodiment is similar to the packaging structure of the first embodiment shown in the plan view of FIGS. 6A and 6B. The cross section of FIG. 8A is made along line A—A of FIG. 6 A. All the leads and the corresponding electrode pads on the chip are positioned and connected in the same manner as in the two configurations of the first embodiment. The chip 23 used in this embodiment is the same chip used in the first embodiment. This packaging also provides two different switches, a normal control switch and a reverse control switch, using the same lead pattern and the same chip just by changing the wire bond connection of two leads.

As shown in FIG. 8A, the difference between the two embodiments is that the lead pattern 22 of the second embodiment is embedded in and supported by the resin body 21 . No other support is provided in the second embodiment for the lead pattern 22 of the device. On the other hand, the lead pattern 2 of the first embodiment is supported by the insulating substrate 1 .

The resin layer 21 covers the lead pattern 22 and the chip 23 , and fills the space 31 between portions of the lead pattern 22 . The chip 23 is mounted on the leads ( 2 a 2 c in FIG. 6A) with an insulating adhesive 50 . The side of the lead pattern 22 is curved inwardly (not shown in the figure) for engaging with the resin body 21 to strengthen the connection between the resin body 21 and the lead pattern 22 . A thermosetting resin, such as an epoxy resin, is used to form the resin body 21 by transfer molding and seals the chip 23 and the lead pattern 22 . Alternatively, a thermoplastic resin, such as a polyimide resin or a polyphenylene sulfide resin, is used to form the resin body 21 by injection molding.

The thickness of the resin body 21 is adjusted so that the separation between the top of the bonding wire 24 and the top surface of the resin body 21 is about 50 μm. The thickness may vary depending on the mechanical strength required for the packaging. The packaging structure is annealed to flatten out the top surface of the resin body 21 . This annealing is required to suppress the bending of the packaging due to the difference in thermal expansion coefficients between the lead pattern 22 and the resin body 21 as well as the difference in contraction rate after a re-flow process.

FIG. 8B is a cross-sectional view of a device intermediate from which the device shown in FIG. 8A is formed. The lead pattern 22 is formed by creating the space 31 in a conductive foil 30 . At this point of manufacturing step, all the lead patterns are a part of the continuous conductive foil 30 , as shown in FIG. 9 B. Removing the back side of the conductive foil 30 separates the conductive foil 30 into individual lead patterns. The removing methods include grinding, polishing, etching and laser evaporation among other methods. As a result, the lead pattern 22 is exposed on the back side of the resin body 21 , and the back surface of the lead pattern 22 and the back surface of the resin body 21 are at the same level.

A photoresist layer 27 covers the back side of the packaging and has openings to expose the back side of the leads. Solder bumps are formed in the openings to work as external electrodes 26 . These solder bumps are movable under surface tension during the mounting of the device on a circuit board so that the device and the board are aligned by itself.

FIG. 9A is a plan view of a conductive foil 30 used for forming the packaging structure of the second embodiment. The conductive foil 30 may be made of copper, and its thickness before the removal of the back side is about 70 μm. The thickness may be anywhere between 10 and 300 μm, and can be outside this range provided that the depth of the space 31 is shorter than the thickness of the conductive foil 30 . A plurality of frames 32 is formed in the conductive foil 30 . The conductive foil 30 may be also made of aluminum, an iron-nickel alloy or other suitable material. If requirements for adhesion to the soldering materials, adhesion to the resin layer and plating of other metal are met, other metals can be used as the conductive foil 30 .

FIG. 9B is an expanded plan view of one frame 32 of the conductive foil 30 of FIG. 9 A. The frame 32 contains 25 package areas 10 , one of which is indicated by the area encircled by the dotted line in the figure. In the package area 10 , the portions encircled by the solid lines represent the portions of the conductive foil 30 that are not etched, and the other portions of the package area 10 represent the portions of the conductive foil 30 that are etched to form the space 31 (FIG. 8 B). The unetched portions provide the lead pattern 22 after the back side of the conductive foil 30 is removed. Because the lead pattern 22 is formed by etching, the separations between the leads can be as small as the spatial resolution of the etching method. This contributes to reduction of overall packaging size.

In the second embodiment, the conductive foil 30 supports the chip 23 until the resin body 21 covers the chip 23 and the lead pattern 22 . This removes the requirement of an additional support, i.e., the insulating substrate 1 of the first embodiment. Because of the absence of the rigid substrate, the flexible sheet like structure of the conductive foil 30 makes handling of the device intermediate easy and simple during manufacturing.

FIG. 10 is a plan view of the packaging of the first embodiment with an alternative lead configuration. This lead configuration is the same as the lead configuration of FIG. 6A except that the leads 2 a , 2 c do not run underneath the semiconductor chip and instead run along edges of the chip. In this lead configuration as well, each of the two leads 2 a , 2 c has areas large enough for wire bonding at the ends of the semiconductor chip. Accordingly, the packaging of the first embodiment with this alternative lead configuration also provides both the normal and reverse control switches without any modification to the chip or the lead pattern. This alternative lead configuration is also applied to the second embodiment. It should noted that in the embodiments described above the boding wires are configured not to intersect each other.

In the first and second embodiments, a switching device made of a compound semiconductor is mounted on the lead pattern. However, other semiconductor chips, including other integrated circuits, transistors and diodes that are made of silicon or compound semiconductors, can be mounted on the lead pattern in the packaging. Furthermore, passive elements, including chip capacitors, chip resistors and chip inductors, can be also mounted. Elements that are mounted with the top surface facing the lead pattern can be also mounted in this packaging system. In other words, any surface mounted element can be used in the packaging system of this invention.

The above is a detailed description of particular embodiments of the invention which is not intended to limit the invention to the embodiments described. It is recognized that modifications within the scope of the invention will occur to persons skilled in the art. Such modifications and equivalents of the invention are included within the scope of this invention.