Via bottom copper/barrier interface improvement to resolve via electromigration and stress migration

The present invention relates generally to semiconductor fabrication and more specifically to formation of copper structures having a lower copper layer/barrier layer interface.

When forming conventional copper structures in a via opening exposing an underlying relatively wide copper line, i.e. greater than about 2 μm, a bulge or hump of the underlying copper forms in the via due to the thermal process. The thermal process causes the copper to “grow” due to the thermal expansion of the underlying copper line at temperatures of from about 120 to 250° C.

A barrier layer is then formed within the via opening, lining the via opening and a second layer of copper is deposited over the barrier layer, filling the via opening. The second copper layer is then planarized to form a planarized copper structure. Later, during burn-in or reliability testing, the underlying copper layer hump shrinks due to stress migration (SM) leaving a void at the via bottom adjacent the barrier layer which deleteriously affects performance of the device(s).

U.S. Pat. No. 6,214,731 B1 to Nogami et al. describes a method of forming copper interconnection patterns whereby a barrier layer liner is formed within a via opening; a thin silicon layer is formed over the barrier layer liner; copper is deposited to fill the opening and is reacted with the thin silicon layer to form a thin layer of copper silicide at the interface between the copper layer and the barrier layer liner.

U.S. Pat. No. 6,211,084 B1 to Ngo et al. describes a copper silicide cap layer.

U.S. Pat. No. 6,046,108 to Liu et al. describes a selective copper silicide process and a copper interconnect process.

U.S. Pat. No. 5,447,887 to Filipiak et al. describes a copper silicide process.

Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of forming a copper layer/barrier layer interface.

Other objects will appear hereinafter.

It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a lower copper layer formed thereover is provided. A patterned dielectric layer is formed over the lower copper layer. The patterned dielectric layer having an opening exposing a portion of the lower copper layer. The exposed portion of the lower copper layer is converted to a copper silicide portion. A barrier layer is formed upon the patterned dielectric layer and the copper silicide portion, lining the opening, whereby the lower copper layer/barrier layer interface is formed such that the barrier layer contacts the copper silicide portion to form an interface.

The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:

FIGS. 1 to 3 schematically illustrate a preferred embodiment of the present invention.

Initial Structure

As shown in FIG. 1 , structure 10 has a metal layer 12 formed thereover. Metal layer 12 is preferably comprised of copper, aluminum, silver or gold and is more preferably comprised of copper as will be used for illustrative purposes hereafter. Copper layer 12 is preferably from about 1000 to 8000 Å thick and is more preferably from about 1000 to 5000 Å thick. Copper layer 12 may be, for example, a copper line having a width of greater than about 0.5 to 3.0 μm and more preferably greater than about 2.0 μm.

Structure 10 is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.

A dielectric layer 14 is formed over copper line 12 to a thickness of preferably from about 1000 to 10,000 Å and more preferably from about 3000 to 8000 Å. Dielectric layer 14 is preferably comprised of SiOCH or FSG. Dielectric layer 14 may be an intermetal dielectric (IMD) layer.

Dielectric layer 14 is patterned to form opening 16 therein, exposing a portion 18 of copper line 12 . Opening 16 may be a damascene opening or a dual damascene opening.

Formation of Metal Silicide Portion 20

In one key step of the invention, metal/copper line portion 18 is converted to a metal/copper silicide portion 20 by: either (1) a silicon-containing gas or precursor soak process; or (2) a plasma-assisted copper silicide formation process. Metal/copper silicide portion 20 has a thickness of preferably from about 5 to 1000 Å and more preferably from about 10 to 500 Å.

(1) In the silicon-containing gas or precursor soak process, the copper line portion 18 is subjected to a silicon (Si)-containing gas soak or a precursor soak preferably such as SiH 4 , Si 2 H 6 , 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS) or 4-methylsilane (4MS) and is more preferably SiH 4 or Si 2 H 6 . The soak is conducted at a temperature preferably from about 10 to 800° C. and more preferably from about 100 to 400° C. for preferably from about 0.1 to 100 seconds and more preferably, for from about 1 to 10 seconds. Soaking involves heating in a gas environment.

(2) The plasma assisted copper silicide formation process is conducted preferably using a silicon-containing plasma, a SiH 4 plasma, a Si 2 H 6 plasma, a 1MS plasma, a 2MS plasma, a 3MS plasma or a 4MS plasma and more preferably a SiH 4 plasma under the following conditions:

power: preferably from about 10 to 1000 watts and more preferably from about 50 to 500 watts;

bias power: preferably from about 0 to 1000 watts and more preferably from about 0 to 100 watts;

temperature: preferably from about 10 to 800° C. and more preferably from about 100 to 400° C.;

SiH 4 flow rate: preferably from about 1 to 500 sccm and more preferably from about 10 to 100 sccm;

time: preferably from about 0.1 to 100 seconds and more preferably from about 1 to 10 seconds; and

pressure preferably from about 1 mTorr to 100 Torr and more preferably from about 10 mTorr to 10 Torr.

Formation of Barrier Layer 22 and Planarized Copper Structure 24

As shown in FIG. 3 , a barrier layer 22 is then formed over the patterned dielectric layer 14 and the copper silicide portion 20 , and lining the opening 16 . The barrier layer 22 has a thickness of preferably from about 5 to 500 Å and more preferably from about 10 to 100 Å. The barrier layer 22 is preferably formed of TaN, Ta, Ti, TiN, TiSiN or WN and is more preferably comprised of TaN, Ta, Ti or TiN.

An upper metal layer is deposited over the barrier layer 22 and is then planarized, preferably by chemical mechanical polishing (CMP), to form a planarized metal structure 24 within the barrier layer 22 lined opening 16 . The upper metal layer is preferably comprised of copper, aluminum, silver or gold and is more preferably comprised of copper.

The advantages of one or more embodiments of the present invention include resolution of the copper stress migration issue.

While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.