Inventor
Tien-I Bao
Inventor
Dayuan Township, TW
Overview
Patents· 222 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H01LSemiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10DInorganic electric semiconductor devices8%
G02BOptical elements, systems or apparatus4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light1%
C23CCoating metallic material1%
C09KMaterials for miscellaneous applications, not provided for elsewhere1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
PatentTitleYear
11,049,811Forming interlayer dielectric material by spin-on metal oxide deposition202111,011,421Semiconductor device having voids and method of forming same202110,983,278Adhesion promoter apparatus and method202110,943,867Schemes for forming barrier layers for copper in interconnect structures202110,943,820Gap-fill method having improved gap-fill capability202110,910,216Low-k dielectric and processes for forming same202110,867,922Porogen bonded gap filling material in semiconductor manufacturing202010,867,913Method and apparatus for forming self-aligned via with selectively deposited etching stop layer202010,867,906Conductive structures in semiconductor devices202010,868,143Spacers with rectangular profile and methods of forming the same202010,867,958Integrated circuit with a thermally conductive underfill202010,861,742Interconnect structure having an etch stop layer over conductive lines202010,854,458Method and structure for semiconductor device having gate spacer protection layer202010,847,634Field effect transistor and method of forming the same202010,840,154Method for forming semiconductor structure with high aspect ratio202010,833,170Low-k gate spacer and methods for forming the same202010,818,600Structure and method for a low-k dielectric with pillar-type air-gaps202010,818,596Method for forming semiconductor device structure with graphene layer202010,784,160Semiconductor device having voids and method of forming same202010,714,620FinFETs and methods of forming FinFETs202010,700,000Semiconductor structure and method making the same202010,679,846System and method of forming a porous low-K structure202010,665,467Spacer etching process for integrated circuit design202010,629,479Structure and method for interconnection202010,539,751Optical bench on substrate202010,527,788Package structure and methods of forming same202010,515,823Via connection to a partially filled trench201910,505,018Spacers with rectangular profile and methods of forming the same201910,490,650Low-k gate spacer and methods for forming the same201910,483,169FinFET cut-last process using oxide trench fill201910,408,998Method of fabrication polymer waveguide201910,353,147Etchant and etching process for substrate of a semiconductor device201910,354,954Copper etching integration scheme201910,332,838Schemes for forming barrier layers for copper in interconnect structures201910,312,136Etch damage and ESL free dual damascene metal interconnect201910,312,139Interconnect structure having an etch stop layer over conductive lines201910,290,536Structure and method for interconnection201910,269,567Multi-layer mask and method of forming same201910,269,757Integrated circuit with a thermally conductive underfill and methods of forming same201910,269,634Semiconductor device having voids and method of forming same201910,261,248Package structure and methods of forming same201910,180,547Optical bench on substrate201910,170,306Method of double patterning lithography process using plurality of mandrels for integrated circuit applications201910,162,198Multiband QAM interface for slab waveguide201810,164,114FinFETs and methods of forming FinFETs201810,163,797Forming interlayer dielectric material by spin-on metal oxide deposition201810,126,512Differential silicon interface for dielectric slab waveguide201810,103,102Structure and formation method of semiconductor device structure201810,090,245Semiconductor device structure201810,082,626Adhesion promoter apparatus and method201810,074,607Semiconductor device structure with graphene layer201810,068,770Method and structure for semiconductor device having gate spacer protection layer201810,049,919Semiconductor device including a target integrated circuit pattern201810,020,259Copper etching integration scheme201810,014,175Lithography using high selectivity spacers for pitch reduction201810,008,382Semiconductor device having a porous low-k structure201810,002,826Semiconductor device structure with conductive pillar and conductive line and method for forming the same20189,997,404Method of forming an interconnect structure for a semiconductor device20189,985,134FinFETs and methods of forming FinFETs20189,966,336Hybrid interconnect scheme and methods for forming the same20189,941,157Porogen bonded gap filling material in semiconductor manufacturing20189,922,927'Method and apparatus for forming self-aligned via with selectively deposited etching stop layer'20189,911,732'Vertical metal insulator metal capacitor having a high-k dielectric material'20189,911,623'Via connection to a partially filled trench'20189,910,217'Method of fabrication polymer waveguide'20189,911,646'Self-aligned double spacer patterning process'20189,905,457'High boiling temperature solvent additives for semiconductor processing'20189,881,871'Schemes for forming barrier layers for copper in interconnect structures'20189,865,539'Structure and formation method of semiconductor device structure'20189,857,688'Method of forming fine patterns'20189,859,152'Protecting layer in a semiconductor structure'20189,852,915Etching apparatus20179,831,117Self-aligned double spacer patterning process20179,831,090Method and structure for semiconductor device having gate spacer protection layer20179,818,690'Self-aligned interconnection structure and method'20179,806,026'Self repairing process for porous dielectric materials'20179,799,603'Semiconductor device structure and method for forming the same'20179,799,558'Method for forming conductive structure in semiconductor structure'20179,793,264'Vertical metal insulator metal capacitor having a high-K dielectric material'20179,786,549'Etch damage and ESL free dual damascene metal interconnect'20179,773,676'Lithography using high selectivity spacers for pitch reduction'20179,768,024'Multi-layer mask and method of forming same'20179,735,052'Metal lines for interconnect structure and method of manufacturing same'20179,709,905'System and method for dark field inspection'20179,698,100'Structure and method for interconnection'20179,685,368'Interconnect structure having an etch stop layer over conductive lines'20179,659,857'Semiconductor structure and method making the same'20179,659,864'Method and apparatus for forming self-aligned via with selectively deposited etching stop layer'20179,651,736'Self-alignment due to wettability difference of an interface'20179,640,397'Method of fabricating a semiconductor integrated circuit using a directed self-assembly block copolymer'20179,633,949'Copper etching integration scheme'20179,633,958'Bonding pad surface damage reduction in a formation of digital pattern generator'20179,627,206'Method of double patterning lithography process using plurality of mandrels for integrated circuit applications'20179,614,053'Spacers with rectangular profile and methods of forming the same'20179,607,850'Self-aligned double spacer patterning process'20179,589,890'Method for interconnect scheme'20179,576,814'Method of spacer patterning to form a target integrated circuit pattern'20179,570,305'Self-aligned double patterning'20179,568,677'Waveguide structure and method for fabricating the same'20179,564,397'Interconnect structure and method of forming the same'20179,502,261'Spacer etching process for integrated circuit design'20169,490,133'Etching apparatus'20169,490,148'Adhesion promoter apparatus and method'20169,484,211'Etchant and etching process'20169,484,257'Semiconductor devices and methods of manufacture thereof'20169,478,939'Light coupling device and methods of forming same'20169,478,430'Method of semiconductor integrated circuit fabrication'20169,466,486'Method for integrated circuit patterning'20169,460,988'Interconnect structures'20169,431,297'Method of forming an interconnect structure for a semiconductor device'20169,412,651'Air-gap formation in interconnect structures'20169,405,063'Integrated metal grating'20169,383,513'Waveguide structure'20169,373,586'Copper etching integration scheme'20169,373,579'Protecting layer in a semiconductor structure'20169,372,316'Silicon interface for dielectric slab waveguide'20169,362,164'Hybrid interconnect scheme and methods for forming the same'20169,349,595'Methods of manufacturing semiconductor devices'20169,335,473'Package structure and methods of forming same'20169,318,377'Etch damage and ESL free dual damascene metal interconnect'20169,312,220'Structure and method for a low-K dielectric with pillar-type air-gaps'20169,291,913'Pattern generator for a lithography system'20169,293,413'Semiconductor devices and methods of manufacture thereof'20169,281,263'Interconnect structure including a continuous conductive body'20169,275,953'Semiconductor integrated circuit and fabricating the same'20169,236,277'Integrated circuit with a thermally conductive underfill and methods of forming same'20169,230,809'Self-aligned double patterning'20169,230,911'Interconnect structure and method of forming the same'20169,224,643'Structure and method for tunable interconnect scheme'20159,209,076'Method of double patterning lithography process using plurality of mandrels for integrated circuit applications'20159,177,797'Lithography using high selectivity spacers for pitch reduction'20159,165,822'Semiconductor devices and methods of forming same'20159,153,478'Spacer etching process for integrated circuit design'20159,134,633'System and method for dark field inspection'20159,136,106'Method for integrated circuit patterning'20159,129,968'Schemes for forming barrier layers for copper in interconnect structures'20159,129,906'Self-aligned double spacer patterning process'20159,123,776'Self-aligned double spacer patterning process'20159,087,877'Low-k interconnect structures with reduced RC delay'20159,041,015'Package structure and methods of forming same'20159,040,417'Semiconductor devices and methods of manufacture thereof'20159,036,956'Method of fabricating a polymer waveguide'20159,029,171'Self repairing process for porous dielectric materials'20159,001,308'Pattern generator for a lithography system'20158,975,189'Method of forming fine patterns'20158,976,833'Light coupling device and methods of forming same'20158,922,900'Optical element structure and optical element fabricating process for the same'20148,901,007'Addition of carboxyl groups plasma during etching for interconnect reliability enhancement'20148,894,869'Lithography process using directed self assembly'20148,889,544'Dielectric protection layer as a chemical-mechanical polishing stop layer'20148,890,321'Method of semiconducotr integrated circuit fabrication'20148,866,297'Air-gap formation in interconnect structures'20148,847,396'Semiconductor integrated circuit and fabricating the same'20148,835,304'Method of semiconductor integrated circuit fabrication'20148,836,127'Interconnect with flexible dielectric layer'20148,828,484'Self-alignment due to wettability difference of an interface'20148,736,014'High mechanical strength additives for porous ultra low-k material'20148,735,278'Copper etch scheme for copper interconnect structure'20148,729,703'Schemes for forming barrier layers for copper in interconnect structures'20148,728,936'Copper etching integration scheme'20148,710,660'Hybrid interconnect scheme including aluminum metal line in low-k dielectric'20148,664,743'Air-gap formation in interconnect structures'20148,652,962'Etch damage and ESL free dual damascene metal interconnect'20148,629,056'Method for forming self-assembled mono-layer liner for cu/porous low-k interconnections'20148,629,066'Liner formation in 3DIC structures'20148,446,012'Interconnect structures'20138,440,564'Schemes for forming barrier layers for copper in interconnect structures'20138,405,192'Low dielectric constant material'20138,348,719'Polisher for chemical mechanical planarization'20138,264,066'Liner formation in 3DIC structures'20128,232,201'Schemes for forming barrier layers for copper in interconnect structures'20128,158,521'Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties'20128,053,359'Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method'20118,030,781'Bond pad structure having dummy plugs and/or patterns formed therearound'20117,968,451'Method for forming self-assembled mono-layer liner for Cu/porous low-k interconnections'20117,964,496'Schemes for forming barrier layers for copper in interconnect structures'20117,732,326'Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method'20107,723,226'Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio'20107,682,963'Air gap for interconnect application'20107,564,136'Integration scheme for Cu/low-k interconnects'20097,482,265'UV curing of low-k porous dielectrics'20097,465,676'Method for forming dielectric film to improve adhesion of low-k film'20087,456,093'Method for improving a semiconductor device delamination resistance'20087,429,542'UV treatment for low-k dielectric layer in damascene structure'20087,365,026'CxHy sacrificial layer for cu/low-k interconnects'20087,314,828'Repairing method for low-k dielectric materials'20087,250,370'Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties'20077,250,364'Semiconductor devices with composite etch stop layers and methods of fabrication thereof'20077,244,673'Integration film scheme for copper / low-k interconnect'20077,223,692'Multi-level semiconductor device with capping layer for improved adhesion'20077,135,402'Sealing pores of low-k dielectrics using CxHy'20067,129,164'Method for forming a multi-layer low-K dual damascene'20067,109,119'Scum solution for chemically amplified resist patterning in cu/low k dual damascene'20067,042,049'Composite etching stop in semiconductor process integration'20067,015,136'Method for preventing formation of photoresist scum'20066,962,869'SiOCH low k surface protection layer formation by CxHy gas plasma treatment'20056,924,242'SiOC properties and its uniformity in bulk for damascene applications'20056,887,790'Method of forming dummy copper plug to improve low k structure mechanical strength and plug fill uniformity'20056,884,659'Thin interface layer to improve copper etch stop'20056,867,135'Via bottom copper/barrier interface improvement to resolve via electromigration and stress migration'20056,861,754'Semiconductor device with anchor type seal ring'20056,812,043'Method for forming a carbon doped oxide low-k insulating layer'20046,753,260'Composite etching stop in semiconductor process integration'20046,734,079'Microelectronic fabrication having sidewall passivated microelectronic capacitor structure fabricated therein'20046,734,101'Solution to the problem of copper hillocks'20046,677,251'Method for forming a hydrophilic surface on low-k dielectric insulating layers for improved adhesion'20046,667,249'Minimizing coating defects in low dielectric constant films'20036,623,654'Thin interface layer to improve copper etch stop'20036,620,745'Method for forming a blocking layer'20036,602,780'Method for protecting sidewalls of etched openings to prevent via poisoning'20036,518,183'Hillock inhibiting method for forming a passivated copper containing conductor layer'20036,472,312'Methods for inhibiting microelectronic damascene processing induced low dielectric constant dielectric layer physical degradation'20026,455,417'Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer'20026,424,038'Low dielectric constant microelectronic conductor structure with enhanced adhesion and attenuated electrical leakage'20026,407,013'Soft plasma oxidizing plasma method for forming carbon doped silicon containing dielectric layer with enhanced adhesive properties'20026,358,841'Method of copper CMP on low dielectric constant HSQ material'20026,350,694'Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials'20026,248,665'Delamination improvement between Cu and dielectrics for damascene process'20016,181,013'Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby'20016,174,797'Silicon oxide dielectric material with excess silicon as diffusion barrier layer'20016,136,680'Methods to improve copper-fluorinated silica glass interconnects'20006,046,108'Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (103)· patent assignee history
2000–2017Based in Hsinchu, TW· patent location history
2012–2016Patents assigned to BAO TIEN-I (22)· patent assignee history
2012–2015Patents assigned to CHEN HAI-CHING (11)· patent assignee history
2012–2015Patents assigned to YU CHEN-HUA (11)· patent assignee history
2013–2021Based in Dayuan Township, TW· patent location history
2014–2020Based in Taoyuan County, TW· patent location history
2014–2016Based in Dayuan Township, Taoyuan County, TW· patent location history
2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (117)· patent assignee history
2016–2021Based in Taoyuan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 117 | 2015–2021 |
| TAIWAN SEMICONDUCTOR MFG | 103 | 2000–2016 |
| BAO TIEN-Iself | 22 | 2012–2016 |
| CHEN HAI-CHING | 11 | 2012–2015 |
| YU CHEN-HUA | 11 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Dayuan Township, TW | 74 | 2013–2021 |
| Hsinchu, TW | 61 | 2000–2017 |
| Taoyuan, TW | 50 | 2016–2021 |
| Taoyuan County, TW | 24 | 2014–2020 |
| Dayuan Township, Taoyuan County, TW | 8 | 2014–2016 |