Inventor

Syun-Ming Jang

Inventor

Hsinchu, TW

Overview

1996–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 316 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%

H10DInorganic electric semiconductor devices10%

H01LSemiconductor devices7%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

B24BMachines, devices, or processes for grinding or polishing3%

C23CCoating metallic material3%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

C09GPolishing compositions1%

H01JElectric discharge tubes or discharge lamps1%

PatentTitleYear

10,868,139Controlling profiles of replacement gates2020 10,867,807Semiconductor device and method2020 10,859,902Lithography mask and method2020 10,854,729Method to reduce etch variation using ion implantation2020 10,784,375Source/drain recess in a semiconductor device2020 10,756,199Fin field effect transistors having conformal oxide layers and methods of forming same2020 10,699,966Semiconductor device with profiled work-function metal gate electrode and method of making2020 10,692,814Chemical direct pattern plating method2020 10,658,491Controlling profiles of replacement gates2020 10,553,718Semiconductor devices with core-shell structures2020 10,515,955Methods of manufacturing transistor gate structures by local thinning of dummy gate stacks using an etch barrier2019 10,515,788Systems and methods for integrated resputtering in a physical vapor deposition chamber2019 10,510,553Dry ashing by secondary excitation2019 10,490,648Method to reduce etch variation using ion implantation2019 10,481,483Lithography mask and method2019 10,269,921Fin field effect transistors having conformal oxide layers and methods of forming same2019 10,262,944Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components2019 10,163,719Method of forming self-alignment contact2018 10,134,604Semiconductor device and method2018 10,020,397Bottle-neck recess in a semiconductor device2018 10,005,990Cleaning method for semiconductor device fabrication2018 9,953,868Mechanisms of forming damascene interconnect structures2018 9,911,812'Semiconductor device having a fin shell covering a fin core'2018 9,887,072'Systems and methods for integrated resputtering in a physical vapor deposition chamber'2018 9,647,066'Dummy FinFET structure and method of making same'2017 9,601,344'Method of forming pattern for semiconductor device'2017 9,601,333'Etching process'2017 9,590,065'Semiconductor device with metal gate structure comprising work-function metal layer and work-fuction adjustment layer'2017 9,564,398'Chemical direct pattern plating interconnect metallization and metal structure produced by the same'2017 9,520,362'Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components'2016 9,515,188'Fin field effect transistors having conformal oxide layers and methods of forming same'2016 9,461,144'Method for semiconductor device fabrication'2016 9,355,874'Silicon nitride etching in a single wafer apparatus'2016 9,281,196'Method to reduce etch variation using ion implantation'2016 9,269,612'Mechanisms of forming damascene interconnect structures'2016 9,219,036'Interconnect structure for semiconductor devices'2015 9,214,383'Method of semiconductor integrated circuit fabrication'2015 9,214,513'Fin structure and method for forming the same'2015 9,111,884'Finlike structures and methods of making same'2015 9,054,130'Bottle-neck recess in a semiconductor device'2015 9,029,260'Gap filling method for dual damascene process'2015 8,999,842'Interconnect structure for semiconductor devices'2015 8,962,484'Method of forming pattern for semiconductor device'2015 8,932,962'Chemical dispensing system and method'2015 8,889,502'Finlike structures and methods of making same'2014 8,822,331'Anchored damascene structures'2014 8,785,324'Interconnect structure for semiconductor devices'2014 8,759,975'Approach for reducing copper line resistivity'2014 8,735,252'Method of semiconductor integrated circuit fabrication'2014 8,609,484'Method for forming high-K metal gate device'2013 8,368,220'Anchored damascene structures'2013 8,330,275'Interconnect structure for semiconductor devices'2012 8,264,046'Synergy effect of alloying materials in interconnect structures'2012 8,255,843'Method of manufacturing strained-silicon semiconductor device'2012 8,242,016'Approach for reducing copper line resistivity'2012 8,053,356'Interconnect structure for semiconductor devices'2011 8,053,359'Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method'2011 7,977,791'Selective formation of boron-containing metal cap pre-layer'2011 7,968,506'Wet cleaning stripping of etch residue after trench and via opening formation in dual damascene process'2011 7,863,196'Self-aligned dielectric cap'2011 7,834,458'Interconnect structure for semiconductor devices'2010 7,754,571'Method for forming a strained channel in a semiconductor device'2010 7,732,326'Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method'2010 7,670,947'Metal interconnect structure and process for forming same'2010 7,655,556'Interconnect structures for semiconductor devices'2010 7,642,189'Synergy effect of alloying materials in interconnect structures'2010 7,629,690'Dual damascene process without an etch stop layer'2009 7,511,349'Contact or via hole structure with enlarged bottom critical dimension'2009 7,462,561'Contact structure formed using supercritical cleaning fluid and ALCVD'2008 7,456,093'Method for improving a semiconductor device delamination resistance'2008 7,429,769'Recessed channel field effect transistor (FET) device'2008 7,414,315'Damascene structure with high moisture-resistant oxide and method for making the same'2008 7,407,601'Polymeric particle slurry system and method to reduce feature sidewall erosion'2008 7,378,308'CMOS devices with improved gap-filling'2008 7,375,040'Etch stop layer'2008 7,371,629'N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications'2008 7,320,945'Gradient low k material'2008 7,297,632'Scratch reduction for chemical mechanical polishing'2007 7,265,447'Interconnect with composite layers and method for fabricating the same'2007 7,253,524'Copper interconnects'2007 7,250,364'Semiconductor devices with composite etch stop layers and methods of fabrication thereof'2007 7,224,068'Stable metal structure with tungsten plug'2007 7,223,692'Multi-level semiconductor device with capping layer for improved adhesion'2007 7,196,423'Interconnect structure with dielectric barrier and fabrication method thereof'2007 7,193,325'Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects'2007 7,187,084'Damascene method employing composite etch stop layer'2007 7,172,964'Method of preventing photoresist poisoning of a low-dielectric-constant insulator'2007 7,153,197'Method for achieving uniform CU CMP polishing'2006 7,151,315'Method of a non-metal barrier copper damascene integration'2006 7,135,408'Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure'2006 7,118,987'Method of achieving improved STI gap fill with reduced stress'2006 7,118,952'Method of making transistor with strained source/drain'2006 7,109,117'Method for chemical mechanical polishing of a shallow trench isolation structure'2006 7,109,119'Scum solution for chemically amplified resist patterning in cu/low k dual damascene'2006 RE039273'Hard masking method for forming patterned oxygen containing plasma etchable layer'2006 7,056,826'Method of forming copper interconnects'2006 7,042,049'Composite etching stop in semiconductor process integration'2006 7,015,136'Method for preventing formation of photoresist scum'2006 7,002,177'Test region layout for shallow trench isolation'2006 7,001,833'Method for forming openings in low-k dielectric layers'2006 6,974,730'Method for fabricating a recessed channel field effect transistor (FET) device'2005 6,972,253'Method for forming dielectric barrier layer in damascene structure'2005 RE038914'Dual damascene patterned conductor layer formation method without etch stop layer'2005 6,962,869'SiOCH low k surface protection layer formation by CxHy gas plasma treatment'2005 6,958,291'Interconnect with composite barrier layers and method for fabricating the same'2005 6,946,397'Chemical mechanical polishing process with reduced defects in a copper process'2005 6,930,040'Method of forming a contact on a silicon-on-insulator wafer'2005 6,924,242'SiOC properties and its uniformity in bulk for damascene applications'2005 6,924,238'Edge peeling improvement of low-k dielectric materials stack by adjusting EBR resistance'2005 6,919,276'Method to reduce dishing and erosion in a CMP process'2005 6,908,773'ATR-FTIR metal surface cleanliness monitoring'2005 6,895,360'Method to measure oxide thickness by FTIR to improve an in-line CMP endpoint determination'2005 6,884,659'Thin interface layer to improve copper etch stop'2005 6,884,149'Method and system for in-situ monitoring of mixing ratio of high selectivity slurry'2005 6,878,621'Method of fabricating barrierless and embedded copper damascene interconnects'2005 6,869,858'Shallow trench isolation planarized by wet etchback and chemical mechanical polishing'2005 6,867,135'Via bottom copper/barrier interface improvement to resolve via electromigration and stress migration'2005 6,849,549'Method for forming dummy structures for improved CMP and reduced capacitance'2005 6,815,336'Planarization of copper damascene using reverse current electroplating and chemical mechanical polishing'2004 6,812,069'Method for improving semiconductor process wafer CMP uniformity while avoiding fracture'2004 6,812,043'Method for forming a carbon doped oxide low-k insulating layer'2004 6,806,184'Method to eliminate copper hillocks and to reduce copper stress'2004 6,770,570'Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer'2004 6,753,607'Structure for improving interlevel conductor connections'2004 6,753,260'Composite etching stop in semiconductor process integration'2004 6,753,269'Method for low k dielectric deposition'2004 6,753,259'Method of improving the bondability between Au wires and Cu bonding pads'2004 6,740,567'Laminating method for forming integrated circuit microelectronic fabrication'2004 6,736,701'Eliminate broken line damage of copper after CMP'2004 6,734,079'Microelectronic fabrication having sidewall passivated microelectronic capacitor structure fabricated therein'2004 6,734,101'Solution to the problem of copper hillocks'2004 6,734,110'Damascene method employing composite etch stop layer'2004 6,729,935'Method and system for in-situ monitoring of mixing ratio of high selectivity slurry'2004 6,727,172'Process to reduce chemical mechanical polishing damage of narrow copper lines'2004 6,706,577'Formation of dual gate oxide by two-step wet oxidation'2004 6,689,665'Method of forming an STI feature while avoiding or reducing divot formation'2004 6,686,284'Chemical mechanical polisher equipped with chilled retaining ring and method of using'2004 6,677,251'Method for forming a hydrophilic surface on low-k dielectric insulating layers for improved adhesion'2004 6,672,941'Method and apparatus for chemical/mechanical planarization (CMP) of a semiconductor substrate having shallow trench isolation'2004 6,657,284'Graded dielectric layer and method for fabrication thereof'2003 6,654,109'System for detecting surface defects in semiconductor wafers'2003 6,638,328'Bimodal slurry system'2003 6,634,930'Method and apparatus for preventing metal corrosion during chemical mechanical polishing'2003 6,635,211'Reinforced polishing pad for linear chemical mechanical polishing and method for forming'2003 6,623,654'Thin interface layer to improve copper etch stop'2003 6,620,034'Way to remove Cu line damage after Cu CMP'2003 6,620,725'Reduction of Cu line damage by two-step CMP'2003 6,599,847'Sandwich composite dielectric layer yielding improved integrated circuit device reliability'2003 6,589,872'Use of low-high slurry flow to eliminate copper line damages'2003 6,559,040'Process for polishing the top surface of a polysilicon gate'2003 6,544,891'Method to eliminate post-CMP copper flake defect'2003 6,541,382'Lining and corner rounding method for shallow trench isolation'2003 6,524,906'Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer'2003 6,518,183'Hillock inhibiting method for forming a passivated copper containing conductor layer'2003 6,511,887'Method for making FET gate oxides with different thicknesses using a thin silicon nitride layer and a single oxidation step'2003 6,503,818'Delamination resistant multi-layer composite dielectric layer employing low dielectric constant dielectric material'2003 6,500,753'Method to reduce the damages of copper lines'2002 6,495,478'Reduction of shrinkage of poly(arylene ether) for low-K IMD'2002 6,483,173'Solution to black diamond film delamination problem'2002 6,479,385'Interlevel dielectric composite layer for insulation of polysilicon and metal structures'2002 6,472,312'Methods for inhibiting microelectronic damascene processing induced low dielectric constant dielectric layer physical degradation'2002 6,458,689'Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish'2002 6,455,417'Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer'2002 6,444,371'Prevention of die loss to chemical mechanical polishing'2002 6,436,771'Method of forming a semiconductor device with multiple thickness gate dielectric layers'2002 6,429,118'Elimination of electrochemical deposition copper line damage for damascene processing'2002 6,422,929'Polishing pad for a linear polisher and method for forming'2002 6,423,653'Reduction of plasma damage for HDP-CVD PSG process'2002 6,424,038'Low dielectric constant microelectronic conductor structure with enhanced adhesion and attenuated electrical leakage'2002 6,423,625'Method of improving the bondability between Au wires and Cu bonding pads'2002 6,417,106'Underlayer liner for copper damascene in low k dielectric'2002 6,417,071'Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity'2002 6,409,587'Dual-hardness polishing pad for linear polisher and method for fabrication'2002 6,407,013'Soft plasma oxidizing plasma method for forming carbon doped silicon containing dielectric layer with enhanced adhesive properties'2002 6,403,432'Hardmask for a salicide gate process with trench isolation'2002 6,398,627'Slurry dispenser having multiple adjustable nozzles'2002 6,391,792'Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer'2002 6,391,777'Two-stage Cu anneal to improve Cu damascene process'2002 6,387,775'Fabrication of MIM capacitor in copper damascene process'2002 6,383,930'Method to eliminate copper CMP residue of an alignment mark for damascene processes'2002 6,376,377'Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity'2002 6,372,664'Crack resistant multi-layer dielectric layer and method for formation thereof'2002 6,368,952'Diffusion inhibited dielectric structure for diffusion enhanced conductor layer'2002 6,365,523'Integrated high density plasma chemical vapor deposition (HDP-CVD) method and chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layers'2002 6,362,093'Dual damascene method employing sacrificial via fill layer'2002 6,362,085'Method for reducing gate oxide effective thickness and leakage current'2002 6,358,841'Method of copper CMP on low dielectric constant HSQ material'2002 6,358,119'Way to remove CU line damage after CU CMP'2002 6,358,839'Solution to black diamond film delamination problem'2002 6,350,364'Method for improvement of planarity of electroplated copper'2002 6,350,693'Method of CMP of polysilicon'2002 6,350,694'Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials'2002 6,346,476'Method for enhancing line-to-line capacitance uniformity of plasma enhanced chemical vapor deposited (PECVD) inter-metal dielectric (IMD) layers'2002 6,329,717'Integrated circuit having selectivity deposited silicon oxide spacer layer formed therein'2001 6,319,809'Method to reduce via poison in low-k Cu dual damascene by UV-treatment'2001 6,319,784'Using high temperature H2 anneal to recrystallize S/D and remove native oxide simultaneously'2001 6,316,348'High selectivity Si-rich SiON etch-stop layer'2001 6,297,162'Method to reduce silicon oxynitride etch rate in a silicon oxide dry etch'2001 6,277,745'Passivation method of post copper dry etching'2001 6,274,483'Method to improve metal line adhesion by trench corner shape modification'2001 6,274,514'HDP-CVD method for forming passivation layers with enhanced adhesion'2001 6,271,123'Chemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG'2001 6,271,138'Chemical mechanical polish (CMP) planarizing method with enhanced chemical mechanical polish (CMP) planarized layer planarity'2001 6,268,294'Method of protecting a low-K dielectric material'2001 6,265,319'Dual damascene method employing spin-on polymer (SOP) etch stop layer'2001 6,261,957'Self-planarized gap-filling by HDPCVD for shallow trench isolation'2001 6,255,207'Composite planarizing dielectric layer employing high density plasma chemical vapor deposited (HDP-CVD) underlayer'2001 6,255,232'Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer'2001 6,248,665'Delamination improvement between Cu and dielectrics for damascene process'2001 6,245,691'Ozone-teos method for forming with attenuated surface sensitivity a silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer'2001 6,245,682'Removal of SiON ARC film after poly photo and etch'2001 6,245,669'High selectivity Si-rich SiON etch-stop layer'2001 6,242,356'Etchback method for forming microelectronic layer with enhanced surface smoothness'2001 6,239,023'Method to reduce the damages of copper lines'2001 6,239,002'Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer'2001 6,235,633'Method for making tungsten metal plugs in a polymer low-K intermetal dielectric layer using an improved two-step chemical/mechanical polishing process'2001 6,228,760'Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish'2001 6,228,780'Non-shrinkable passivation scheme for metal em improvement'2001 6,225,171'Shallow trench isolation process for reduced for junction leakage'2001 6,211,098'Wet oxidation method for forming silicon oxide dielectric layer'2001 6,207,483'Method for smoothing polysilicon gate structures in CMOS devices'2001 6,204,205'Using H2anneal to improve the electrical characteristics of gate oxide'2001 6,200,875'Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer'2001 6,197,706'Low temperature method to form low k dielectric'2001 6,197,669'Reduction of surface defects on amorphous silicon grown by a low-temperature, high pressure LPCVD process'2001 6,197,660'Integration of CMP and wet or dry etching for STI'2001 6,197,658'Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity'2001 6,194,287'Shallow trench isolation (STI) method with reproducible alignment registration'2001 6,194,307'Elimination of copper line damages for damascene process'2001 6,191,039'Method of CMP of polysilicon'2001 6,187,663'Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials'2001 6,184,155'Method for forming a ultra-thin gate insulator layer'2001 6,180,540'Method for forming a stabilized fluorosilicate glass layer'2001 6,180,543'Method of generating two nitrogen concentration peak profiles in gate oxide'2001 6,181,013'Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby'2001 6,176,141'Method for stud pull test for film formed on semiconductor device'2001 6,174,808'Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS'2001 6,174,800'Via formation in a poly(arylene ether) inter metal dielectric layer'2001 6,174,797'Silicon oxide dielectric material with excess silicon as diffusion barrier layer'2001 6,171,896'Method of forming shallow trench isolation by HDPCVD oxide'2001 6,165,898'Dual damascene patterned conductor layer formation method without etch stop layer'2000 6,165,897'Void forming method for fabricating low dielectric constant dielectric layer'2000 6,165,052'Method and apparatus for chemical/mechanical planarization (CMP) of a semiconductor substrate having shallow trench isolation'2000 6,165,915'Forming halogen doped glass dielectric layer with enhanced stability'2000 6,153,512'Process to improve adhesion of HSQ to underlying materials'2000 6,143,673'Method for forming gap filling silicon oxide intermetal dielectric (IMD) layer formed employing ozone-tEOS'2000 6,143,670'Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer'2000 6,136,679'Gate micro-patterning process'2000 6,136,680'Methods to improve copper-fluorinated silica glass interconnects'2000 6,121,111'Method of removing tungsten near the wafer edge after CMP'2000 6,114,253'Via patterning for poly(arylene ether) used as an inter-metal dielectric'2000 6,110,648'Method of enclosing copper conductor in a dual damascene process'2000 6,100,163'Gap filling of shallow trench isolation by ozone-tetraethoxysilane'2000 6,096,649'Top metal and passivation procedures for copper damascene structures'2000 6,093,593'Method of forming a gate which provides a reduced corner recess in adjacent shallow trench isolation'2000 6,090,714'Chemical mechanical polish (CMP) planarizing trench fill method employing composite trench fill layer'2000 6,090,696'Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures'2000 6,080,656'Method for forming a self-aligned copper structure with improved planarity'2000 6,080,635'Method of photo alignment for shallow trench isolation with chemical mechanical polishing'2000 6,071,814'Selective electroplating of copper for damascene process'2000 6,072,237'Borderless contact structure'2000 6,051,496'Use of stop layer for chemical mechanical polishing of CU damascene'2000 6,049,137'Readable alignment mark structure formed using enhanced chemical mechanical polishing'2000 6,046,108'Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby'2000 6,043,133'Method of photo alignment for shallow trench isolation chemical-mechanical polishing'2000 6,043,152'Method to reduce metal damage in the HDP-CVD process by using a sacrificial dielectric film'2000 6,043,136'Trench filling method employing oxygen densified gap filling CVD silicon oxide layer'2000 6,037,018'Shallow trench isolation filled by high density plasma chemical vapor deposition'2000 6,037,236'Regeneration of alignment marks after shallow trench isolation with chemical mechanical polishing'2000 6,027,861'VLSIC patterning process'2000 6,022,802'Low dielectric constant intermetal dielectric (IMD) by formation of air gap between metal lines'2000 6,019,906'Hard masking method for forming patterned oxygen containing plasma etchable layer'2000 6,020,249'Method for photo alignment after CMP planarization'2000 6,010,948'Shallow trench isolation process employing a BPSG trench fill'2000 6,007,733'Hard masking method for forming oxygen containing plasma etchable layer'1999 6,004,863'Non-polishing sacrificial layer etchback planarizing method for forming a planarized aperture fill layer'1999 6,004,873'Method for reducing the pattern sensitivity of ozone assisted chemical vapor deposited (CVD) silicon oxide insulator layers'1999 6,004,883'Dual damascene patterned conductor layer formation method without etch stop layer'1999 5,972,798'Prevention of die loss to chemical mechanical polishing'1999 5,968,687'Mask for recovering alignment marks after chemical mechanical polishing'1999 5,958,800'Method for post planarization metal photolithography'1999 5,955,787'Method for forming intermetal dielectric with SOG etchback and CMP'1999 5,926,722'Planarization of shallow trench isolation by differential etchback and chemical mechanical polishing'1999 5,923,996'Method to protect alignment mark in CMP process'1999 5,904,573'PE-TEOS process'1999 5,871,886'Sandwiched middle antireflection coating (SMARC) process'1999 5,872,042'Method for alignment mark regeneration'1999 5,869,384'Trench filling method employing silicon liner layer and gap filling silicon oxide trench fill layer'1999 5,858,588'Method for recovering alignment marks after chemical mechanical polishing'1999 5,858,623'Method for attenuating photoresist layer outgassing'1999 5,840,624'Reduction of via over etching for borderless contacts'1998 5,817,567'Shallow trench isolation method'1998 5,817,566'Trench filling method employing oxygen densified gap filling silicon oxide layer formed with low ozone concentration'1998 5,817,571'Multilayer interlevel dielectrics using phosphorus-doped glass'1998 5,811,345'Planarization of shallow- trench- isolation without chemical mechanical polishing'1998 5,804,498'Method of making an underlayer to reduce pattern sensitivity of ozone-TEOS'1998 5,786,262'Self-planarized gapfilling for shallow trench isolation'1998 5,786,260'Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing'1998 5,773,360'Reduction of surface contamination in post-CMP cleaning'1998 5,747,380'Robust end-point detection for contact and via etching'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (275)· patent assignee history

1996–2020Based in Hsinchu, TW· patent location history

1997Based in Hsin Chu, TW· patent location history

2008–2017Patents assigned to JANG SYUN-MING (17)· patent assignee history

2012–2015Patents assigned to TSAI MINGHSING (4)· patent assignee history

2014–2016Patents assigned to CHEN CHAO-CHENG (4)· patent assignee history

2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (33)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG	275	1996–2016
TAIWAN SEMICONDUCTOR MFG CO LTD	33	2016–2020
JANG SYUN-MINGself	17	2008–2017
CHEN CHAO-CHENG	4	2014–2016
TSAI MINGHSING	4	2012–2015

Locations

Location	Patents	Span
Hsinchu, TW	315	1996–2020
Hsin Chu, TW	1	1997