USPatent applicationPatented

UV-enhanced oxy-nitridation of semiconductor substrates

Granted 16 Mar 2004 · 1 office action

Assignee: Mattson Technology

Law firm: Law firm · Log in to unlock

Attorney: Attorney · Log in to unlock

Inventors: Sing-Pin Tay, Yao Zhi Hu · Examiner: Alexander Ghyka · AU 2812 · TC 2800

Life of the application

10 dated events
⤢ drag to zoom20022004200620082010201220142016201820202022ProsecutionOwnershipTerm & fees
ProsecutionOwnershipTerm & feeshover for detail · click to open

Abstract

The oxynitride or oxide layer is formed on a semiconductor substrate by subjecting the substrate to UV radiation while exposed to a gaseous atmosphere of O2 and one or more of N2, N2O, H2 and NH3. Thereafter, a silicon nitride layer is formed according to known 4-step gate stack dielectric processing techniques. Alternatively, a 3-step gate stack process is used, namely following UV-oxidation, a further UV-radiation in NH3 may be applied, followed by a rapid thermal anneal process in an inert ambient. By using UV-oxidation as the first step in either a 4-step or 3-step gate stack process, very thin composite dielectric films with equivalent oxide thickness (EOT) below 16 and as low as 14.2 can be obtained with significant improvement in leakage current density.

Description

6 parts
›FIELD OF THE INVENTION

The present invention relates generally to processes for forming ultra-thin dielectric films for ULSI applications. The processes have particular advantage when used for forming oxynitride films on silicon semiconductor substrates with chemical vapor deposition (CVD) techniques.

›BACKGROUND OF THE INVENTION

The current trend in integrated circuits is to use ultra thin dielectric layers when fabricating metal-oxide-semiconductors (MOS). A gate oxide layer is typically formed by thermal oxidation of a silicon semiconductor substrate in a substantially pure oxygen atmosphere. In ultra large scale integrated (ULSI) circuits, however, such gate oxide layers in the metal oxide semiconductor field effect transistor (MOSFET) can exhibit undesirable characteristics, such as relatively high defect densities and charge trapping, and relatively low reliability and low resistance to hot carrier effects. Composite oxide-nitride dielectrics have been experimented with in order to achieve very thin dielectric films with the required equivalent oxide thickness (EOT), as well as all the other qualities required to meet performance specifications. While higher nitrogen content in the oxynitride can be advantageous, it may also degrade the mobility of the transistors.

Once the semiconductor substrate surface has been cleaned, it is subjected to a series of rapid thermal heating processes (RTP) to form the multi-layer gate stack. Those processes often consist of: (1) growing an oxynitride layer with nitric oxide (NO); (2) depositing a silicon nitride (SiN x ) layer with a rapid thermal chemical vapor deposition (RTCVD) process; (3) rapid thermal annealing the substrate with the SiN x layer in an ammonia (NH 3 ) environment; and (4) rapid thermal annealing the substrate in an N 2 O environment. These four steps generally are considered standard in a 4-step gate stack dielectric growth.

The first step is the most critical. The goals of the oxynitride layer growth step are as follows: to achieve very thin EOT of the gate stack dielectric film; to grow an oxynitride layer with appropriate nitrogen content; to grow an oxynitride layer that allows good quality growth of silicon nitride applied on the oxynitride layer; and to obtain high mobility for transistors.

Most commonly, the oxynitride film is formed with a rapid thermal NO or O 2 oxidation in which the substrate is heated rapidly in an atmosphere of NO or O 2 gases for a controlled, generally short, time. When such rapid thermal NO or O 2 oxidation is the first step in the 4-step gate stack dielectric growth process, the EOT of dielectric films ultimately formed on the semiconductor are almost always higher than 16 angstrom (Å). In the trend for producing thinner and thinner gate stack dielectrics, thinner oxynitride layers with still good performance are required. Unfortunately, the resultant dielectric films deteriorate rapidly, i.e. the leakage current density increases dramatically, when the EOT of the oxynitride is less than 16 Å.

The surface roughness of a CVD silicon nitride film deposited on a silicon dioxide layer has been found undesirably high (i.e., root mean square (RMS) roughness of about 10 Å and even up to 20 Å) when the physical thickness of the nitride layer is about 25 Å and below. Published research papers have indicated that the coalescence of nitride nucleation islands does not take place until the silicon nitride film physical thickness exceeds about 20 Å. See H. Resinger and A. Spitzer, “Electrical Breakdown Induced by Silicon Nitride Roughness in Thin Oxide-Nitride-Oxide Films,” J. Appl. Phys ., V. 79, p. 3028 (1996); M. Copel, et. al., “Nucleation of Chemical Vapor Deposited Silicon Nitride on Silicon Dioxide,” Appl. Phys. Lett ., V. 74, p. 1830 (1999); and Y. Hu, et al., “An In-Situ Real Time Measurement of the Incubation Time for Si Nucleation on SiO 2 in a Rapid Thermal Process,” Appl. Phys. Lett ., V. 66, p. 700 (1995). Thus, because the growth of silicon nitride films on oxide layers appears to be dependent upon having sufficient nucleation sites, thinner nitride films have had unacceptable surface roughness leading to unacceptable gate dielectric characteristics.

More recently, some studies showed that remote plasma oxidation may improve the ultra-thin oxide interface. See Lucovsky, et al., Appl. Phys. Lett ., V. 74, p. 2005 (1999). Unfortunately, remote plasma oxidation requires special processing equipment and is complicated to use. Alternative approaches to create more nucleation sites and reduce surface roughness of the thin silicon nitride films are still being sought. In addition, alternative approaches to create dielectric films with lower EOT and less leakage current density are still being sought.

›SUMMARY OF THE INVENTION

According to the invention, an oxynitride layer is formed on a semiconductor substrate using UV-oxidation as the first step in the 4-step gate stack dielectric growth process. In contrast to the prior art rapid thermal NO or O 2 oxidation, in our process, the semiconductor substrate surface is simultaneously exposed to UV radiation and a gaseous atmosphere containing O 2 and one or more gases selected from N 2 , NH 3 , N 2 O and H 2 . Preferably, the semiconductor substrate is silicon. Preferably, the oxynitride layer is formed on the substrate surface by exposing the substrate surface both to (1) UV radiation (from about 50% to 100% power of a maximum power of 200 Watt, preferably 70% power) and (2) the gaseous atmosphere for about 30 to 90 seconds (preferably 60 seconds), at a temperature of about 100 to 150° C. (preferably 130° C.) and at a pressure of about 80 to 120 Torr (preferably 100 Torr). Preferably, the O 2 gas is introduced at a flow rate of about 100 to 500 SCCM (Standard Cubic Centimeters per Minute), and the N 2 , NH 3 , N 2 O and/or H 2 gas is introduced at a flow rate of about 2,000 to 3,000 SCCM, with the O 2 gas comprising less than about 20% of the mixture in the gaseous atmosphere. Most preferably, the gaseous atmosphere consists of O 2 and N 2 gases, with the O 2 gas about 2 to 12% of the mixture in the gaseous atmosphere.

After the oxynitride layer is applied by UV-oxidation according to the invention, the remaining steps of the known 4-step gate stack process are carried out. A silicon nitride layer is applied onto the oxynitride layer, frequently using chemical vapor deposition. The substrate with SiN x layer is annealed in the presence of a NH 3 atmosphere and then further annealed in the presence of a N 2 O atmosphere.

In an alternate preferred embodiment, the semiconductor substrate surface is simultaneously exposed to UV radiation and a gaseous atmosphere containing O 2 and one or more gases selected from N 2 , NH 3 , N 2 O and H 2 . After an oxynitride layer is formed, the semiconductor substrate is exposed to UV radiation and a gaseous atmosphere containing NH 3 . The NH 3 is introduced at a flow rate of about 0.2 to 1.0 SLPM (Standard Liters Per Minute), at a temperature in the range of about 100 to 200° C. (preferably 150° C.) and at a pressure in the range of about 10 to 200 Torr (preferably 100 Torr). UV radiation is applied at a power setting of about 50% to 100% power of a maximum power of 200 Watt (preferably 70% power) for about 2 to 30 seconds. The substrate is then annealed using a rapid thermal process in inert ambient (preferably N 2 at a flow rate of 0.5 to 2 SLPM) at a temperature in the range of about 800 to 1000° C. and for a time of about 30 to 60 seconds.

We have found that by using UV-oxidation as the first step in the 4-step (e.g., FIG. 1) gate stack dielectric growth process, one can obtain composite dielectric films with EOT values below 16 Angstrom (Å), and as low as 14.2 Å. The associated leakage current densities of the resulting dielectric films are also very low, on the order of 1.0E-01 A/cm 2 . This is more than one order of magnitude lower than that extrapolated from the prior art (solid line in FIG. 3 ).

The ITRS (International Technology Roadmap for Semiconductors) specifications demand that, for the 100 nm technology node the gate dielectric EOT shall be 10 Å thick with leakage current density less than 1.0 A/cm 2 . It is expected that the 3-step process (e.g., FIG. 2) will yield the same or better quality dielectric. The process thus improves the quality of the dielectric films formed on the semiconductor substrate surface.

›BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic flow chart of a 4-step gate stack dielectric growth process according to a first embodiment of the invention;

FIG. 2 is a schematic flow chart of a 3-step gate stack dielectric growth process according to an alternate embodiment of the invention; and

FIG. 3 is a graph comparing leakage current density with equivalent oxide thickness (EOT) for the gate stack dielectric films formed (i) when UV-oxidation is used to apply the oxynitride layer and (ii) when conventional rapid thermal processing is used to apply the oxynitride layer.

›DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS · 1 of 2

FIG. 1 depicts in schematic form the process according to the invention. In one embodiment of the process 10 , the first step 12 of 4-step gate stack processing comprises oxynitride formation with UV-oxidation. The second step 14 comprises depositing a silicon nitride layer over the oxynitride layer using a rapid thermal chemical vapor deposition (CVD) process. The third step 16 comprises annealing the semiconductor substrate while the substrate is exposed to a gaseous atmosphere of NH 3 . The fourth step 18 comprises further annealing the semiconductor substrate while the substrate is exposed to a gaseous atmosphere of N 2 O.

According to the invention, a semiconductor substrate (preferably a silicon semiconductor substrate) is simultaneously exposed to UV radiation and a gaseous atmosphere containing O 2 and one or more gases selected from N 2 , NH 3 , N 2 O and H 2 , in order to oxidize the silicon surface. The oxynitride thickness is estimated to be ordinarily about 6 Å based on analysis of ellipsometric and electrical data of the final gate stack. In the preferred embodiment, UV radiation is emitted from an external Xenon lamp with a broad wavelength (200-1100 nm) output. Preferably, the photon energies from such Xenon lamp are 6.2-1.1 eV, which are higher than most bond energies for semiconductor substrates, such as: Si—Si=3.1 eV; Si—H=3.0 eV; Si—Cl=3.9 eV; Si—N=4.0 eV; Si—O=4.6 eV. These bonds can be dissociated under UV radiation, but they should not be ionized because their ionization potentials far exceed 10 eV.

The preferred process includes the following steps:

(1) optionally dry clean the surface of the semiconductor substrate, preferably a silicon semiconductor substrate, with UV-excited ozone to remove organic residues, then apply an HF-methanol vapor treatment to remove any grown oxide, and then use UV-excited chlorine to remove metallic contaminants;

(2) expose the semiconductor substrate surface, for about 30 to 90 seconds, most preferably 60 seconds, to gaseous O 2 at a flow rate of about 100 to 500 SCCM mixed with one or more gases selected from N 2 , NH 3 , N 2 O and H 2 at a flow rate of about 2,000 to 3,000 SCCM. The O 2 gas should be less than 20% mixture in the gaseous atmosphere. Most preferably, the gaseous mixture is O 2 and N 2 , with the O 2 comprising about 2 to 12% mixture in the gaseous atmosphere. UV radiation preferably is applied at a power setting of about 50 to 100% of a maximum power of 200 Watt, most preferably 70%, at a pressure of about 80 to 120 Torr, most preferably 100 Torr. The temperature in the atmosphere should be about 100 to 150° C., most preferably 130° C., to thermally grow an oxynitride layer;

(3) deposit a film of silicon nitride over the oxynitride layer using a chemical vapor deposition (CVD) process;

(4) anneal the substrate in the presence of a NH 3 atmosphere; and

(5) further anneal the substrate in the presence of a N 2 O atmosphere.

FIG. 2 depicts in schematic form an alternate process according to the invention. In this alternate embodiment 20 the first step 22 of the gate stack processing comprises oxynitride formation with UV-oxidation. The second step 24 comprises exposing the semiconductor substrate to UV radiation and a gaseous atmosphere of NH 3 . The third step 26 comprises annealing the semiconductor substrate using rapid thermal processing (RTP) in an inert ambient, e.g., N 2 gas.

The alternate preferred process includes the following steps:

(1) optionally dry clean the surface of the semiconductor substrate, preferably a silicon semiconductor substrate, with UV-excited ozone to remove organic residues, then apply an HF-methanol vapor treatment to remove any grown oxide, and then use UV-excited chlorine to remove metallic contaminants;

(2) expose the semiconductor substrate surface, for about 30 to 90 seconds, most preferably for 60 seconds, to gaseous O 2 at a flow rate of about 100 to 500 SCCM mixed with one or more gases selected from N 2 , NH 3 , N 2 O and H 2 at a flow rate of about 2,000 to 3,000 SCCM. The O 2 should be less than 20% of the gas mixture in the gaseous atmosphere. Most preferably, the gaseous mixture is O 2 and N 2 , with the O 2 comprising about 5 to 12% of the mixture. UV radiation is applied at a power setting of about 50 to 100% of a maximum power of 200 Watt, most preferably 70%. The atmosphere is maintained at a pressure of about 80 to 120 Torr, most preferably 100 Torr, and at a temperature of about 100 to 150° C., most preferably 130° C., to thermally grow an oxynitride layer;

(3) expose the semiconductor substrate surface, for about 2 to 30 seconds, to gaseous NH 3 at a flow rate of about 0.2 to 1.0 SLPM and UV radiation at a power setting of about 50 to 100% of a maximum power of 200 Watt, most preferably 70%, at a pressure of about 10 to 200 Torr, most preferably 100 Torr, and at a temperature of about 100 to 200° C., preferably 150° C.;

(4) anneal the semiconductor substrate for about 30 to 60 seconds, using a rapid thermal process (RTP) in inert ambient, most preferably N 2 gas, where annealing is carried out at a temperature of about 800 to 1000° C.

With this process, dielectric films formed on the semiconductor substrate have substantially improved quality. Composite dielectric films with EOT values below 16 Å, and even as a low as 14.2 Å, are obtained. The associated leakage current densities of the resulting dielectric films are also very low, on the order of 1.0E-01 A/cm 2 . The process according to the invention has been found to reduce the surface roughness of the resultant nitride films, thus improving the gate dielectric characteristics of such films.

Experiments were conducted to compare the processes according to the invention with known processes. The results of these experiments are shown below in Table I.

Examples 1, 2 and 3 were carried out according to the invention. In Example 1, after pre-cleaning the semiconductor substrate surface with a wet process of RCA and an HF dip a treatment, a gaseous mixture was introduced to begin the gate stack processing. The O 2 gas stream was introduced for 60 seconds at a temperature of 150° C. and pressure of 100 Torr at a rate of 1000 SCCM. A film of silicon nitride was then deposited over the oxynitride layer using a chemical vapor deposition (CVD) process at a temperature of 750° C. and pressure of 1.5 Torr for 25 seconds. The substrate was then annealed in an NH 3 atmosphere, the NH 3 gas stream introduced for 30 seconds at a temperature of 900° C. and a pressure of 450 Torr at a rate of 5.5 s1m. Finally, the substrate was annealed in a N 2 O atmosphere; the N 2 O gas stream was introduced for 30 seconds at a temperature of 800° C. and pressure of 450 Torr at a rate of 8 slm. UV radiation emitted from a Xenon lamp was applied for 10 seconds at a power setting of 70% (maximum power 200 Watt) to thermally grow an oxide layer on the semiconductor substrate surface as the surface was exposed to the O 2 atmosphere. The resulting EOT was determined by capacitance measurement (a C-V measurement technique known to persons of skill in the art) to be 15.79 Å (mean). Other parameters for Example 1 are set forth in Table I.

›DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS · 2 of 2

Examples 2 and 3 were carried out similarly to Example 1, except that in Examples 2 and 3, the O 2 was introduced as a mixture with N 2 to grow the oxide layer. In Example 2, such mixture was introduced at 150° C. and at a pressure of 100 Torr at a rate of 100 SCCM O 2 to 5000 SCCM N 2 . In Example 3, such mixture was introduced at 150° C. and at a pressure of 100 Torr at a rate of 200 SCCM O 2 to 3200 SCCM N 2 . The EOT for Example 3 was 14.2 Å and for Example 2 was 15.37 Å.

FIG. 3 shows graphically the results from the representative Examples reported in Table I. In FIG. 3, leakage current density (in A/cm 2 ) is plotted against EOT (in Å) of the dielectric films in which the oxynitride layers are formed by (i) RT-NO oxidation and (ii) the novel UV-oxidation process. It is clear that UV-oxidation as the first step in the 4-step gate stack process produces dielectric films that have both lower EOT values (as low as 14.2 Å) and lower leakage current densities than dielectric films formed by using RT-NO oxidation as the first step in the 4-step gate stack process. The experimental results also show the excellent uniformity of the dielectric films formed by using the novel UV-oxidation process as the first step in the 4-step gate stack process.

The foregoing description of the invention illustrates and describes the preferred embodiments. Nevertheless, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments, and is capable of changes or modifications within the scope of the inventive concept that has been expressed herein. The description is not intended to limit the invention to the form disclosed here. Alternate embodiments apparent to those skilled in the art are to be included within the scope of the appended claims.

›Tables in the description — 1
TABLE I
O2O2/N2O2/N2NONH3NH3NH3NH3
(150°0 C.,(150° C.,(150° C.,(800° C.,SiNSiN(900° C.,(900° C.,(900° C.,(900° C.,
100T,100T, 200100T, 100100T,(750° C.,(800° C.,50T,150T,350T,450T,
1000 SCCM,SCCM O2/3200SCCM O2/50002 slm,1.5T,1.5T,10 slm,10 slm,10 slm,10 slm,
Example60s)SCCM N2, 60s)SCCM N2, 60s)10s)25s)25s)30s)30s)30s)30s)
1xx
2xx
3xx
C1xxx
C2xxx
C3xxx
C4xxx
C5xxx
C6xxx
C7xxx
C8xxx
C9xxx
C10xxx
C11xxx
C12xxx
C13xxx
C14xxx
C15xxx
C16xxx
C17xxx
C18xxxx
C19xxxx
C20xxxx
C21xxxx
C22xxx
C23xxx
C24xxx
C25xxx
C26xxx
C27xxx
C28xxx
C29xx
C30xx
C31xx
C32xxx
C33xxx
C34xxx
NH3N2ON2ON2O
(900° C.,(800° C.,(800° C.,(800° C.,
450T,50T,450T,450T,EOTC
5.5 slm,18 slm,18 slm,8 slm,Vfbhysteresis(Å)(pF) @Jg(A/cm2) @
Example30s)30s)30s)30s)(V)(mV)mean−2.5 VVg = −1.5 V
1xx−1.1212.215.891.8.084O2 as first oxide
2xx−1.0811.315.493.5.088O2/N2 as first oxide
3xx−1.119.414.299.8.083O2/N2 as first oxide
C1x−1.096.816.886.5.021standard
C2x−1.096.017.185.2.017standard
C3x−1.0611.716.490.2.130standard/fast ramp
C4x−1.0611.216.689.2.130standard/fast ramp
C5x−1.0510.916.291.5.170P2(NO + CVD + NH3) −
P3(N2O)
C6x−1.0410.816.887.9.152P2(NO + CVD + NH3) −
P3(N2O)
C7x−1.0410.516.888.1.158P2(NO + CVD + NH3) −
P3(N2O)
C8x−1.048.217.087.2.116P2(NO + CVD + NH3) −
P3(N2O)
C9x−1.025.916.289.7.068P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C10x−1.057.416.389.7.076P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C11x−1.068.816.489.3.066P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C12x−1.067.916.389.5.061P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C13x−1.078.316.588.8.054P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C14x−1.0613.317.685.1.054P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C15x−1.059.017.286.7.109P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C16x−1.0713.017.585.5.142P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C17x−1.635.917.585.4.092P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C18−1.0524.018.184.2.267P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C19−1.0922.016.790.8.346P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C20−1.2325.016.992.4.001P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C21−1.2516.316.793.0.001P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C22x−1.077.717.583.6.034P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C23x−1.0412.517.286.9.139P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C24x−1.0414.116.690.0.234P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C25x−1.0413.916.988.1.208P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C26x−1.0416.816.989.5.317P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C27x−1.0315.417.287.8.286P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C28x−1.3119.216.097.4.808P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C29xx−0.0910.015.993.0.109P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C30xx−1.0116.816.491.2.113P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C31xx−0.9713.415.992.3.145P3(NO)—P2(CVD) −
P3(NH3 + N2O)
C32x−0.975.916.289.8.044P2(NO + CVD) +
P3(NH3 + N2O)
C33x−0.9811.216.589.0.052P2(NO + CVD) +
P3(NH3 + N2O)
C34x−0.909.816.688.1.043P2(NO + CVD) +
P3(NH3 + N2O)

Claims as granted

17 claims

Log in to read the claims of this application.

Log in to unlock

Classifications

8 codes
IPC · International Patent Classification
Section H — Electricity
  • H01L29/78
  • H01L29/51
  • H10P14/69
  • H10P14/694
  • H10P34/42
USPC · US Patent Classification
438/771438/770438/287

Claim changes

Soon
Coming soonHow the claims changed between publication and grant

See which claims were amended, added or cancelled during examination, with every added and removed word marked.

AmendedAddedCancelledUnchanged

The published claims of this application are not paired with the granted ones in what we hold.

File wrapper

⤢ drag to zoomJan 2002Apr 2002Jul 2002Oct 2002Jan 2003Apr 2003Jul 2003Oct 2003Jan 2004Apr 2004USPTOApplicantNon-final rejectionResponse after non-finalRequest for continued examinationNotice of allowance
USPTOApplicanthover for detail · click to open
Pendency
2.2 y
798 days filing → grant
Office actions
1
non-final + final
Responses
2
1 RCE
Examiner
Alexander Ghyka
art unit 2812 · TC 2800
Citations: 27 back · 5 forward

See the full prosecution history — every USPTO and applicant action on this file, in order.

Log in to unlock

Documents

Log in to open the documents of this file: the application as filed, every office action and response, the notice of allowance.

Log in to unlock

Chain of title

⤢ drag to zoom20022004200620082010201220142016201820202022Owner 1
Titlehover for detail · click to open

See the full assignment history — every owner this patent has passed through, with recordation dates and reel/frame numbers.

Log in to unlock