Inventor
Jason R. Wright
Inventor
Chandler, AZ, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H01LSemiconductor devices21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
C23CCoating metallic material9%
Y10TTechnical subjects covered by former us classification6%
H10DInorganic electric semiconductor devices4%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
H05KPrinted circuits3%
H10NElectric solid-state devices not otherwise provided for3%
B24BMachines, devices, or processes for grinding or polishing1%
PatentTitleYear
10,727,195Bond materials with enhanced plasma resistant characteristics and associated methods202010,340,251Method for making an electronic component package20199,899,298'Microelectronic packages having mold-embedded traces and methods for the production thereof'20189,761,570'Electronic component package with multple electronic components'20179,502,363'Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers'20169,331,029'Microelectronic packages having mold-embedded traces and methods for the production thereof'20169,305,911'Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication'20169,299,670'Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof'20169,281,293'Microelectronic packages having layered interconnect structures and methods for the manufacture thereof'20169,257,415'Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof'20169,190,390'Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof'20159,159,702'Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof'20159,142,502'Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits'20159,093,457'Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof'20159,064,977'Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof'20159,040,387'Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof'20159,025,340'Devices and stacked microelectronic packages with in-trench package surface conductors and methods of their fabrication'20158,925,481'Systems and methods for measuring, monitoring and controlling ozone concentration'20158,906,790'Combinatorial approach for screening of ALD film stacks'20148,900,364'High productivity vapor processing system'20148,851,010'Systems and methods for measuring, monitoring and controlling ozone concentration'20148,733,280'Showerhead for processing chamber'20148,609,519'Combinatorial approach for screening of ALD film stacks'20138,592,241'Method for packaging an electronic device assembly having a capped device interconnect'20138,216,918'Method of forming a packaged semiconductor device'20127,892,950'Methodology for processing a panel during semiconductor device fabrication'20117,845,308'Systems incorporating microwave heaters within fluid supply lines of substrate processing chambers and methods for use of such systems'20106,832,950'Polishing pad with window'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2010Based in Sunnyvale, CA, US· patent location history
2011–2018Patents assigned to FREESCALE SEMICONDUCTOR INC (15)· patent assignee history
2011–2019Based in Chandler, AZ, US· patent location history
2012–2016Patents assigned to WRIGHT JASON R (13)· patent assignee history
2012–2016Patents assigned to HAYES SCOTT M (9)· patent assignee history
2012–2016Patents assigned to GONG ZHIWEI (7)· patent assignee history
2013–2015Based in Saratoga, CA, US· patent location history
2015–2016Patents assigned to VINCENT MICHAEL B (10)· patent assignee history
2017Based in Austin, TX, US· patent location history
2020Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FREESCALE SEMICONDUCTOR INC | 15 | 2011–2018 |
| WRIGHT JASON Rself | 13 | 2012–2016 |
| VINCENT MICHAEL B | 10 | 2015–2016 |
| HAYES SCOTT M | 9 | 2012–2016 |
| GONG ZHIWEI | 7 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chandler, AZ, US | 18 | 2011–2019 |
| Saratoga, California, US | 6 | 2013–2015 |
| Sunnyvale, California, US | 2 | 2004–2010 |
| Santa Clara, California, US | 1 | 2020 |
| Austin, Texas, US | 1 | 2017 |