Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof

A method for fabricating stacked microelectronic packages, comprising:narranging microelectronic device panels in a panel stack, each microelectronic device panel comprising a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom;forming trenches in the panel stack, the trenches having sidewalls through which the plurality of package edge conductors are exposed;dispensing a metal-containing epoxy into the trenches in sufficient quantity to substantially fill the trenches and yield a plurality of epoxy-filled trenchesseparating the panel stack into partially-completed stacked microelectronic packages to produce unpatterned metal-containing epoxy layers contacting the plurality of package edge conductors, the panel stack separated along saw lanes extending through the epoxy-filled trenches to impart the unpatterned metal-containing epoxy layers with exposed sidewall surfaces; andpatterning the unpatterned metal-containing epoxy layers to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic packages, wherein selected portions of the unpatterned metal-containing epoxy layers are removed at the exposed sidewall surfaces during patterning.

A method for fabricating a stacked microelectronic package, comprising:nobtaining a partially-completed stacked microelectronic package having at least upper and lower package layers, the upper and lower package layers each comprising:na package body;a microelectronic device embedded in the package body; andone or more dielectric layers overlying the package body and the microelectronic device; anda plurality of package edge conductors formed in the one or more dielectric layers and extending from the microelectronic device to a sidewall of the stacked microelectronic package, the plurality of package edge conductors exposed through the sidewall of the stacked microelectronic package;producing an unpatterned metal-containing epoxy layer contacting the plurality of package edge conductors by dispensing a metal-containing epoxy over the sidewall of the package body, curing the metal-containing epoxy, and cutting through the metal-containing epoxy during package singulation; andpatterning the unpatterned metal-containing epoxy layer by removing selected portions of the electrically-conductive layer at one or more surfaces created when cutting through the metal-containing epoxy layer during package singulation, the unpatterned metal-containing epoxy layer patterned to produce a plurality of sidewall conductors interconnecting the microelectronic devices included within the upper and lower package layers.