Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof

A method for fabricating stacked microelectronic packages, comprising:narranging a plurality of microelectronic device panels in a panel stack, each microelectronic device panel containing plurality of microelectronic devices and a plurality of package edge conductors extending therefrom;creating trenches in the panel stack exposing the plurality of package edge conductors;forming a plurality of sidewall conductors interconnecting different ones of the package edge conductors exposed through the trenches, forming comprising:ndepositing an electrically-conductive material into the trenches contacting the plurality of package edge conductors to produce conductor-filled trenches; andremoving selected portions of the electrically-conductive material to produce a series of linearly-spaced vertical openings in each conductor-filled trench, the series of linearly-spaced vertical openings partially defining the plurality of sidewall conductors; andseparating the panel stack into a plurality of stacked microelectronic packages each comprising at least first and second sidewall conductors, the first sidewall conductor electrically isolated from the second sidewall conductor by one of the linearly-spaced vertical openings during removal of selected portions of the electrically-conductive material.

A method for fabricating stacked microelectronic packages, comprising:nstacking at least first and second device panels to produce a panel stack, the first microelectronic device panel comprising:na molded panel body;a plurality of microelectronic devices embedded in the molded panel body;dicing streets bordering the plurality of microelectronic devices; anda plurality of package edge conductors extending from the microelectronic devices to the dicing streets;cutting trenches into the panel stack along the dicing streets exposing the plurality of package edge conductors and at least partially defining one or more sidewalls of each of the plurality of stacked microelectronic packages;filling the trenches with an electrically-conductive material to produce electrically-conductive bodies within the trenches contacting the package edge conductors exposed through the trench sidewalls;forming a plurality of spaced-apart vertical openings in each electrically-conductive bodies to at least partially define a plurality of sidewall conductors electrically-coupled to the plurality of package edge conductors, the plurality of spaced-apart vertical openings extending into the sidewalls of the plurality of stacked microelectronic packages to provide electrical isolation between the neighboring sidewall conductors of each stacked microelectronic package; andafter forming the plurality of spaced-apart vertical openings, singulating the panel stack into the plurality of stacked microelectronic packages to fully define the sidewall conductors and to separate the plurality of stacked microelectronic packages.

A method for fabricating stacked microelectronic packages, comprising:nforming a trench between first and second stacked microelectronic packages extending along a first axis, the first and second stacked microelectronic packages each including a plurality of package edge conductors extending to the trench and a sidewall defined, at least in part, by the trench;filling the trench with an electrically-conductive material to produce a conductor-filled trench;forming linearly-spaced vertical openings in the conductor-filled trench to at least partially define a plurality of sidewall conductors electrically-coupled to the plurality of package edge conductors, the linearly-spaced vertical openings spaced along the first axis and extending into the sidewalls of the first and second stacked microelectronic packages; andsingulating the first and second microelectronic stacked microelectronic packages to fully define the plurality of sidewall conductors and to separate the first and second microelectronic stacked microelectronic packages;wherein at least two first neighboring sidewall conductors included within the first microelectronic package are electrically isolated from one another by removal of material from the conductor-filled trench during formation of the linearly-spaced vertical openings, and wherein at least two second neighboring the sidewall conductors included within the second microelectronic package are electrically isolated from one another by removal of material from the conductor-filled trench during formation of the linearly-spaced vertical openings.