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Inventor

Taber H. Smith

Inventor
Fremont, CA, US

Overview

26→
Patents
2000–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 26 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing35%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
Y02PClimate change mitigation technologies in the production or processing of goods15%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
H10DInorganic electric semiconductor devices3%
B01LChemical or physical laboratory apparatus for general use2%
C12QMeasuring or testing processes involving enzymes, nucleic acids or microorganisms2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H01JElectric discharge tubes or discharge lamps2%
PatentTitleYear
10,549,275Multiplexed biological assay device with electronic readout20208,806,396'Method and system performing circuit design predictions'20148,312,406'Method and system performing RC extraction'20128,302,052'Methods, systems, and computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design'20128,219,944'Method and system performing block-level RC extraction'20128,001,516'Characterization and reduction of variation for integrated circuits'20117,962,867'Electronic design for integrated circuits based on process related variations'20117,757,195'Methods and systems for implementing dummy fill for integrated circuits'20107,712,056'Characterization and verification for integrated circuit designs'20107,393,755'Dummy fill for integrated circuits'20087,383,521'Characterization and reduction of variation for integrated circuits'20087,380,220'Dummy fill for integrated circuits'20087,367,008'Adjustment of masks for integrated circuit fabrication'20087,363,099'Integrated circuit metrology'20087,363,598'Dummy fill for integrated circuits'20087,360,179'Use of models in integrated circuit fabrication'20087,356,783'Dummy fill for integrated circuits'20087,353,475'Electronic design for integrated circuits based on process related variations'20087,325,206'Electronic design for integrated circuits based process related variations'20087,243,316'Test masks for lithographic and etch processes'20077,174,520'Characterization and verification for integrated circuit designs'20077,152,215'Dummy fill for integrated circuits'20067,124,386'Dummy fill for integrated circuits'20067,062,730'Test masks for lithographic and etch processes'20067,039,895'Adjustment of masks for integrated circuit fabrication'20066,153,115'Monitor of plasma processes with multivariate statistical analysis of plasma emission spectra'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000Based in Dallas, TX, US· patent location history
2006–2007Patents assigned to PRAESAGUS INC (4)· patent assignee history
2006–2011Based in Fremont, CA, US· patent location history
2006–2011Based in San Jose, CA, US· patent location history
2008–2014Patents assigned to CADENCE DESIGN SYSTEMS INC (18)· patent assignee history
2012–2014Patents assigned to SMITH TABER (4)· patent assignee history
2012Patents assigned to SONG LI J (2)· patent assignee history
2012Patents assigned to YAO ZHAN-ZHONG (2)· patent assignee history
2012–2020Based in Saratoga, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CADENCE DESIGN SYSTEMS INC182008–2014
PRAESAGUS INC42006–2007
SMITH TABERself42012–2014
SONG LI J22012
YAO ZHAN-ZHONG22012
Locations
LocationPatentsSpan
Fremont, California, US122006–2011
San Jose, California, US82006–2011
Saratoga, California, US52012–2020
Dallas, Texas, US12000