A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process. A location on an integrated circuit is predicted for which a lithography tool would not produce a satisfactory feature dimension without a degree of adjustment of the tool during fabrication to accommodate a focus limitation of the tool, and the design of at least one mask derived from the design is adjusted to enable the lithography tool to produce a satisfactory feature dimension at the locations. A virtual adjustment is effected of a distance of a lithographic tool from a location in a region of a wafer, the virtual adjustment being effected by using a mask having a mask layout that has been generated based on a pattern-dependent model prediction that the location in the region of the wafer would not otherwise have a satisfactory feature dimension due to a focus limitation of the lithographic tool. A pattern-dependent model is used to predict topography variations that will occur in an integrated circuit as a result of processing up to a predetermined lithographic process step, and designs of masks used in the lithographic process step are adjusted to accommodate the topography variations.

Claims

44 · 5 independent · depth 3

44 granted claims

›1.independentA method comprisingnusing a pattern-dependent model of process-induced variation to predict a location on an integrated circuit for which a lithograph…+16

›2.↳ 1The method of claim 1 in which the focus limitation comprises depth of focus.d2

›3.↳ 1The method of claim 1 in which the lithography tool comprises a lithography stepper.d2

›4.↳ 1The method of claim 1 also including using an electronics design automation (EDA) tool in conjunction with at least one of the predicting or the alter…d2

›5.↳ 1The method of claim 1 in which the pattern-dependent model of process-induced variation receives as inputs at least one of the following: layout and d…d2

›6.↳ 1The method of claim 1 in which using the pattern-dependent model of process-induced variation comprises determining if an integrated circuit can be fa…d2

›7.↳ 1The method of claim 1 in which the altering of the design or the at least one mask also produces a satisfactory electrical performance.d2

›8.↳ 1The method of claim 1 in which the location is within a region of the design for which the lithography tool is not to be adjusted during fabrication.d2

›9.↳ 1The method of claim 1 in which the design includes at least one other integrated circuit and the lithography tool is to be adjusted between the one in…d2

›10.↳ 1The method of claim 1 in which the altered design or mask enables the lithography tool to produce a satisfactory feature dimension at the location wit…d2

›11.↳ 1The method of claim 1 in which the feature dimension oomprises line dimension.d2

›12.↳ 1The method of claim 1 in which the feature dimension comprises line spacing.d2

›13.↳ 1The method of claim 1 in which the feature dimension comprises line density.d2

›14.↳ 1The method of claim 1 in which altering the design or the at least one mask comprises altering features in the design or the at least one mask.d2

›15.↳ 1The method of claim 1 in which at least one of the predicting and the altering is provided as a service in a network.d2+1

›17.↳ 1The method of claim 1 in which the features of the integrated circuit comprise current-carrying features.d2

›18.independentA method comprisingneffecting a virtual adjustment of a distance of a lithographic tool from a location in a region of a wafer, the virtual adjustment…+14

›19.↳ 18The method of claim 18 in which the focus limitation comprises a depth-of-field limitation.d2

›20.↳ 18The method of claim 18 also includingnphysically adjusting a distance of the lithographic tool from a region of a wafer on which the lithographic tool…d2

›21.↳ 18The method of claim 18 in which an adjusted mask layout is generated by altering portions of an original mask layout.d2

›22.↳ 18The method of claim 18 in which the region of the wafer comprises a single integrated circuit.d2

›23.↳ 18The method of claim 18 in which the region on the wafer has a dimension that is smaller than a predetermined dimension.d2

›24.↳ 18The method of claim 18 in which the distance of the lithographic tool from the region is physically adjusted based on a mark on the wafer.d2

›25.↳ 18The method of claim 18 also includingneffecting virtual adjustments for other locations in the region of the wafer.d2

›26.↳ 18The method of claim 18 also includingneffecting virtual adjustments for other locations of the wafer outside the region.d2

›27.↳ 18The method of claim 18 in which the feature dimension comprises line dimension.d2

›28.↳ 18The method of claim 18 in which the feature dimension comprises line spacing.d2

›29.↳ 18The method of claim 18 in which the feature dimension comprises line density.d2

›30.↳ 18The method of claim 18 in which access to the pattern-dependent model of process-induced variation is provided as a service in a network.d2+1

›32.↳ 18The method of claim 18 in which the features of the integrated circuit comprise current-carrying features.d2

›33.independentA method comprisingnusing a pattern-dependent model of process-induced variation to predict thickness variations of shapes or patterns of conductive a…+1

›35.independentA method comprisingnusing a pattern-dependent model of process-induced variation to predict thickness variation of shapes or patterns of conductive an…+8

›36.↳ 35The method of claim 35 in which the features of the integrated circuit comprise current-carrying features.d2

›38.↳ 35multiple · 35, 37The method of claim 35 or 37 in which the pattern-dependent model for predicting width variation to which the predicted thickness variation is made av…d2

›39.↳ 35multiple · 35, 37The method of claim 35 or 37 in which the pattern-dependent model for predicting width variation to which the predicted thickness variation is made av…d2

›40.↳ 35multiple · 35, 37The method of claim 35 or 37 also comprising determining if the integrated circuit can be fabricated according to the design using the lithography or …d2

›41.↳ 35multiple · 35, 37The method of claim 35 or 37 in which the adjusting of the design or mask also produces a satisfactory electrical performance.d2

›42.↳ 35multiple · 35, 37The method of claim 35 or 37 in which the adjusting the mask comprises altering dimensions of features in the design or mask.d2

›43.↳ 35multiple · 35, 37The method of claim 35 or 37 in which the pattern-dependent model of process-induced variation is provided as a service in a network.d2+1

›37.independentA method comprisingnproviding a pattern-dependent model of process-induced variation, the pattern-dependent model being configured(1) to predict thick…

Classifications

3 codes

IPC · International Patent Classification

Section G — Physics

G06F17/50

USPC · US Patent Classification

716/19716/21

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3.4 y

1,232 days filing → grant

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non-final + final

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5 RCE

Examiner

Sun James Lin

art unit 2825 · TC 2800

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Type	Document	Date
related publication	US 20030229881 A1	11 Dec 2003

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