Test masks for lithographic and etch processes
Granted 13 Jun 2006 · 6 office actions
Current assignee: Cadence Design Systems, Inc. · originally Praesagus, Inc.
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Inventors: Taber H. Smith, David White · Examiner: Stacy A. Whitmore · AU 2812 · TC 2800
Life of the patent
3 dated eventsAbstract
A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.
Claims
17 · 2 independent · depth 3Classifications
3 codes- G06F17/50
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1 priority documents›Priority documents — 1
| Type | Document | Date |
|---|---|---|
| related publication | US 20030229880 A1 | 11 Dec 2003 |
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