USPatentGranted
B2

Test masks for lithographic and etch processes

Granted 13 Jun 2006 · 6 office actions

Current assignee: Cadence Design Systems, Inc. · originally Praesagus, Inc.

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Inventors: Taber H. Smith, David White · Examiner: Stacy A. Whitmore · AU 2812 · TC 2800

Life of the patent

3 dated events
⤢ drag to zoomJan 2003Jul 2003Jan 2004Jul 2004Jan 2005Jul 2005Jan 2006Jul 2006Prosecution
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Abstract

A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.

Claims

17 · 2 independent · depth 3
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17 granted claims

Classifications

3 codes
IPC · International Patent Classification
Section G — Physics
  • G06F17/50
USPC · US Patent Classification
716/4716/19

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File wrapper

Pendency
3.5 y
1,274 days filing → grant
Office actions
3
non-final + final
Responses
3
2 RCE
Interviews
1
examiner interview summaries
Examiner
Stacy A. Whitmore
art unit 2812 · TC 2800
Citations: 132 back · 0 forward

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Priority chain

1 priority documents
›Priority documents — 1
TypeDocumentDate
related publicationUS 20030229880 A111 Dec 2003

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