Inventor

Gilbert Dewey

Inventor

Hillsboro, OR, US

Overview

2006–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 228 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices34%

H01LSemiconductor devices25%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

B82YSpecific uses or applications of nanostructures7%

H10BElectronic memory devices3%

G11CStatic stores2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

H10NElectric solid-state devices not otherwise provided for1%

C30BSingle-crystal growth0%

PatentTitleYear

11,107,890FINFET transistor having a doped subfin structure to reduce channel to substrate leakage2021 11,101,376Non-planar transition metal dichalcogenide devices2021 11,101,377Transistor device with heterogeneous channel structure bodies and method of providing same2021 11,075,202Bottom fin trim isolation aligned with top gate for stacked device architectures2021 11,075,198Stacked transistor architecture having diverse fin geometry2021 11,049,773Art trench spacers to enable fin release for non-lattice matched channels2021 11,031,503Non-planar gate thin film transistor2021 11,031,482Gate electrode having a capping layer2021 11,017,843Thin film transistors for memory cell array layer selection2021 11,011,550Self-aligned top-gated non-planar oxide semiconductor thin film transistors2021 11,004,982Gate for a transistor2021 10,992,017Semiconductor package comprising chiplets disposed on a substrate which are electromagnetically coupled by dielectric waveguides and a computing networks formed therefrom2021 10,964,992Electromagnetic wave launcher including an electromagnetic waveguide, wherein a millimeter wave signal and a lower frequency signal are respectively launched at different portions of the waveguide2021 10,964,701Vertical shared gate thin-film transistor-based charge storage memory2021 10,964,820Vertical transistor devices and techniques2021 10,957,769High-mobility field effect transistors with wide bandgap fin cladding2021 10,950,733Deep gate-all-around semiconductor device having germanium or group III-V active layer2021 10,950,301Two transistor, one resistor non-volatile gain cell memory and storage element2021 10,930,679Thin film transistors with a crystalline oxide semiconductor source/drain2021 10,930,791Systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in source and drain for low access and contact resistance of thin film transistors2021 10,903,364Semiconductor device with released source and drain2021 10,892,335Device isolation by fixed charge2021 10,886,408Group III-V material transistors employing nitride-based dopant diffusion barrier layer2021 10,879,365Transistors with non-vertical gates2020 10,878,889High retention time memory element with dual gate devices2020 10,872,660Resistive memory devices with transition metal dichalcogenide (TMD) materials as ballast resistors to control current flow through the devices2020 10,861,939Stiff quantum layers to slow and or stop defect propagation2020 10,847,656Fabrication of non-planar IGZO devices for improved electrostatics2020 10,847,619Supperlatice channel included in a trench2020 10,818,799Vertical transistor devices and techniques2020 10,818,793Indium-rich NMOS transistor channels2020 10,811,461Access transmission gate2020 10,797,150Differential work function between gate stack metals to reduce parasitic capacitance2020 10,784,170CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture2020 10,770,593Beaded fin transistor2020 10,756,198Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same2020 10,749,032Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers2020 10,748,900Fin-based III-V/SI or GE CMOS SAGE integration2020 10,734,488Aluminum indium phosphide subfin germanium channel transistors2020 10,734,511High mobility asymmetric field effect transistors with a band-offset semiconductor drain spacer2020 10,727,339Selectively regrown top contact for vertical semiconductor devices2020 10,727,138Integration of single crystalline transistors in back end of line (BEOL)2020 10,707,319Gate electrode having a capping layer2020 10,693,008Cladding layer epitaxy via template engineering for heterogeneous integration on silicon2020 10,665,688Low Schottky barrier contact structure for Ge NMOS2020 10,659,046Local cell-level power gating switch2020 10,651,288Pseudomorphic InGaAs on GaAs for gate-all-around transistors2020 10,651,313Reduced transistor resistance using doped layer2020 10,644,111Strained silicon layer with relaxed underlayer2020 10,644,123Systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors2020 10,644,137III-V finfet transistor with V-groove S/D profile for improved access resistance2020 10,644,140Integrated circuit die having back-end-of-line transistors2020 10,636,912FINFET transistor having a tapered subfin structure2020 10,586,848Apparatus and methods to create an active channel having indium rich side and bottom surfaces2020 10,580,882Low band gap semiconductor devices having reduced gate induced drain leakage (GIDL)2020 10,580,865Transistor with a sub-fin dielectric region under a gate2020 10,573,717Selective epitaxially grown III-V materials based devices2020 10,559,683Apparatus and methods to create a buffer to reduce leakage in microelectronic transistors2020 10,546,858Low damage self-aligned amphoteric FINFET tip doping2020 10,541,305Group III-N nanowire transistors2020 10,529,808Dopant diffusion barrier for source/drain to curb dopant atom diffusion2020 10,497,814III-V semiconductor alloys for use in the subfin of non-planar semiconductor devices and methods of forming the same2019 10,483,353Transistor including tensile-strained germanium channel2019 10,461,193Apparatus and methods to create a buffer which extends into a gated region of a transistor2019 10,461,082Well-based integration of heteroepitaxial N-type transistors with P-type transistors2019 10,446,685High-electron-mobility transistors with heterojunction dopant diffusion barrier2019 10,431,690High electron mobility transistors with localized sub-fin isolation2019 10,411,122Semiconductor device having group III-V material active region and graded gate dielectric2019 10,411,007High mobility field effect transistors with a band-offset semiconductor source/drain spacer2019 10,403,733Dielectric metal oxide cap for channel containing germanium2019 10,388,764High-electron-mobility transistors with counter-doped dopant diffusion barrier2019 10,388,800Thin film transistor with gate stack on multiple sides2019 10,373,977Transistor fin formation via cladding on sacrificial core2019 10,347,767Transistor with a subfin layer2019 10,340,275Stackable thin film memory2019 10,340,374High mobility field effect transistors with a retrograded semiconductor source/drain2019 10,319,646CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture2019 10,290,709Apparatus and methods to create an indium gallium arsenide active channel having indium rich surfaces2019 10,290,614Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits2019 10,263,074High voltage field effect transistors2019 10,263,079Apparatus and methods for forming a modulation doped non-planar transistor2019 10,249,742Offstate parasitic leakage reduction for tunneling field effect transistors2019 10,249,490Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy2019 10,243,078Carrier confinement for high mobility channel devices2019 10,236,369Techniques for forming non-planar germanium quantum well devices2019 10,229,997Indium-rich NMOS transistor channels2019 10,211,208High-mobility semiconductor source/drain spacer2019 10,186,581Group III-N nanowire transistors2019 10,181,518Selective epitaxially grown III-V materials based devices2019 10,096,474Methods and structures to prevent sidewall defects during selective epitaxy2018 10,096,709Aspect ratio trapping (ART) for fabricating vertical semiconductor devices2018 10,090,405Semiconductor device having group III-V material active region and graded gate dielectric2018 10,084,058Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains2018 10,084,043High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin2018 10,074,718Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack2018 10,026,845Deep gate-all-around semiconductor device having germanium or group III-V active layer2018 10,020,371Contact techniques and configurations for reducing parasitic resistance in nanowire transistors2018 9,972,686Germanium tin channel transistors2018 9,947,780High electron mobility transistor (HEMT) and method of fabrication2018 9,934,976Methods of forming low interface resistance rare earth metal contacts and structures formed thereby2018 9,929,273'Apparatus and methods of forming fin structures with asymmetric profile'2018 9,911,835'Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs'2018 9,905,651'GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation'2018 9,899,505'Conductivity improvements for III-V semiconductor devices'2018 9,876,014Germanium-based quantum well devices2018 9,871,106'Heterogeneous pocket for tunneling field effect transistors (TFETs)'2018 9,865,684'Nanoscale structure with epitaxial film having a recessed bottom portion'2018 9,853,107Selective epitaxially grown III-V materials based devices2017 9,818,870'Transistor structure with variable clad/core dimension for stress and bandgap'2017 9,818,847'Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface'2017 9,812,574'Techniques and configurations for stacking transistors of an integrated circuit device'2017 9,799,759'Techniques for forming non-planar germanium quantum well devices'2017 9,768,269'Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same'2017 9,748,338'Preventing isolation leakage in III-V devices'2017 9,698,013'Methods and structures to prevent sidewall defects during selective epitaxy'2017 9,691,857'Group III-N nanowire transistors'2017 9,685,508'High voltage field effect transistors'2017 9,685,381'Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon'2017 9,666,492'CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture'2017 9,666,583'Methods of containing defects for non-silicon device engineering'2017 9,653,548'Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack'2017 9,653,559'Methods to enhance doping concentration in near-surface layers of semiconductors and methods of making same'2017 9,640,622'Selective epitaxially grown III-V materials based devices'2017 9,640,646'Semiconductor device having group III-V material active region and graded gate dielectric'2017 9,640,537'Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy'2017 9,640,671'Deep gate-all-around semiconductor device having germanium or group III-V active layer'2017 9,634,007'Trench confined epitaxially grown device layer(s)'2017 9,583,602'Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs'2017 9,570,614'Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation'2017 9,564,490'Apparatus and methods for forming a modulation doped non-planar transistor'2017 9,478,635'Germanium-based quantum well devices'2016 9,461,141'Contact techniques and configurations for reducing parasitic resistance in nanowire transistors'2016 9,461,160'Non-planar III-N transistor'2016 9,455,150'Conformal thin film deposition of electropositive metal alloy films'2016 9,443,936'Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains'2016 9,437,706'Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes'2016 9,412,872'N-type and P-type tunneling field effect transistors (TFETs)'2016 9,397,188'Group III-N nanowire transistors'2016 9,391,181'Lattice mismatched hetero-epitaxial film'2016 9,343,574'Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack'2016 9,337,291'Deep gate-all-around semiconductor device having germanium or group III-V active layer'2016 9,287,380'Gate electrode having a capping layer'2016 9,263,557'Techniques for forming non-planar germanium quantum well devices'2016 9,257,346'Apparatus and methods for forming a modulation doped non-planar transistor'2016 9,245,989'High voltage field effect transistors'2016 9,240,410'Group III-N nanowire transistors'2016 9,236,476'Techniques and configuration for stacking transistors of an integrated circuit device'2016 9,219,135'Germanium-based quantum well devices'2015 9,153,671'Techniques for forming non-planar germanium quantum well devices'2015 9,136,343'Deep gate-all-around semiconductor device having germanium or group III-V active layer'2015 9,123,567'CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture'2015 9,123,790'Contact techniques and configurations for reducing parasitic resistance in nanowire transistors'2015 9,112,028'Methods of containing defects for non-silicon device engineering'2015 9,054,190'Methods of containing defects for non-silicon device engineering'2015 9,029,835'Epitaxial film on nanoscale structure'2015 9,018,680'Non-planar semiconductor device having active region with multi-dielectric gate stack'2015 8,952,541'Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes'2015 8,936,976'Conductivity improvements for III-V semiconductor devices'2015 8,901,740'Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes'2014 8,890,264'Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface'2014 8,890,118'Tunnel field effect transistor'2014 8,890,120'Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs'2014 8,878,363'Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same'2014 8,872,160'Increasing carrier injection velocity for integrated circuit devices'2014 8,872,225'Defect transferred and lattice mismatched epitaxial film'2014 8,846,480'Carrier mobility in surface-channel transistors, apparatus made therewith, and system containing same'2014 8,823,059'Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack'2014 8,803,255'Gate electrode having a capping layer'2014 8,785,907'Epitaxial film growth on patterned substrate'2014 8,785,909'Non-planar semiconductor device having channel region with low band-gap cladding layer'2014 8,765,563'Trench confined epitaxially grown device layer(s)'2014 8,748,269'Quantum-well-based semiconductor devices'2014 8,716,751'Methods of containing defects for non-silicon device engineering'2014 8,710,490'Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer'2014 8,633,470'Techniques and configurations to impart strain to integrated circuit devices'2014 8,633,471'Apparatus and methods for forming a modulation doped non-planar transistor'2014 8,592,803'Germanium-based quantum well devices'2013 8,575,596'Non-planar germanium quantum well devices'2013 8,536,621'Quantum-well-based semiconductor devices'2013 8,501,508'Method of forming quantum well mosfet channels having uni-axial strains caused by metal source/drains'2013 8,440,998'Increasing carrier injection velocity for integrated circuit devices'2013 8,415,751'Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain'2013 8,390,082'Gate electrode having a capping layer'2013 8,384,128'Carrier mobility in surface-channel transistors, apparatus made therewith, and systems containing same'2013 8,378,334'Low power floating body memory cell based on low-bandgap-material quantum well'2013 8,350,291'Modulation-doped multi-gate devices'2013 8,344,425'Multi-gate III-V quantum well structures'2013 8,344,418'Materials for interfacing high-K dielectric layers with III-V semiconductors'2013 8,324,661'Quantum well transistors with remote counter doping'2012 8,283,653'Non-planar germanium quantum well devices'2012 8,278,687'Semiconductor heterostructures to reduce short channel effects'2012 8,258,543'Quantum-well-based semiconductor devices'2012 8,258,498'Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains'2012 8,227,833'Dual layer gate dielectrics for non-silicon semiconductor devices'2012 8,193,523'Germanium-based quantum well devices'2012 8,148,772'Recessed channel array transistor (RCAT) structures'2012 8,129,749'Double quantum well structures for transistors'2012 8,120,063'Modulation-doped multi-gate devices'2012 8,115,235'Modulation-doped halo in quantum well field-effect transistors, apparatus made therewith, and methods of using same'2012 8,110,877'Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions'2012 8,030,197'Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow'2011 8,022,487'Increasing body dopant uniformity in multi-gate transistor devices'2011 8,021,940'Methods for fabricating PMOS metal gate structures'2011 8,017,933'Compositionally-graded quantum-well channels for semiconductor devices'2011 7,999,298'Embedded memory cell and method of manufacturing same'2011 7,999,351'Phase memorization for low leakage dielectric films'2011 7,968,457'Sandwiched metal structure silicidation for enhanced contact'2011 7,964,866'Low power floating body memory cell based on low bandgap material quantum well'2011 7,947,971'Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains'2011 7,915,642'Apparatus and methods for forming a modulation doped non-planar transistor'2011 7,915,694'Gate electrode having a capping layer'2011 7,898,023'Recessed channel array transistor (RCAT) structures'2011 7,892,902'Group III-V devices with multiple spacer layers'2011 7,888,221'Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions'2011 7,868,318'Quantum well field-effect transistors with composite spacer structures, apparatus made therewith, and methods of using same'2011 7,800,166'Recessed channel array transistor (RCAT) structures and method of formation'2010 7,759,142'Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains'2010 7,736,956'Lateral undercut of metal gate in SOI device'2010 7,709,909'Method for making a semiconductor device having a high-k gate dielectric'2010 7,615,441'Forming high-k dielectric layers on smooth substrates'2009 7,531,404'Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer'2009 7,524,727'Gate electrode having a capping layer'2009 7,465,976'Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions'2008 7,442,983'Method for making a semiconductor device having a high-k gate dielectric'2008 7,402,875'Lateral undercut of metal gate in SOI device'2008 7,323,423'Forming high-k dielectric layers on smooth substrates'2008 7,084,038'Method for making a semiconductor device having a high-k gate dielectric'2006 7,074,680'Method for making a semiconductor device having a high-k gate dielectric'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2021Patents assigned to INTEL CORP (225)· patent assignee history

2006–2021Based in Hillsboro, OR, US· patent location history

2012–2019Patents assigned to DEWEY GILBERT (59)· patent assignee history

2012–2019Patents assigned to RADOSAVLJEVIC MARKO (49)· patent assignee history

2012–2019Patents assigned to PILLARISETTY RAVI (45)· patent assignee history

2012–2019Patents assigned to MUKHERJEE NILOY (35)· patent assignee history

2017–2021Based in Beaverton, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	225	2006–2021
DEWEY GILBERTself	59	2012–2019
RADOSAVLJEVIC MARKO	49	2012–2019
PILLARISETTY RAVI	45	2012–2019
MUKHERJEE NILOY	35	2012–2019

Locations

Location	Patents	Span
Hillsboro, OR, US	197	2006–2021
Beaverton, OR, US	31	2017–2021