An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Claims

15 · 3 independent · depth 3

15 granted claims

›1.independentAn apparatus comprising:na semiconductor device comprising a channel material having a first lattice structure on a well of a well material having a m…+5

›7.independentA method comprising:nforming a well trench in a buffer material of a substrate the well comprising dimensions of a height greater than each of a width…+5

›13.independentA system comprising:na computer comprising a processor electrically coupled to a printed circuit board, the processor comprising complimentary metal o…+2

Classifications

6 codes

IPC · International Patent Classification

Section H — Electricity

H01L21/02
H01L21/84
H01L29/78
H01L27/12
H01L27/092
H01L21/8238

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File wrapper

Pendency

1.1 y

407 days filing → grant

Office actions

none on record

Responses

no RCE

Examiner

David Vu

art unit 2818 · TC 2800

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Citations: 16 back · 0 forward

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Priority chain

1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20140231871 A1	21 Aug 2014

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