Elastic membrane for semiconductor wafer polishing apparatus

FIG. 1 is a top plan view of a first embodiment of an elastic membrane for semiconductor wafer polishing apparatus showing our new design;

FIG. 2 is a bottom plan view thereof;

FIG. 3 is a front side view thereof;

FIG. 4 is a right side view thereof;

FIG. 5 is a left side view thereof;

FIG. 6 is a cross sectional view taken along section line 6 - 6 in FIG. 1 ;

FIG. 7 is an enlarged perspective view of a portion labeled FIG. 7 in FIG. 1 ;

FIG. 8 is an opposite side view of FIG. 7 ;

FIG. 9 is a top plan view of a second embodiment of an elastic membrane for semiconductor wafer polishing apparatus showing our new design;

FIG. 10 is a bottom plan view thereof;

FIG. 11 is a front side view thereof;

FIG. 12 is a right side view thereof;

FIG. 13 is a left side view thereof;

FIG. 14 is a cross sectional view taken along section line 14 - 14 in FIG. 9 ;

FIG. 15 is an enlarged perspective view of a portion labeled FIG. 15 in FIG. 9 ; and,

FIG. 16 is an opposite side view of FIG. 15 .

The broken lines shown in the drawings represent portions of the elastic membrane for semiconductor wafer polishing apparatus that form no part of the claimed design. The dashed-dot-dashed lines represent the boundary lines of the claimed design.

All surfaces not shown form no part of the claimed design.