USPatentGranted
S1

Process tube for manufacturing semiconductor wafers

Granted 17 Feb 2009 · no office action yet

Assignee: Tokyo Electron Limited

Law firm: Law firm · Log in to unlock

Attorney: Attorney · Log in to unlock

Inventors: Atsushi Endo, Hisashi Inoue · Examiner: Selina Sikder · AU 2912 · TC 2900

Application
29/274,293
filed 11 Apr 2007
Publication
Not published
not published
Patent· this page
US D586768
granted 17 Feb 2009

Life of the patent

5 dated events
⤢ drag to zoom20082010201220142016201820202022202420262028ProsecutionOwnershipTerm & fees
ProsecutionOwnershipTerm & feeshover for detail · click to open

Description

1 parts
›FIG. 1 is a front view of the…

FIG. 1 is a front view of the design for a process tube for manufacturing semiconductor wafers in accordance with the invention;

FIG. 2 is a rear view thereof;

FIG. 3 is a right side view thereof;

FIG. 4 is a left side view thereof;

FIG. 5 is a top view thereof;

FIG. 6 is a bottom view thereof;

FIG. 7 is a sectional view thereof along line 7 — 7 of FIG. 5 ;

FIG. 8 is a sectional view thereof along line 8 — 8 of FIG. 5 ;

FIG. 9 is a sectional view thereof along line 9 — 9 of FIG. 1 ; and,

FIG. 10 is a front, perspective view thereof.

In the preferred embodiment, the entire body of the process tube is transparent such that the inside of the tube can be seen. Dash lines show the boundary of the claimed design.

The broken lines define portions of the process tube that form no part of the claimed design.

the grant prints no section headings; every part label below is ours, taken from that part's own first words

Claims

1 · 1 independent · depth 1
1 granted claims

Classifications

1 codes
USPC · US Patent Classification
D13/182

Claim changes

Soon
Coming soonHow the claims changed between publication and grant

See which claims were amended, added or cancelled during examination, with every added and removed word marked.

AmendedAddedCancelledUnchanged

The published claims of this patent are not paired with the granted ones in what we hold.

File wrapper

⤢ drag to zoomApr 2007Jul 2007Oct 2007Jan 2008Apr 2008Jul 2008Oct 2008Jan 2009Apr 2009USPTOApplicantNotice of allowance
USPTOApplicanthover for detail · click to open
Pendency
1.9 y
678 days filing → grant
Office actions
0
none on record
Examiner
Selina Sikder
art unit 2912 · TC 2900
Citations: 10 back · 0 forward

See the full prosecution history — every USPTO and applicant action on this file, in order.

Log in to unlock

Chain of title

⤢ drag to zoom20082010201220142016201820202022202420262028Owner 1
Titlehover for detail · click to open

See the full assignment history — every owner this patent has passed through, with recordation dates and reel/frame numbers.

Log in to unlock

Term & fees

See the term timeline — pendency span, in-force span, the maintenance fees paid and both computed expiry dates.

Log in to unlock

Worldwide family

2 members · 2 offices
US1TW1
this patentIP5 & PCTother officessolid = grantedhover for detail · click to open
Members
2
DOCDB simple family 40349734
Offices
2
US
Granted
1 of 2
grant date present
Non-English titles
1
shown as filed, never translated
›IP5 & PCT — 1 members
OfficePublicationKindPublishedFiledStatusTitle
USthis patentUS-D586768-SS117 Feb 200911 Apr 2007grantedProcess tube for manufacturing semiconductor wafers
›Other offices — 1 members
OfficePublicationKindPublishedFiledStatusTitle
TWTW-D125600-S1S121 Oct 200810 Apr 2007published半導體製造用加工處理管zh

Validity challenges

See the validity challenges on record — reexaminations, IPRs and PGRs, with their institution decisions and outcomes.

Log in to unlock

Citations

See every patent this one cites and every patent that cites it back — publication, assignee, and how each one was found.

Log in to unlock